include/configs/theadorable.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
   4  */
   5
   6 #ifndef _CONFIG_THEADORABLE_H
   7 #define _CONFIG_THEADORABLE_H
   8
   9 /*
  10  * High Level Configuration Options (easy to change)
  11  */
  12
  13 /*
  14  * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
  15  * for DDR ECC byte filling in the SPL before loading the main
  16  * U-Boot into it.
  17  */
  18 #define CONFIG_SYS_TCLK         250000000       /* 250MHz */
  19
  20 /*
  21  * Commands configuration
  22  */
  23
  24 /*
  25  * The debugging version enables USB support via defconfig.
  26  * This version should also enable all other non-production
  27  * interfaces / features.
  28  */
  29
  30 /* I2C */
  31 #define CONFIG_SYS_I2C
  32 #define CONFIG_SYS_I2C_MVTWSI
  33 #define CONFIG_I2C_MVTWSI_BASE0         MVEBU_TWSI_BASE
  34 #define CONFIG_I2C_MVTWSI_BASE1         MVEBU_TWSI1_BASE
  35 #define CONFIG_SYS_I2C_SLAVE            0x0
  36 #define CONFIG_SYS_I2C_SPEED            100000
  37
  38 /* USB/EHCI configuration */
  39 #define CONFIG_EHCI_IS_TDI
  40 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3
  41
  42 /* SPI NOR flash default params, used by sf commands */
  43
  44 /* Environment in SPI NOR flash */
  45 #define CONFIG_ENV_OFFSET               (1 << 20) /* 1MiB in */
  46 #define CONFIG_ENV_SIZE                 (64 << 10) /* 64KiB */
  47 #define CONFIG_ENV_SECT_SIZE            (256 << 10) /* 256KiB sectors */
  48 #define CONFIG_ENV_OVERWRITE
  49
  50 #define PHY_ANEG_TIMEOUT        8000    /* PHY needs a longer aneg time */
  51
  52 #define CONFIG_PREBOOT
  53
  54 /* Keep device tree and initrd in lower memory so the kernel can access them */
  55 #define CONFIG_EXTRA_ENV_SETTINGS       \
  56         "fdt_high=0x10000000\0"         \
  57         "initrd_high=0x10000000\0"
  58
  59 /* SATA support */
  60 #define CONFIG_SYS_SATA_MAX_DEVICE      1
  61 #define CONFIG_LBA48
  62
  63 /* Enable LCD and reserve 512KB from top of memory*/
  64 #define CONFIG_SYS_MEM_TOP_HIDE         0x80000
  65
  66 #define CONFIG_BMP_16BPP
  67 #define CONFIG_BMP_24BPP
  68 #define CONFIG_BMP_32BPP
  69
  70 /* FPGA programming support */
  71 #define CONFIG_FPGA_STRATIX_V
  72
  73 /*
  74  * Bootcounter
  75  */
  76 /* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */
  77 #define BOOTCOUNT_ADDR                  0x1000
  78
  79 /*
  80  * mv-common.h should be defined after CMD configs since it used them
  81  * to enable certain macros
  82  */
  83 #include "mv-common.h"
  84
  85 /*
  86  * Memory layout while starting into the bin_hdr via the
  87  * BootROM:
  88  *
  89  * 0x4000.4000 - 0x4003.4000    headers space (192KiB)
  90  * 0x4000.4030                  bin_hdr start address
  91  * 0x4003.4000 - 0x4004.7c00    BootROM memory allocations (15KiB)
  92  * 0x4007.fffc                  BootROM stack top
  93  *
  94  * The address space between 0x4007.fffc and 0x400f.fff is not locked in
  95  * L2 cache thus cannot be used.
  96  */
  97
  98 /* SPL */
  99 /* Defines for SPL */
 100 #define CONFIG_SPL_TEXT_BASE            0x40004030
 101 #define CONFIG_SPL_MAX_SIZE             ((128 << 10) - 0x4030)
 102
 103 #define CONFIG_SPL_BSS_START_ADDR       (0x40000000 + (128 << 10))
 104 #define CONFIG_SPL_BSS_MAX_SIZE         (16 << 10)
 105
 106 #ifdef CONFIG_SPL_BUILD
 107 #define CONFIG_SYS_MALLOC_SIMPLE
 108 #endif
 109
 110 #define CONFIG_SPL_STACK                (0x40000000 + ((192 - 16) << 10))
 111 #define CONFIG_SPL_BOOTROM_SAVE         (CONFIG_SPL_STACK + 4)
 112
 113 /* SPL related SPI defines */
 114 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x1a000
 115 #define CONFIG_SYS_U_BOOT_OFFS          CONFIG_SYS_SPI_U_BOOT_OFFS
 116
 117 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
 118 #define CONFIG_DDR_FIXED_SIZE           (2 << 20)       /* 2GiB */
 119
 120 #endif /* _CONFIG_THEADORABLE_H */