include/configs/tricorder.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2006-2008
   4  * Texas Instruments.
   5  * Richard Woodruff <r-woodruff2@ti.com>
   6  * Syed Mohammed Khasim <x0khasim@ti.com>
   7  *
   8  * (C) Copyright 2012
   9  * Corscience GmbH & Co. KG
  10  * Thomas Weber <weber@corscience.de>
  11  *
  12  * Configuration settings for the Tricorder board.
  13  */
  14
  15 #ifndef __CONFIG_H
  16 #define __CONFIG_H
  17
  18 #define CONFIG_MACH_TYPE                MACH_TYPE_TRICORDER
  19 /*
  20  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
  21  * 64 bytes before this address should be set aside for u-boot.img's
  22  * header. That is 0x800FFFC0--0x80100000 should not be used for any
  23  * other needs.
  24  */
  25
  26 #include <asm/arch/cpu.h>               /* get chip and board defs */
  27 #include <asm/arch/omap.h>
  28
  29 /* Clock Defines */
  30 #define V_OSCK                          26000000 /* Clock output from T2 */
  31 #define V_SCLK                          (V_OSCK >> 1)
  32
  33 #define CONFIG_MISC_INIT_R
  34
  35 #define CONFIG_CMDLINE_TAG              /* enable passing of ATAGs */
  36 #define CONFIG_SETUP_MEMORY_TAGS
  37 #define CONFIG_INITRD_TAG
  38 #define CONFIG_REVISION_TAG
  39
  40 /* Size of malloc() pool */
  41 #define CONFIG_SYS_MALLOC_LEN           (1024*1024)
  42
  43 /* Hardware drivers */
  44
  45 /* NS16550 Configuration */
  46 #define CONFIG_SYS_NS16550_SERIAL
  47 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  48 #define CONFIG_SYS_NS16550_CLK          48000000 /* 48MHz (APLL96/2) */
  49
  50 /* select serial console configuration */
  51 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  52 #define CONFIG_SERIAL3                  3
  53 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
  54                                         115200}
  55
  56 /* I2C */
  57 #define CONFIG_SYS_I2C
  58
  59
  60 /* EEPROM */
  61 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
  62 #define CONFIG_SYS_EEPROM_BUS_NUM       1
  63
  64 /* TWL4030 */
  65 #define CONFIG_TWL4030_LED
  66
  67 /* Board NAND Info */
  68 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
  69
  70 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
  71                                                         /* to access nand */
  72 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
  73                                                         /* to access nand at */
  74                                                         /* CS0 */
  75 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
  76                                                         /* devices */
  77 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
  78 #define CONFIG_SYS_NAND_MAX_ECCPOS      56
  79
  80 /* needed for ubi */
  81 #define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
  82 #define CONFIG_MTD_PARTITIONS
  83
  84 /* Environment information (this is the common part) */
  85
  86
  87 /* hang() the board on panic() */
  88
  89 /* environment placement (for NAND), is different for FLASHCARD but does not
  90  * harm there */
  91 #define CONFIG_ENV_OFFSET               0x120000    /* env start */
  92 #define CONFIG_ENV_OFFSET_REDUND        0x2A0000    /* redundant env start */
  93 #define CONFIG_ENV_SIZE                 (16 << 10)  /* use 16KiB for env */
  94 #define CONFIG_ENV_RANGE                (384 << 10) /* allow badblocks in env */
  95
  96 /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend
  97  * value can not be used here! */
  98 #define CONFIG_LOADADDR         0x82000000
  99
 100 #define CONFIG_COMMON_ENV_SETTINGS \
 101         "console=ttyO2,115200n8\0" \
 102         "mmcdev=0\0" \
 103         "vram=3M\0" \
 104         "defaultdisplay=lcd\0" \
 105         "kernelopts=mtdoops.mtddev=3\0" \
 106         "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
 107         "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
 108         "commonargs=" \
 109                 "setenv bootargs console=${console} " \
 110                 "${mtdparts} " \
 111                 "${kernelopts} " \
 112                 "vt.global_cursor_default=0 " \
 113                 "vram=${vram} " \
 114                 "omapdss.def_disp=${defaultdisplay}\0"
 115
 116 #define CONFIG_BOOTCOMMAND "run autoboot"
 117
 118 /* specific environment settings for different use cases
 119  * FLASHCARD: used to run a rdimage from sdcard to program the device
 120  * 'NORMAL': used to boot kernel from sdcard, nand, ...
 121  *
 122  * The main aim for the FLASHCARD skin is to have an embedded environment
 123  * which will not be influenced by any data already on the device.
 124  */
 125 #ifdef CONFIG_FLASHCARD
 126 /* the rdaddr is 16 MiB before the loadaddr */
 127 #define CONFIG_ENV_RDADDR       "rdaddr=0x81000000\0"
 128
 129 #define CONFIG_EXTRA_ENV_SETTINGS \
 130         CONFIG_COMMON_ENV_SETTINGS \
 131         CONFIG_ENV_RDADDR \
 132         "autoboot=" \
 133         "run commonargs; " \
 134         "setenv bootargs ${bootargs} " \
 135                 "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \
 136                 "rdinit=/sbin/init; " \
 137         "mmc dev ${mmcdev}; mmc rescan; " \
 138         "fatload mmc ${mmcdev} ${loadaddr} uImage; " \
 139         "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \
 140         "bootm ${loadaddr} ${rdaddr}\0"
 141
 142 #else /* CONFIG_FLASHCARD */
 143
 144 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
 145
 146 #define CONFIG_EXTRA_ENV_SETTINGS \
 147         CONFIG_COMMON_ENV_SETTINGS \
 148         "mmcargs=" \
 149                 "run commonargs; " \
 150                 "setenv bootargs ${bootargs} " \
 151                 "root=/dev/mmcblk0p2 " \
 152                 "rootwait " \
 153                 "rw\0" \
 154         "nandargs=" \
 155                 "run commonargs; " \
 156                 "setenv bootargs ${bootargs} " \
 157                 "root=ubi0:root " \
 158                 "ubi.mtd=7 " \
 159                 "rootfstype=ubifs " \
 160                 "ro\0" \
 161         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 162         "bootscript=echo Running bootscript from mmc ...; " \
 163                 "source ${loadaddr}\0" \
 164         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 165         "mmcboot=echo Booting from mmc ...; " \
 166                 "run mmcargs; " \
 167                 "bootm ${loadaddr}\0" \
 168         "loaduimage_ubi=ubi part ubi; " \
 169                 "ubifsmount ubi:root; " \
 170                 "ubifsload ${loadaddr} /boot/uImage\0" \
 171         "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \
 172         "nandboot=echo Booting from nand ...; " \
 173                 "run nandargs; " \
 174                 "run loaduimage_nand; " \
 175                 "bootm ${loadaddr}\0" \
 176         "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
 177                         "if run loadbootscript; then " \
 178                                 "run bootscript; " \
 179                         "else " \
 180                                 "if run loaduimage; then " \
 181                                         "run mmcboot; " \
 182                                 "else run nandboot; " \
 183                                 "fi; " \
 184                         "fi; " \
 185                 "else run nandboot; fi\0"
 186
 187 #endif /* CONFIG_FLASHCARD */
 188
 189 /* Miscellaneous configurable options */
 190 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 191
 192 #define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0 + 0x00000000)
 193 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + \
 194                                         0x07000000) /* 112 MB */
 195
 196 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0 + 0x02000000)
 197
 198 /*
 199  * OMAP3 has 12 GP timers, they can be driven by the system clock
 200  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 201  * This rate is divided by a local divisor.
 202  */
 203 #define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
 204 #define CONFIG_SYS_PTV                  2 /* Divisor: 2^(PTV+1) => 8 */
 205
 206 /*  Physical Memory Map  */
 207 #define CONFIG_NR_DRAM_BANKS            2 /* CS1 may or may not be populated */
 208 #define PHYS_SDRAM_1                    OMAP34XX_SDRC_CS0
 209 #define PHYS_SDRAM_2                    OMAP34XX_SDRC_CS1
 210
 211 /* NAND and environment organization  */
 212 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 213
 214 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 215 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 216 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
 217 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
 218                                                 CONFIG_SYS_INIT_RAM_SIZE - \
 219                                                 GENERATED_GBL_DATA_SIZE)
 220
 221 /* SRAM config */
 222 #define CONFIG_SYS_SRAM_START           0x40200000
 223 #define CONFIG_SYS_SRAM_SIZE            0x10000
 224
 225 /* Defines for SPL */
 226
 227 #define CONFIG_SPL_NAND_BASE
 228 #define CONFIG_SPL_NAND_DRIVERS
 229 #define CONFIG_SPL_NAND_ECC
 230 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME        "u-boot.img"
 231 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION     1
 232
 233 #define CONFIG_SPL_TEXT_BASE            0x40200000 /*CONFIG_SYS_SRAM_START*/
 234 #define CONFIG_SPL_MAX_SIZE             (SRAM_SCRATCH_SPACE_ADDR - \
 235                                          CONFIG_SPL_TEXT_BASE)
 236
 237 #define CONFIG_SPL_BSS_START_ADDR       0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
 238 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
 239
 240 /* NAND boot config */
 241 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 242 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 243 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 244 #define CONFIG_SYS_NAND_OOBSIZE         64
 245 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128*1024)
 246 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 247 #define CONFIG_SYS_NAND_ECCPOS          {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
 248                                          13, 14, 16, 17, 18, 19, 20, 21, 22, \
 249                                          23, 24, 25, 26, 27, 28, 30, 31, 32, \
 250                                          33, 34, 35, 36, 37, 38, 39, 40, 41, \
 251                                          42, 44, 45, 46, 47, 48, 49, 50, 51, \
 252                                          52, 53, 54, 55, 56}
 253
 254 #define CONFIG_SYS_NAND_ECCSIZE         512
 255 #define CONFIG_SYS_NAND_ECCBYTES        13
 256 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
 257
 258 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 259
 260 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x20000
 261 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x100000
 262
 263 #define CONFIG_SYS_SPL_MALLOC_START     0x80208000
 264 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000        /* 1 MB */
 265
 266 #define CONFIG_SYS_MEMTEST_SCRATCH      0x81000000
 267 #endif /* __CONFIG_H */