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ARM: uniphier: collect SPL CONFIG symbols to the bottom of header
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1 /*
2 * Copyright (C) 2012-2015 Panasonic Corporation
3 * Copyright (C) 2015-2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9 /* U-Boot - Common settings for UniPhier Family */
10
11 #ifndef __CONFIG_UNIPHIER_COMMON_H__
12 #define __CONFIG_UNIPHIER_COMMON_H__
13
14 #define CONFIG_ARMV7_PSCI_1_0
15
16 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
17
18 /*-----------------------------------------------------------------------
19 * MMU and Cache Setting
20 *----------------------------------------------------------------------*/
21
22 /* Comment out the following to enable L1 cache */
23 /* #define CONFIG_SYS_ICACHE_OFF */
24 /* #define CONFIG_SYS_DCACHE_OFF */
25
26 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
27
28 #define CONFIG_TIMESTAMP
29
30 /* FLASH related */
31 #define CONFIG_MTD_DEVICE
32
33 #define CONFIG_SMC911X_32_BIT
34 /* dummy: referenced by examples/standalone/smc911x_eeprom.c */
35 #define CONFIG_SMC911X_BASE 0
36
37 #ifdef CONFIG_MICRO_SUPPORT_CARD
38 #define CONFIG_SMC911X
39 #else
40 #define CONFIG_SYS_NO_FLASH
41 #endif
42
43 #define CONFIG_FLASH_CFI_DRIVER
44 #define CONFIG_SYS_FLASH_CFI
45
46 #define CONFIG_SYS_MAX_FLASH_SECT 256
47 #define CONFIG_SYS_MONITOR_BASE 0
48 #define CONFIG_SYS_MONITOR_LEN 0x00080000 /* 512KB */
49 #define CONFIG_SYS_FLASH_BASE 0
50
51 /*
52 * flash_toggle does not work for our support card.
53 * We need to use flash_status_poll.
54 */
55 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
56
57 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
58
59 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
60
61 /* serial console configuration */
62 #define CONFIG_BAUDRATE 115200
63
64 #define CONFIG_SYS_LONGHELP /* undef to save memory */
65
66 #define CONFIG_CMDLINE_EDITING /* add command line history */
67 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
68 /* Print Buffer Size */
69 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
70 #define CONFIG_SYS_MAXARGS 16 /* max number of command */
71 /* Boot Argument Buffer Size */
72 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
73
74 #define CONFIG_CONS_INDEX 1
75
76 /* #define CONFIG_ENV_IS_NOWHERE */
77 /* #define CONFIG_ENV_IS_IN_NAND */
78 #define CONFIG_ENV_IS_IN_MMC
79 #define CONFIG_ENV_OFFSET 0x80000
80 #define CONFIG_ENV_SIZE 0x2000
81 /* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
82
83 #define CONFIG_SYS_MMC_ENV_DEV 0
84 #define CONFIG_SYS_MMC_ENV_PART 1
85
86 #ifdef CONFIG_ARMV8_MULTIENTRY
87 #define CPU_RELEASE_ADDR 0x80000000
88 #define COUNTER_FREQUENCY 50000000
89 #define CONFIG_GICV3
90 #define GICD_BASE 0x5fe00000
91 #if defined(CONFIG_ARCH_UNIPHIER_LD11)
92 #define GICR_BASE 0x5fe40000
93 #elif defined(CONFIG_ARCH_UNIPHIER_LD20)
94 #define GICR_BASE 0x5fe80000
95 #endif
96 #elif !defined(CONFIG_ARM64)
97 /* Time clock 1MHz */
98 #define CONFIG_SYS_TIMER_RATE 1000000
99 #endif
100
101 #define CONFIG_SYS_MAX_NAND_DEVICE 1
102 #define CONFIG_SYS_NAND_MAX_CHIPS 2
103 #define CONFIG_SYS_NAND_ONFI_DETECTION
104
105 #define CONFIG_NAND_DENALI_ECC_SIZE 1024
106
107 #ifdef CONFIG_ARCH_UNIPHIER_SLD3
108 #define CONFIG_SYS_NAND_REGS_BASE 0xf8100000
109 #define CONFIG_SYS_NAND_DATA_BASE 0xf8000000
110 #else
111 #define CONFIG_SYS_NAND_REGS_BASE 0x68100000
112 #define CONFIG_SYS_NAND_DATA_BASE 0x68000000
113 #endif
114
115 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
116
117 #define CONFIG_SYS_NAND_USE_FLASH_BBT
118 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
119
120 /* USB */
121 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4
122 #define CONFIG_FAT_WRITE
123
124 /* SD/MMC */
125 #define CONFIG_SUPPORT_EMMC_BOOT
126 #define CONFIG_GENERIC_MMC
127
128 /* memtest works on */
129 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
130 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000)
131
132 /*
133 * Network Configuration
134 */
135 #define CONFIG_SERVERIP 192.168.11.1
136 #define CONFIG_IPADDR 192.168.11.10
137 #define CONFIG_GATEWAYIP 192.168.11.1
138 #define CONFIG_NETMASK 255.255.255.0
139
140 #define CONFIG_LOADADDR 0x84000000
141 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
142
143 #define CONFIG_CMDLINE_EDITING /* add command line history */
144
145 #define CONFIG_BOOTCOMMAND "run $bootmode"
146
147 #define CONFIG_ROOTPATH "/nfs/root/path"
148 #define CONFIG_NFSBOOTCOMMAND \
149 "setenv bootargs $bootargs root=/dev/nfs rw " \
150 "nfsroot=$serverip:$rootpath " \
151 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
152 "run __nfsboot"
153
154 #ifdef CONFIG_FIT
155 #define CONFIG_BOOTFILE "fitImage"
156 #define LINUXBOOT_ENV_SETTINGS \
157 "fit_addr=0x00100000\0" \
158 "fit_addr_r=0x84100000\0" \
159 "fit_size=0x00f00000\0" \
160 "norboot=setexpr fit_addr $nor_base + $fit_addr &&" \
161 "bootm $fit_addr\0" \
162 "nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \
163 "bootm $fit_addr_r\0" \
164 "tftpboot=tftpboot $fit_addr_r $bootfile &&" \
165 "bootm $fit_addr_r\0" \
166 "__nfsboot=run tftpboot\0"
167 #else
168 #ifdef CONFIG_ARM64
169 #define CONFIG_BOOTFILE "Image"
170 #define LINUXBOOT_CMD "booti"
171 #define KERNEL_ADDR_R "kernel_addr_r=0x80080000\0"
172 #define KERNEL_SIZE "kernel_size=0x00c00000\0"
173 #define RAMDISK_ADDR "ramdisk_addr=0x00e00000\0"
174 #else
175 #define CONFIG_BOOTFILE "zImage"
176 #define LINUXBOOT_CMD "bootz"
177 #define KERNEL_ADDR_R "kernel_addr_r=0x80208000\0"
178 #define KERNEL_SIZE "kernel_size=0x00800000\0"
179 #define RAMDISK_ADDR "ramdisk_addr=0x00a00000\0"
180 #endif
181 #define LINUXBOOT_ENV_SETTINGS \
182 "fdt_addr=0x00100000\0" \
183 "fdt_addr_r=0x84100000\0" \
184 "fdt_size=0x00008000\0" \
185 "kernel_addr=0x00200000\0" \
186 KERNEL_ADDR_R \
187 KERNEL_SIZE \
188 RAMDISK_ADDR \
189 "ramdisk_addr_r=0x84a00000\0" \
190 "ramdisk_size=0x00600000\0" \
191 "ramdisk_file=rootfs.cpio.uboot\0" \
192 "boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \
193 LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
194 "norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \
195 "setexpr kernel_size $kernel_size / 4 &&" \
196 "cp $kernel_addr $kernel_addr_r $kernel_size &&" \
197 "setexpr ramdisk_addr_r $nor_base + $ramdisk_addr &&" \
198 "setexpr fdt_addr_r $nor_base + $fdt_addr &&" \
199 "run boot_common\0" \
200 "nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
201 "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
202 "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
203 "run boot_common\0" \
204 "tftpboot=tftpboot $kernel_addr_r $bootfile &&" \
205 "tftpboot $ramdisk_addr_r $ramdisk_file &&" \
206 "tftpboot $fdt_addr_r $fdt_file &&" \
207 "run boot_common\0" \
208 "__nfsboot=tftpboot $kernel_addr_r $bootfile &&" \
209 "tftpboot $fdt_addr_r $fdt_file &&" \
210 "setenv ramdisk_addr_r - &&" \
211 "run boot_common\0"
212 #endif
213
214 #define CONFIG_EXTRA_ENV_SETTINGS \
215 "netdev=eth0\0" \
216 "verify=n\0" \
217 "nor_base=0x42000000\0" \
218 "sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&" \
219 "tftpboot $tmp_addr u-boot-spl.bin &&" \
220 "setexpr tmp_addr $nor_base + 0x60000 &&" \
221 "tftpboot $tmp_addr u-boot.bin\0" \
222 "emmcupdate=mmcsetn &&" \
223 "mmc partconf $mmc_first_dev 0 1 1 &&" \
224 "tftpboot u-boot-spl.bin &&" \
225 "mmc write $loadaddr 0 80 &&" \
226 "tftpboot u-boot.bin &&" \
227 "mmc write $loadaddr 80 780\0" \
228 "nandupdate=nand erase 0 0x00100000 &&" \
229 "tftpboot u-boot-spl.bin &&" \
230 "nand write $loadaddr 0 0x00010000 &&" \
231 "tftpboot u-boot.bin &&" \
232 "nand write $loadaddr 0x00010000 0x000f0000\0" \
233 LINUXBOOT_ENV_SETTINGS
234
235 #define CONFIG_SYS_BOOTMAPSZ 0x20000000
236
237 #define CONFIG_SYS_SDRAM_BASE 0x80000000
238 #define CONFIG_NR_DRAM_BANKS 3
239 /* for LD20; the last 64 byte is used for dynamic DDR PHY training */
240 #define CONFIG_SYS_MEM_TOP_HIDE 64
241
242 #define CONFIG_PANIC_HANG
243
244 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)
245
246 /* only for SPL */
247 #if defined(CONFIG_ARM64)
248 #define CONFIG_SPL_TEXT_BASE 0x30000000
249 #elif defined(CONFIG_ARCH_UNIPHIER_SLD3) || \
250 defined(CONFIG_ARCH_UNIPHIER_LD4) || \
251 defined(CONFIG_ARCH_UNIPHIER_SLD8)
252 #define CONFIG_SPL_TEXT_BASE 0x00040000
253 #else
254 #define CONFIG_SPL_TEXT_BASE 0x00100000
255 #endif
256
257 #if defined(CONFIG_ARCH_UNIPHIER_LD11)
258 #define CONFIG_SPL_STACK (0x30014c00)
259 #elif defined(CONFIG_ARCH_UNIPHIER_LD20)
260 #define CONFIG_SPL_STACK (0x3001c000)
261 #else
262 #define CONFIG_SPL_STACK (0x00100000)
263 #endif
264
265 #define CONFIG_SPL_FRAMEWORK
266 #ifdef CONFIG_ARM64
267 #define CONFIG_SPL_BOARD_LOAD_IMAGE
268 #endif
269
270 #define CONFIG_SPL_BOARD_INIT
271
272 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000
273
274 /* subtract sizeof(struct image_header) */
275 #define CONFIG_SYS_UBOOT_BASE (0x60000 - 0x40)
276
277 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
278 #define CONFIG_SPL_MAX_FOOTPRINT 0x10000
279 #define CONFIG_SPL_MAX_SIZE 0x10000
280 #if defined(CONFIG_ARCH_UNIPHIER_LD11)
281 #define CONFIG_SPL_BSS_START_ADDR 0x30012000
282 #elif defined(CONFIG_ARCH_UNIPHIER_LD20)
283 #define CONFIG_SPL_BSS_START_ADDR 0x30016000
284 #endif
285 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000
286
287 #endif /* __CONFIG_UNIPHIER_COMMON_H__ */