include/configs/uniphier.h

   1 /*
   2  * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /* U-boot - Common settings for UniPhier Family */
   8
   9 #ifndef __CONFIG_UNIPHIER_COMMON_H__
  10 #define __CONFIG_UNIPHIER_COMMON_H__
  11
  12 #if defined(CONFIG_MACH_PH1_SLD3)
  13 #define CONFIG_DDR_NUM_CH0 2
  14 #define CONFIG_DDR_NUM_CH1 1
  15 #define CONFIG_DDR_NUM_CH2 1
  16
  17 /* Physical start address of SDRAM */
  18 #define CONFIG_SDRAM0_BASE      0x80000000
  19 #define CONFIG_SDRAM0_SIZE      0x20000000
  20 #define CONFIG_SDRAM1_BASE      0xc0000000
  21 #define CONFIG_SDRAM1_SIZE      0x20000000
  22 #define CONFIG_SDRAM2_BASE      0xc0000000
  23 #define CONFIG_SDRAM2_SIZE      0x10000000
  24 #endif
  25
  26 #if defined(CONFIG_MACH_PH1_LD4)
  27 #define CONFIG_DDR_NUM_CH0 1
  28 #define CONFIG_DDR_NUM_CH1 1
  29
  30 /* Physical start address of SDRAM */
  31 #define CONFIG_SDRAM0_BASE      0x80000000
  32 #define CONFIG_SDRAM0_SIZE      0x10000000
  33 #define CONFIG_SDRAM1_BASE      0x90000000
  34 #define CONFIG_SDRAM1_SIZE      0x10000000
  35 #endif
  36
  37 #if defined(CONFIG_MACH_PH1_PRO4)
  38 #define CONFIG_DDR_NUM_CH0 2
  39 #define CONFIG_DDR_NUM_CH1 2
  40
  41 /* Physical start address of SDRAM */
  42 #define CONFIG_SDRAM0_BASE      0x80000000
  43 #define CONFIG_SDRAM0_SIZE      0x20000000
  44 #define CONFIG_SDRAM1_BASE      0xa0000000
  45 #define CONFIG_SDRAM1_SIZE      0x20000000
  46 #endif
  47
  48 #if defined(CONFIG_MACH_PH1_SLD8)
  49 #define CONFIG_DDR_NUM_CH0 1
  50 #define CONFIG_DDR_NUM_CH1 1
  51
  52 /* Physical start address of SDRAM */
  53 #define CONFIG_SDRAM0_BASE      0x80000000
  54 #define CONFIG_SDRAM0_SIZE      0x10000000
  55 #define CONFIG_SDRAM1_BASE      0x90000000
  56 #define CONFIG_SDRAM1_SIZE      0x10000000
  57 #endif
  58
  59 #define CONFIG_I2C_EEPROM
  60 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  10
  61
  62 /*
  63  * Support card address map
  64  */
  65 #define CONFIG_SUPPORT_CARD_BASE        0x43f00000
  66 #define CONFIG_SUPPORT_CARD_ETHER_BASE  (CONFIG_SUPPORT_CARD_BASE + 0x00000000)
  67 #define CONFIG_SUPPORT_CARD_LED_BASE    (CONFIG_SUPPORT_CARD_BASE + 0x00090000)
  68 #define CONFIG_SUPPORT_CARD_UART_BASE   (CONFIG_SUPPORT_CARD_BASE + 0x000b0000)
  69
  70 #ifdef CONFIG_SYS_NS16550_SERIAL
  71 #define CONFIG_SYS_NS16550
  72 #define CONFIG_SYS_NS16550_COM1         CONFIG_SUPPORT_CARD_UART_BASE
  73 #define CONFIG_SYS_NS16550_CLK          12288000
  74 #define CONFIG_SYS_NS16550_REG_SIZE     -2
  75 #endif
  76
  77 /* TODO: move to Kconfig and device tree */
  78 #if 0
  79 #define CONFIG_SYS_NS16550_SERIAL
  80 #endif
  81
  82 #define CONFIG_SMC911X
  83
  84 #define CONFIG_SMC911X_BASE             CONFIG_SUPPORT_CARD_ETHER_BASE
  85 #define CONFIG_SMC911X_32_BIT
  86
  87 /*-----------------------------------------------------------------------
  88  * MMU and Cache Setting
  89  *----------------------------------------------------------------------*/
  90
  91 /* Comment out the following to enable L1 cache */
  92 /* #define CONFIG_SYS_ICACHE_OFF */
  93 /* #define CONFIG_SYS_DCACHE_OFF */
  94
  95 #define CONFIG_SYS_CACHELINE_SIZE       32
  96
  97 /* Comment out the following to enable L2 cache */
  98 #define CONFIG_UNIPHIER_L2CACHE_ON
  99
 100 #define CONFIG_DISPLAY_CPUINFO
 101 #define CONFIG_DISPLAY_BOARDINFO
 102 #define CONFIG_MISC_INIT_F
 103 #define CONFIG_BOARD_EARLY_INIT_F
 104 #define CONFIG_BOARD_EARLY_INIT_R
 105 #define CONFIG_BOARD_LATE_INIT
 106
 107 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 108
 109 #define CONFIG_TIMESTAMP
 110
 111 /* FLASH related */
 112 #define CONFIG_MTD_DEVICE
 113
 114 /*
 115  * uncomment the following to disable FLASH related code.
 116  */
 117 /* #define CONFIG_SYS_NO_FLASH */
 118
 119 #define CONFIG_FLASH_CFI_DRIVER
 120 #define CONFIG_SYS_FLASH_CFI
 121
 122 #define CONFIG_SYS_MAX_FLASH_SECT       256
 123 #define CONFIG_SYS_MONITOR_BASE         0
 124 #define CONFIG_SYS_FLASH_BASE           0
 125
 126 /*
 127  * flash_toggle does not work for out supoort card.
 128  * We need to use flash_status_poll.
 129  */
 130 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
 131
 132 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 133
 134 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
 135
 136 /* serial console configuration */
 137 #define CONFIG_BAUDRATE                 115200
 138
 139 #define CONFIG_SYS_GENERIC_BOARD
 140
 141 #if !defined(CONFIG_SPL_BUILD)
 142 #define CONFIG_USE_ARCH_MEMSET
 143 #define CONFIG_USE_ARCH_MEMCPY
 144 #endif
 145
 146 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 147
 148 #define CONFIG_CMDLINE_EDITING          /* add command line history     */
 149 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size */
 150 /* Print Buffer Size */
 151 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 152 #define CONFIG_SYS_MAXARGS              16      /* max number of command */
 153 /* Boot Argument Buffer Size */
 154 #define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
 155
 156 #define CONFIG_CONS_INDEX               1
 157
 158 /*
 159  * For NAND booting the environment is embedded in the U-Boot image. Please take
 160  * look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
 161  */
 162 /* #define CONFIG_ENV_IS_IN_NAND */
 163 #define CONFIG_ENV_IS_NOWHERE
 164 #define CONFIG_ENV_SIZE                         0x2000
 165 #define CONFIG_ENV_OFFSET                       0x0
 166 /* #define CONFIG_ENV_OFFSET_REDUND     (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
 167
 168 /* Time clock 1MHz */
 169 #define CONFIG_SYS_TIMER_RATE                   1000000
 170
 171 /*
 172  * By default, ARP timeout is 5 sec.
 173  * The first ARP request does not seem to work.
 174  * So we need to retry ARP request anyway.
 175  * We want to shrink the interval until the second ARP request.
 176  */
 177 #define CONFIG_ARP_TIMEOUT      500UL  /* 0.5 msec */
 178
 179 #define CONFIG_SYS_MAX_NAND_DEVICE                      1
 180 #define CONFIG_SYS_NAND_MAX_CHIPS                       2
 181 #define CONFIG_SYS_NAND_ONFI_DETECTION
 182
 183 #define CONFIG_NAND_DENALI_ECC_SIZE                     1024
 184
 185 #ifdef CONFIG_MACH_PH1_SLD3
 186 #define CONFIG_SYS_NAND_REGS_BASE                       0xf8100000
 187 #define CONFIG_SYS_NAND_DATA_BASE                       0xf8000000
 188 #else
 189 #define CONFIG_SYS_NAND_REGS_BASE                       0x68100000
 190 #define CONFIG_SYS_NAND_DATA_BASE                       0x68000000
 191 #endif
 192
 193 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_DATA_BASE + 0x10)
 194
 195 #define CONFIG_SYS_NAND_USE_FLASH_BBT
 196 #define CONFIG_SYS_NAND_BAD_BLOCK_POS                   0
 197
 198 /* USB */
 199 #define CONFIG_USB_MAX_CONTROLLER_COUNT         2
 200 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      4
 201 #define CONFIG_CMD_FAT
 202 #define CONFIG_FAT_WRITE
 203 #define CONFIG_DOS_PARTITION
 204
 205 /* memtest works on */
 206 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE
 207 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_SDRAM_BASE + 0x01000000)
 208
 209 #define CONFIG_BOOTDELAY                        3
 210 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 211
 212 /*
 213  * Network Configuration
 214  */
 215 #define CONFIG_SERVERIP                 192.168.11.1
 216 #define CONFIG_IPADDR                   192.168.11.10
 217 #define CONFIG_GATEWAYIP                192.168.11.1
 218 #define CONFIG_NETMASK                  255.255.255.0
 219
 220 #define CONFIG_LOADADDR                 0x84000000
 221 #define CONFIG_SYS_LOAD_ADDR            CONFIG_LOADADDR
 222
 223 #define CONFIG_CMDLINE_EDITING          /* add command line history     */
 224
 225 #define CONFIG_BOOTCOMMAND              "run $bootmode"
 226
 227 #define CONFIG_ROOTPATH                 "/nfs/root/path"
 228 #define CONFIG_NFSBOOTCOMMAND                                           \
 229         "setenv bootargs $bootargs root=/dev/nfs rw "                   \
 230         "nfsroot=$serverip:$rootpath "                                  \
 231         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
 232         "tftpboot; bootm;"
 233
 234 #define CONFIG_BOOTARGS         " earlyprintk loglevel=8"
 235
 236 #ifdef CONFIG_FIT
 237 #define CONFIG_BOOTFILE                 "fitImage"
 238 #define LINUXBOOT_ENV_SETTINGS \
 239         "fit_addr=0x00100000\0" \
 240         "fit_addr_r=0x84100000\0" \
 241         "fit_size=0x00f00000\0" \
 242         "norboot=run add_default_bootargs &&" \
 243                 "setexpr fit_addr $nor_base + $fit_addr &&" \
 244                 "bootm $fit_addr\0" \
 245         "nandboot=run add_default_bootargs &&" \
 246                 "nand read $fit_addr_r $fit_addr $fit_size &&" \
 247                 "bootm $fit_addr_r\0" \
 248         "tftpboot=run add_default_bootargs &&" \
 249                 "tftpboot $fit_addr_r $bootfile &&" \
 250                 "bootm $fit_addr_r\0"
 251 #else
 252 #define CONFIG_BOOTFILE                 "uImage"
 253 #define LINUXBOOT_ENV_SETTINGS \
 254         "fdt_addr=0x00100000\0" \
 255         "fdt_addr_r=0x84100000\0" \
 256         "fdt_size=0x00008000\0" \
 257         "fdt_file=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
 258         "kernel_addr=0x00200000\0" \
 259         "kernel_addr_r=0x84200000\0" \
 260         "kernel_size=0x00800000\0" \
 261         "ramdisk_addr=0x00a00000\0" \
 262         "ramdisk_addr_r=0x84a00000\0" \
 263         "ramdisk_size=0x00600000\0" \
 264         "ramdisk_file=rootfs.cpio.uboot\0" \
 265         "norboot=run add_default_bootargs &&" \
 266                 "setexpr kernel_addr $nor_base + $kernel_addr &&" \
 267                 "setexpr ramdisk_addr $nor_base + $ramdisk_addr &&" \
 268                 "setexpr fdt_addr $nor_base + $fdt_addr &&" \
 269                 "bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \
 270         "nandboot=run add_default_bootargs &&" \
 271                 "nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
 272                 "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
 273                 "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
 274                 "bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
 275         "tftpboot=run add_default_bootargs &&" \
 276                 "tftpboot $kernel_addr_r $bootfile &&" \
 277                 "tftpboot $ramdisk_addr_r $ramdisk_file &&" \
 278                 "tftpboot $fdt_addr_r $fdt_file &&" \
 279                 "bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0"
 280 #endif
 281
 282 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 283         "netdev=eth0\0"                                         \
 284         "verify=n\0"                                            \
 285         "norbase=0x42000000\0"                                  \
 286         "nandupdate=nand erase 0 0x00100000 &&"                 \
 287                 "tftpboot u-boot-spl-dtb.bin &&"                \
 288                 "nand write $loadaddr 0 0x00010000 &&"          \
 289                 "tftpboot u-boot-dtb.img &&"                    \
 290                 "nand write $loadaddr 0x00010000 0x000f0000\0"  \
 291         "add_default_bootargs=setenv bootargs $bootargs"        \
 292                 " console=ttyS0,$baudrate\0"                    \
 293         LINUXBOOT_ENV_SETTINGS
 294
 295 /* Open Firmware flat tree */
 296 #define CONFIG_OF_LIBFDT
 297
 298 /* Memory Size & Mapping */
 299 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SDRAM0_BASE
 300
 301 #if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE >= CONFIG_SDRAM1_BASE
 302 /* Thre is no memory hole */
 303 #define CONFIG_NR_DRAM_BANKS            1
 304 #define CONFIG_SYS_SDRAM_SIZE   (CONFIG_SDRAM0_SIZE + CONFIG_SDRAM1_SIZE)
 305 #else
 306 #define CONFIG_NR_DRAM_BANKS            2
 307 #define CONFIG_SYS_SDRAM_SIZE   (CONFIG_SDRAM0_SIZE)
 308 #endif
 309
 310 #if defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_LD4) || \
 311         defined(CONFIG_MACH_PH1_SLD8)
 312 #define CONFIG_SPL_TEXT_BASE            0x00040000
 313 #endif
 314 #if defined(CONFIG_MACH_PH1_PRO4)
 315 #define CONFIG_SPL_TEXT_BASE            0x00100000
 316 #endif
 317
 318 #define CONFIG_SPL_STACK                (0x0ff08000)
 319 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_TEXT_BASE)
 320
 321 #define CONFIG_PANIC_HANG
 322
 323 #define CONFIG_SPL_FRAMEWORK
 324 #define CONFIG_SPL_SERIAL_SUPPORT
 325 #define CONFIG_SPL_NAND_SUPPORT
 326
 327 #define CONFIG_SPL_LIBCOMMON_SUPPORT    /* for mem_malloc_init */
 328 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 329
 330 #define CONFIG_SPL_BOARD_INIT
 331
 332 #define CONFIG_SYS_NAND_U_BOOT_OFFS             0x10000
 333
 334 #define CONFIG_SPL_MAX_FOOTPRINT                0x10000
 335
 336 #endif /* __CONFIG_UNIPHIER_COMMON_H__ */