include/configs/utx8245.h

   1 /*
   2  * (C) Copyright 2001
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2002
   6  * Gregory E. Allen, gallen@arlut.utexas.edu
   7  * Matthew E. Karger, karger@arlut.utexas.edu
   8  * Applied Research Laboratories, The University of Texas at Austin
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 /*
  30  *
  31  * Configuration settings for the utx8245 board.
  32  *
  33  */
  34
  35 /* ------------------------------------------------------------------------- */
  36
  37 /*
  38  * board/config.h - configuration options, board specific
  39  */
  40
  41 #ifndef __CONFIG_H
  42 #define __CONFIG_H
  43
  44 /*
  45  * High Level Configuration Options
  46  * (easy to change)
  47  */
  48
  49 #define CONFIG_MPC824X          1
  50 #define CONFIG_MPC8245          1
  51 #define CONFIG_UTX8245          1
  52 #define DEBUG                           1
  53
  54 #define CONFIG_IDENT_STRING     " [UTX5] "
  55
  56 #define CONFIG_CONS_INDEX       1
  57 #define CONFIG_BAUDRATE         57600
  58 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
  59
  60 #define CONFIG_BOOTDELAY        2
  61 #define CONFIG_AUTOBOOT_PROMPT  "autoboot in %d seconds\n"
  62 #define CONFIG_BOOTCOMMAND      "run nfsboot"   /* autoboot command     */
  63 #define CONFIG_BOOTARGS         "root=/dev/ram console=ttyS0,57600" /* RAMdisk */
  64 #define CONFIG_ETHADDR          00:AA:00:14:00:05       /* UTX5 */
  65 #define CONFIG_SERVERIP         10.8.17.105     /* Spree */
  66 #define CFG_TFTP_LOADADDR       10000
  67
  68 #define CONFIG_EXTRA_ENV_SETTINGS \
  69         "kernel_addr=FFA00000\0" \
  70         "ramdisk_addr=FF800000\0" \
  71         "u-boot_startaddr=FFB00000\0" \
  72         "u-boot_endaddr=FFB2FFFF\0" \
  73         "nfsargs=setenv bootargs console=ttyS0,$(baudrate) root=/dev/nfs rw \
  74 nfsroot=$(nfsrootip):$(rootpath) ip=dhcp\0" \
  75         "ramargs=setenv bootargs console=ttyS0,$(baudrate) root=/dev/ram0\0" \
  76         "smargs=setenv bootargs console=ttyS0,$(baudrate) root=/dev/mtdblock1 ro\0" \
  77         "fwargs=setenv bootargs console=ttyS0,$(baudrate) root=/dev/sda2 ro\0" \
  78         "nfsboot=run nfsargs;bootm $(kernel_addr)\0" \
  79         "ramboot=run ramargs;bootm $(kernel_addr) $(ramdisk_addr)\0" \
  80         "smboot=run smargs;bootm $(kernel_addr) $(ramdisk_addr)\0" \
  81         "fwboot=run fwargs;bootm $(kernel_addr) $(ramdisk_addr)\0" \
  82         "update_u-boot=tftp $(loadaddr) /bdi2000/u-boot.bin;protect off \
  83 $(u-boot_startaddr) $(u-boot_endaddr);era $(u-boot_startaddr) \
  84 $(u-boot_endaddr);cp.b $(loadaddr) $(u-boot_startaddr) $(filesize);\
  85 protect on $(u-boot_startaddr) $(u-boot_endaddr)"
  86
  87 #define CONFIG_ENV_OVERWRITE
  88
  89 #define CONFIG_COMMANDS         (CFG_CMD_DFL | CFG_CMD_BDI | CFG_CMD_PCI \
  90                                                                 | CFG_CMD_FLASH | CFG_CMD_MEMORY \
  91                                                                 | CFG_CMD_ENV | CFG_CMD_CONSOLE \
  92                                                                 | CFG_CMD_LOADS | CFG_CMD_LOADB \
  93                                                                 | CFG_CMD_IMI | CFG_CMD_CACHE \
  94                                                                 | CFG_CMD_RUN | CFG_CMD_ECHO \
  95                                                                 | CFG_CMD_REGINFO | CFG_CMD_NET\
  96                                                                 | CFG_CMD_DHCP | CFG_CMD_I2C \
  97                                                                 | CFG_CMD_DATE)
  98
  99 /* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
 100  */
 101 #include <cmd_confdefs.h>
 102
 103
 104 /*
 105  * Miscellaneous configurable options
 106  */
 107 #define CFG_LONGHELP                            /* undef to save memory         */
 108 #define CFG_PROMPT      "=> "                   /* Monitor Command Prompt       */
 109 #define CFG_CBSIZE      256                             /* Console I/O Buffer Size      */
 110
 111 /* Print Buffer Size */
 112 #define CFG_PBSIZE      (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
 113
 114 #define CFG_MAXARGS     16              /* max number of command args   */
 115 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 116 #define CFG_LOAD_ADDR   0x00100000      /* Default load address         */
 117
 118
 119 /*-----------------------------------------------------------------------
 120  * PCI configuration
 121  *-----------------------------------------------------------------------
 122  */
 123 #define CONFIG_PCI                              /* include pci support          */
 124 #undef CONFIG_PCI_PNP
 125 #define CONFIG_PCI_SCAN_SHOW
 126 #define CONFIG_NET_MULTI
 127 #define CONFIG_EEPRO100
 128 #define CFG_RX_ETH_BUFFER       8               /* use 8 rx buffer on eepro100  */
 129 #define CONFIG_EEPRO100_SROM_WRITE
 130
 131 #define PCI_ENET0_IOADDR        0xF0000000
 132 #define PCI_ENET0_MEMADDR       0xF0000000
 133
 134 #define PCI_FIREWIRE_IOADDR             0xF1000000
 135 #define PCI_FIREWIRE_MEMADDR    0xF1000000
 136 /*
 137 #define PCI_ENET0_IOADDR        0xFE000000
 138 #define PCI_ENET0_MEMADDR       0x80000000
 139
 140 #define PCI_FIREWIRE_IOADDR     0x81000000
 141 #define PCI_FIREWIRE_MEMADDR    0x81000000
 142 */
 143
 144 /*-----------------------------------------------------------------------
 145  * Start addresses for the final memory configuration
 146  * (Set up by the startup code)
 147  * Please note that CFG_SDRAM_BASE _must_ start at 0
 148  */
 149 #define CFG_SDRAM_BASE      0x00000000
 150 #define CFG_MAX_RAM_SIZE    0x10000000  /* 256MB  */
 151 /*#define CFG_VERY_BIG_RAM      1 */
 152
 153 /* FLASH_BASE is FF800000, with 4MB on RCS0, but the reset vector
 154  * is actually located at FFF00100.  Therefore, U-Boot is
 155  * physically located at 0xFFB0_0000, but is also mirrored at
 156  * 0xFFF0_0000.
 157  */
 158 #define CFG_RESET_ADDRESS   0xFFF00100
 159
 160 #define CFG_EUMB_ADDR       0xFC000000
 161
 162 #define CFG_MONITOR_BASE    TEXT_BASE
 163
 164 #define CFG_MONITOR_LEN     (256 << 10) /* Reserve 256 kB for Monitor   */
 165 #define CFG_MALLOC_LEN      (128 << 10) /* Reserve 128 kB for malloc()  */
 166
 167 /*#define CFG_DRAM_TEST         1 */
 168 #define CFG_MEMTEST_START   0x00003000  /* memtest works on     0...256 MB      */
 169 #define CFG_MEMTEST_END     0x0ff8ffa7  /* in SDRAM, skips exception */
 170                                                                                 /* vectors and U-Boot */
 171
 172
 173 /*--------------------------------------------------------------------
 174  * Definitions for initial stack pointer and data area
 175  *------------------------------------------------------------------*/
 176 #define CFG_INIT_DATA_SIZE    128       /* Size in bytes reserved for */
 177                                                                         /* initial data */
 178 #define CFG_INIT_RAM_ADDR     0x40000000
 179 #define CFG_INIT_RAM_END      0x1000
 180 #define CFG_INIT_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
 181 #define CFG_GBL_DATA_SIZE       128
 182 #define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 183
 184 /*--------------------------------------------------------------------
 185  * NS16550 Configuration
 186  *------------------------------------------------------------------*/
 187 #define CFG_NS16550
 188 #define CFG_NS16550_SERIAL
 189
 190 #define CFG_NS16550_REG_SIZE    1
 191
 192 #if (CONFIG_CONS_INDEX == 1 || CONFIG_CONS_INDEX == 2)
 193 #       define CFG_NS16550_CLK          get_bus_freq(0)
 194 #else
 195 #       define CFG_NS16550_CLK 33000000
 196 #endif
 197
 198 #define CFG_NS16550_COM1        (CFG_EUMB_ADDR + 0x4500)
 199 #define CFG_NS16550_COM2        (CFG_EUMB_ADDR + 0x4600)
 200 #define CFG_NS16550_COM3        0xFF000000
 201 #define CFG_NS16550_COM4        0xFF000008
 202
 203 /*--------------------------------------------------------------------
 204  * Low Level Configuration Settings
 205  * (address mappings, register initial values, etc.)
 206  * You should know what you are doing if you make changes here.
 207  * For the detail description refer to the MPC8240 user's manual.
 208  *------------------------------------------------------------------*/
 209
 210 #define CONFIG_SYS_CLK_FREQ  33000000
 211 #define CFG_HZ                          1000
 212
 213 /*#define CFG_ETH_DEV_FN             0x7800 */
 214 /*#define CFG_ETH_IOBASE             0x00104000 */
 215
 216 /*--------------------------------------------------------------------
 217  * I2C Configuration
 218  *------------------------------------------------------------------*/
 219 #if 1
 220 #define CONFIG_HARD_I2C         1               /* To enable I2C support        */
 221 #undef  CONFIG_SOFT_I2C                         /* I2C bit-banged               */
 222 #define CFG_I2C_SPEED           400000          /* I2C speed and slave address  */
 223 #define CFG_I2C_SLAVE           0x7F
 224 #endif
 225
 226 #define CONFIG_RTC_PCF8563      1               /* enable I2C support for */
 227                                                                         /* Philips PCF8563 RTC */
 228 #define CFG_I2C_RTC_ADDR        0x51    /* Philips PCF8563 RTC address */
 229
 230 /*--------------------------------------------------------------------
 231  *      Memory Control Configuration Register values
 232  *      - see sec. 4.12 of MPC8245 UM
 233  *------------------------------------------------------------------*/
 234
 235 /**** MCCR1 ****/
 236 #define CFG_ROMNAL          0
 237 #define CFG_ROMFAL          10          /* (tacc=70ns)*mem_freq - 2,
 238                                                                         mem_freq = 100MHz */
 239
 240 #define CFG_BANK7_ROW   0               /* SDRAM bank 7-0 row address */
 241 #define CFG_BANK6_ROW   0               /*      bit count */
 242 #define CFG_BANK5_ROW   0
 243 #define CFG_BANK4_ROW   0
 244 #define CFG_BANK3_ROW   0
 245 #define CFG_BANK2_ROW   0
 246 #define CFG_BANK1_ROW   2
 247 #define CFG_BANK0_ROW   2
 248
 249 /**** MCCR2, refresh interval clock cycles ****/
 250 #define CFG_REFINT          480     /* 33 MHz SDRAM clock was 480 */
 251
 252 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
 253 #define CFG_BSTOPRE         1023        /* burst to precharge[0..9], */
 254                                                                 /* sets open page interval */
 255
 256 /**** MCCR3 ****/
 257 #define CFG_REFREC          7       /* Refresh to activate interval, trc */
 258
 259 /**** MCCR4 ****/
 260 #define CFG_PRETOACT        2       /* trp */
 261 #define CFG_ACTTOPRE        7       /* trcd + (burst length - 1) + trdl */
 262 #define CFG_SDMODE_CAS_LAT  3       /* SDMODE CAS latancy */
 263 #define CFG_SDMODE_WRAP     0       /* SDMODE wrap type, sequential */
 264 #define CFG_ACTORW              2               /* trcd min */
 265 #define CFG_DBUS_SIZE2          1               /* set for 8-bit RCS1, clear for 32,64 */
 266 #define CFG_REGISTERD_TYPE_BUFFER 1
 267 #define CFG_EXTROM          0                   /* we don't need extended ROM space */
 268 #define CFG_REGDIMM         0
 269
 270 /* calculate according to formula in sec. 6-22 of 8245 UM */
 271 #define CFG_PGMAX           50          /* how long the 8245 retains the */
 272                                                                         /* currently accessed page in memory */
 273                                                                         /* was 45 */
 274
 275 #define CFG_SDRAM_DSCD  0x20    /* SDRAM data in sample clock delay - note */
 276                                                                 /* bits 7,6, and 3-0 MUST be 0 */
 277
 278 #if 0
 279 #define CFG_DLL_MAX_DELAY       0x04
 280 #else
 281 #define CFG_DLL_MAX_DELAY       0
 282 #endif
 283 #if 0                                                   /* need for 33MHz SDRAM */
 284 #define CFG_DLL_EXTEND  0x80
 285 #else
 286 #define CFG_DLL_EXTEND  0
 287 #endif
 288 #define CFG_PCI_HOLD_DEL 0x20
 289
 290
 291 /* Memory bank settings.
 292  * Only bits 20-29 are actually used from these values to set the
 293  * start/end addresses. The upper two bits will always be 0, and the lower
 294  * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
 295  * address. Refer to the MPC8245 user manual.
 296  */
 297
 298 #define CFG_BANK0_START     0x00000000
 299 #define CFG_BANK0_END       (CFG_MAX_RAM_SIZE/2 - 1)
 300 #define CFG_BANK0_ENABLE    1
 301 #define CFG_BANK1_START     CFG_MAX_RAM_SIZE/2
 302 #define CFG_BANK1_END       (CFG_MAX_RAM_SIZE - 1)
 303 #define CFG_BANK1_ENABLE    1
 304 #define CFG_BANK2_START     0x3ff00000          /* not available in this design */
 305 #define CFG_BANK2_END       0x3fffffff
 306 #define CFG_BANK2_ENABLE    0
 307 #define CFG_BANK3_START     0x3ff00000
 308 #define CFG_BANK3_END       0x3fffffff
 309 #define CFG_BANK3_ENABLE    0
 310 #define CFG_BANK4_START     0x3ff00000
 311 #define CFG_BANK4_END       0x3fffffff
 312 #define CFG_BANK4_ENABLE    0
 313 #define CFG_BANK5_START     0x3ff00000
 314 #define CFG_BANK5_END       0x3fffffff
 315 #define CFG_BANK5_ENABLE    0
 316 #define CFG_BANK6_START     0x3ff00000
 317 #define CFG_BANK6_END       0x3fffffff
 318 #define CFG_BANK6_ENABLE    0
 319 #define CFG_BANK7_START     0x3ff00000
 320 #define CFG_BANK7_END       0x3fffffff
 321 #define CFG_BANK7_ENABLE    0
 322
 323 /*--------------------------------------------------------------------*/
 324 /* 4.4 - Output Driver Control Register */
 325 /*--------------------------------------------------------------------*/
 326 #define CFG_ODCR            0xe5
 327
 328 /*--------------------------------------------------------------------*/
 329 /* 4.8 - Error Handling Registers */
 330 /*-------------------------------CFG_SDMODE_BURSTLEN-------------------------------------*/
 331 #define CFG_ERRENR1     0x11    /* enable SDRAM refresh overflow error */
 332
 333 /* SDRAM 0-256 MB */
 334 #define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 335 /*#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT) */
 336 #define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 337
 338 /* stack in dcache */
 339 #define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
 340 #define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 341
 342
 343 #define CFG_IBAT2L  (CFG_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
 344 #define CFG_IBAT2U  (CFG_SDRAM_BASE + 0x10000000| BATU_BL_256M | BATU_VS | BATU_VP)
 345
 346 /* PCI memory */
 347 /*#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) */
 348 /*#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) */
 349
 350 /*Flash, config addrs, etc. */
 351 #define CFG_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 352 #define CFG_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 353
 354 #define CFG_DBAT0L  CFG_IBAT0L
 355 #define CFG_DBAT0U  CFG_IBAT0U
 356 #define CFG_DBAT1L  CFG_IBAT1L
 357 #define CFG_DBAT1U  CFG_IBAT1U
 358 #define CFG_DBAT2L  CFG_IBAT2L
 359 #define CFG_DBAT2U  CFG_IBAT2U
 360 #define CFG_DBAT3L  CFG_IBAT3L
 361 #define CFG_DBAT3U  CFG_IBAT3U
 362
 363 /*
 364  * For booting Linux, the board info and command line data
 365  * have to be in the first 8 MB of memory, since this is
 366  * the maximum mapped by the Linux kernel during initialization.
 367  */
 368 #define CFG_BOOTMAPSZ       (8 << 20)   /* Initial Memory map for Linux */
 369
 370 /*-----------------------------------------------------------------------
 371  * FLASH organization
 372  *----------------------------------------------------------------------*/
 373 #define CFG_FLASH_BASE      0xFF800000
 374 #define CFG_MAX_FLASH_BANKS     1                       /* Max number of flash banks */
 375
 376 /*      NOTE: environment is not EMBEDDED in the u-boot code.
 377         It's stored in flash in its own separate sector.  */
 378 #define CFG_ENV_IS_IN_FLASH         1
 379
 380 #if 1   /* AMD AM29LV033C */
 381 #define CFG_MAX_FLASH_SECT      64              /* Max number of sectors in one bank */
 382 #define CFG_ENV_ADDR            0xFFBF0000      /* flash sector SA63 */
 383 #define CFG_ENV_SECT_SIZE       (64*1024)       /* Size of the Environment Sector */
 384 #else   /* AMD AM29LV116D */
 385 #define CFG_MAX_FLASH_SECT      35      /* Max number of sectors in one bank */
 386 #define CFG_ENV_ADDR            0xFF9FA000      /* flash sector SA33 */
 387 #define CFG_ENV_SECT_SIZE       (8*1024)        /* Size of the Environment Sector */
 388 #endif /* #if */
 389
 390 #define CFG_ENV_SIZE            CFG_ENV_SECT_SIZE               /* Size of the Environment */
 391 #define CFG_ENV_OFFSET          0                       /* starting right at the beginning */
 392
 393 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 394 #define CFG_FLASH_WRITE_TOUT    500             /* Timeout for Flash Write (in ms)      */
 395
 396 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
 397 #undef CFG_RAMBOOT
 398 #else
 399 #define CFG_RAMBOOT
 400 #endif
 401
 402
 403 /*-----------------------------------------------------------------------
 404  * Cache Configuration
 405  */
 406 #define CFG_CACHELINE_SIZE      32
 407 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 408 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value        */
 409 #endif
 410
 411 /*
 412  * Internal Definitions
 413  *
 414  * Boot Flags
 415  */
 416 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH     */
 417 #define BOOTFLAG_WARM           0x02    /* Software reboot                      */
 418
 419
 420 #endif  /* __CONFIG_H */