include/configs/v38b.h

   1 /*
   2  * (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering,
   3  * wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this project.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the Free
   9  * Software Foundation; either version 2 of the License, or (at your option)
  10  * any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15  * for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, write to the Free Software Foundation, Inc., 59
  19  * Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20  */
  21
  22 #ifndef __CONFIG_H
  23 #define __CONFIG_H
  24
  25 /*
  26  * High Level Configuration Options
  27  * (easy to change)
  28  */
  29 #define CONFIG_MPC5xxx                  1       /* This is an MPC5xxx CPU */
  30 #define CONFIG_MPC5200                  1       /* This is an MPC5200 CPU */
  31 #define CONFIG_V38B                     1       /* ...on V38B board */
  32 #define CFG_MPC5XXX_CLKIN       33000000        /* ...running at 33.000000MHz */
  33
  34 #define CONFIG_RTC_PCF8563              1       /* has PCF8563 RTC */
  35 #define CONFIG_MPC5200_DDR              1       /* has DDR SDRAM */
  36
  37 #undef CONFIG_HW_WATCHDOG                       /* don't use watchdog */
  38
  39 #define CONFIG_NETCONSOLE               1
  40
  41 #define CONFIG_BOARD_EARLY_INIT_R       1       /* do board-specific init */
  42 #define CONFIG_BOARD_EARLY_INIT_F       1       /* do board-specific init */
  43
  44 #define CFG_XLB_PIPELINING              1       /* gives better performance */
  45
  46 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH  */
  47 #define BOOTFLAG_WARM           0x02    /* Software reboot */
  48
  49 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
  50
  51 /*
  52  * Serial console configuration
  53  */
  54 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1 */
  55 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
  56 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
  57
  58 /*
  59  * DDR
  60  */
  61 #define SDRAM_DDR               1       /* is DDR */
  62 /* Settings for XLB = 132 MHz */
  63 #define SDRAM_MODE              0x018D0000
  64 #define SDRAM_EMODE             0x40090000
  65 #define SDRAM_CONTROL           0x704f0f00
  66 #define SDRAM_CONFIG1           0x73722930
  67 #define SDRAM_CONFIG2           0x47770000
  68 #define SDRAM_TAPDELAY          0x10000000
  69
  70 /*
  71  * PCI - no suport
  72  */
  73 #undef CONFIG_PCI
  74
  75 /*
  76  * Partitions
  77  */
  78 #define CONFIG_MAC_PARTITION    1
  79 #define CONFIG_DOS_PARTITION    1
  80
  81 /*
  82  * USB
  83  */
  84 #define CONFIG_USB_OHCI
  85 #define CONFIG_USB_STORAGE
  86 #define CONFIG_USB_CLOCK        0x0001BBBB
  87 #define CONFIG_USB_CONFIG       0x00001000
  88
  89
  90 /*
  91  * BOOTP options
  92  */
  93 #define CONFIG_BOOTP_BOOTFILESIZE
  94 #define CONFIG_BOOTP_BOOTPATH
  95 #define CONFIG_BOOTP_GATEWAY
  96 #define CONFIG_BOOTP_HOSTNAME
  97
  98
  99 /*
 100  * Command line configuration.
 101  */
 102 #include <config_cmd_default.h>
 103
 104 #define CONFIG_CMD_FAT
 105 #define CONFIG_CMD_I2C
 106 #define CONFIG_CMD_IDE
 107 #define CONFIG_CMD_PING
 108 #define CONFIG_CMD_DHCP
 109 #define CONFIG_CMD_DIAG
 110 #define CONFIG_CMD_IRQ
 111 #define CONFIG_CMD_JFFS2
 112 #define CONFIG_CMD_MII
 113 #define CONFIG_CMD_SDRAM
 114 #define CONFIG_CMD_DATE
 115 #define CONFIG_CMD_USB
 116 #define CONFIG_CMD_FAT
 117
 118
 119 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
 120
 121 /*
 122  * Boot low with 16 MB Flash
 123  */
 124 #define CFG_LOWBOOT             1
 125 #define CFG_LOWBOOT16           1
 126
 127 /*
 128  * Autobooting
 129  */
 130 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds */
 131
 132 #define CONFIG_PREBOOT  "echo;" \
 133         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 134         "echo"
 135
 136 #undef CONFIG_BOOTARGS
 137
 138 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 139         "bootcmd=run net_nfs\0"                                         \
 140         "bootdelay=3\0"                                                 \
 141         "baudrate=115200\0"                                             \
 142         "preboot=echo;echo Type \"run flash_nfs\" to mount root "       \
 143                 "filesystem over NFS; echo\0"                           \
 144         "netdev=eth0\0"                                                 \
 145         "ramargs=setenv bootargs root=/dev/ram rw wdt=off \0"           \
 146         "addip=setenv bootargs $(bootargs) "                            \
 147                 "ip=$(ipaddr):$(serverip):$(gatewayip):"                \
 148                 "$(netmask):$(hostname):$(netdev):off panic=1\0"        \
 149         "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0"            \
 150         "flash_self=run ramargs addip;bootm $(kernel_addr) "            \
 151                 "$(ramdisk_addr)\0"                                     \
 152         "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"     \
 153         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 154                 "nfsroot=$(serverip):$(rootpath) wdt=off\0"             \
 155         "hostname=v38b\0"                                               \
 156         "ethact=FEC ETHERNET\0"                                         \
 157         "rootpath=/opt/eldk-3.1.1/ppc_6xx\0"                            \
 158         "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; "    \
 159                 "cp.b 200000 ff000000 $(filesize);"                     \
 160                 "prot on ff000000 ff03ffff\0"                           \
 161         "load=tftp 200000 $(u-boot)\0"                                  \
 162         "netmask=255.255.0.0\0"                                         \
 163         "ipaddr=192.168.160.18\0"                                       \
 164         "serverip=192.168.1.1\0"                                        \
 165         "ethaddr=00:e0:ee:00:05:2e\0"                                   \
 166         "bootfile=/tftpboot/v38b/uImage\0"                              \
 167         "u-boot=/tftpboot/v38b/u-boot.bin\0"                            \
 168         ""
 169
 170 #define CONFIG_BOOTCOMMAND      "run net_nfs"
 171
 172 #if defined(CONFIG_MPC5200)
 173 /*
 174  * IPB Bus clocking configuration.
 175  */
 176 #undef CFG_IPBCLK_EQUALS_XLBCLK                 /* define for 133MHz speed */
 177 #endif
 178
 179 /*
 180  * I2C configuration
 181  */
 182 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 183 #define CFG_I2C_MODULE          2       /* Select I2C module #1 or #2 */
 184 #define CFG_I2C_SPEED           100000  /* 100 kHz */
 185 #define CFG_I2C_SLAVE           0x7F
 186
 187 /*
 188  * EEPROM configuration
 189  */
 190 #define CFG_I2C_EEPROM_ADDR             0x50    /* 1010000x */
 191 #define CFG_I2C_EEPROM_ADDR_LEN         1
 192 #define CFG_EEPROM_PAGE_WRITE_BITS      3
 193 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  70
 194
 195 /*
 196  * RTC configuration
 197  */
 198 #define CFG_I2C_RTC_ADDR                0x51
 199
 200 /*
 201  * Flash configuration - use CFI driver
 202  */
 203 #define CFG_FLASH_CFI           1               /* Flash is CFI conformant */
 204 #define CFG_FLASH_CFI_DRIVER    1               /* Use the common driver */
 205 #define CFG_FLASH_CFI_AMD_RESET 1
 206 #define CFG_FLASH_BASE          0xFF000000
 207 #define CFG_MAX_FLASH_BANKS     1               /* max num of flash banks */
 208 #define CFG_FLASH_BANKS_LIST    { CFG_FLASH_BASE }
 209 #define CFG_FLASH_SIZE          0x01000000      /* 16 MiB */
 210 #define CFG_MAX_FLASH_SECT      256             /* max num of sects on one chip */
 211 #define CFG_FLASH_USE_BUFFER_WRITE      1       /* flash write speed-up */
 212
 213 /*
 214  * Environment settings
 215  */
 216 #define CFG_ENV_IS_IN_FLASH     1
 217 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x00040000)
 218 #define CFG_ENV_SIZE            0x10000
 219 #define CFG_ENV_SECT_SIZE       0x10000
 220 #define CONFIG_ENV_OVERWRITE    1
 221
 222 /*
 223  * Memory map
 224  */
 225 #define CFG_MBAR                0xF0000000
 226 #define CFG_SDRAM_BASE          0x00000000
 227 #define CFG_DEFAULT_MBAR        0x80000000
 228
 229 /* Use SRAM until RAM will be available */
 230 #define CFG_INIT_RAM_ADDR       MPC5XXX_SRAM
 231 #define CFG_INIT_RAM_END        MPC5XXX_SRAM_SIZE       /* End of used area in DPRAM */
 232
 233 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 234 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 235 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 236
 237 #define CFG_MONITOR_BASE        TEXT_BASE
 238 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 239 #   define CFG_RAMBOOT          1
 240 #endif
 241
 242 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256kB for Monitor */
 243 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128kB for malloc() */
 244 #define CFG_BOOTMAPSZ           (8 << 20)       /* Linux initial memory map */
 245
 246 /*
 247  * Ethernet configuration
 248  */
 249 #define CONFIG_MPC5xxx_FEC      1
 250 #define CONFIG_PHY_ADDR         0x00
 251 #define CONFIG_MII              1
 252
 253 /*
 254  * GPIO configuration
 255  */
 256 #define CFG_GPS_PORT_CONFIG     0x90001404
 257
 258 /*
 259  * Miscellaneous configurable options
 260  */
 261 #define CFG_LONGHELP                    /* undef to save memory */
 262 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt */
 263 #if defined(CONFIG_CMD_KGDB)
 264 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size */
 265 #else
 266 #define CFG_CBSIZE              256     /* Console I/O Buffer Size */
 267 #endif
 268 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size */
 269 #define CFG_MAXARGS             16              /* max number of command args */
 270 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size */
 271
 272 #define CFG_MEMTEST_START       0x00100000      /* memtest works on */
 273 #define CFG_MEMTEST_END         0x00f00000      /* 1 ... 15 MB in DRAM */
 274
 275 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 276
 277 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 278
 279 #define CFG_CACHELINE_SIZE      32      /* For MPC5xxx CPUs */
 280 #if defined(CONFIG_CMD_KGDB)
 281 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value */
 282 #endif
 283
 284 /*
 285  * Various low-level settings
 286  */
 287 #define CFG_HID0_INIT           HID0_ICE | HID0_ICFI
 288 #define CFG_HID0_FINAL          HID0_ICE
 289
 290 #define CFG_BOOTCS_START        CFG_FLASH_BASE
 291 #define CFG_BOOTCS_SIZE         CFG_FLASH_SIZE
 292 #define CFG_BOOTCS_CFG          0x00047801
 293 #define CFG_CS0_START           CFG_FLASH_BASE
 294 #define CFG_CS0_SIZE            CFG_FLASH_SIZE
 295
 296 #define CFG_CS_BURST            0x00000000
 297 #define CFG_CS_DEADCYCLE        0x33333333
 298
 299 #define CFG_RESET_ADDRESS       0xff000000
 300
 301 /*
 302  * IDE/ATA (supports IDE harddisk)
 303  */
 304 #undef CONFIG_IDE_8xx_PCCARD            /* Don't use IDE with PC Card Adapter */
 305 #undef CONFIG_IDE_8xx_DIRECT            /* Direct IDE not supported */
 306 #undef CONFIG_IDE_LED                   /* LED for ide not supported */
 307
 308 #define CONFIG_IDE_RESET                /* reset for ide supported */
 309 #define CONFIG_IDE_PREINIT
 310
 311 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus */
 312 #define CFG_IDE_MAXDEVICE       1       /* max. 1 drive per IDE bus */
 313
 314 #define CFG_ATA_IDE0_OFFSET     0x0000
 315
 316 #define CFG_ATA_BASE_ADDR       MPC5XXX_ATA
 317
 318 #define CFG_ATA_DATA_OFFSET     (0x0060)        /* data I/O offset */
 319
 320 #define CFG_ATA_REG_OFFSET      (CFG_ATA_DATA_OFFSET)   /* normal register accesses offset */
 321
 322 #define CFG_ATA_ALT_OFFSET      (0x005C)        /* alternate registers offset */
 323
 324 #define CFG_ATA_STRIDE          4               /* Interval between registers */
 325
 326 /*
 327  * Status LED
 328  */
 329 #define  CONFIG_STATUS_LED              /* Status LED enabled */
 330 #define  CONFIG_BOARD_SPECIFIC_LED      /* version has board specific leds */
 331
 332 #define CFG_LED_BASE    MPC5XXX_GPT7_ENABLE     /* Timer 7 GPIO */
 333 #ifndef __ASSEMBLY__
 334 typedef unsigned int led_id_t;
 335
 336 #define __led_toggle(_msk) \
 337         do { \
 338                 *((volatile long *) (CFG_LED_BASE)) ^= (_msk); \
 339         } while(0)
 340
 341 #define __led_set(_msk, _st) \
 342         do { \
 343                 if ((_st)) \
 344                         *((volatile long *) (CFG_LED_BASE)) &= ~(_msk); \
 345                 else \
 346                         *((volatile long *) (CFG_LED_BASE)) |= (_msk); \
 347         } while(0)
 348
 349 #define __led_init(_msk, st) \
 350         do { \
 351                 *((volatile long *) (CFG_LED_BASE)) |= 0x34; \
 352         } while(0)
 353 #endif /* __ASSEMBLY__ */
 354
 355 #endif /* __CONFIG_H */