include/configs/vct.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
   4  */
   5
   6 /*
   7  * This file contains the configuration parameters for the VCT board
   8  * family:
   9  *
  10  * vct_premium
  11  * vct_premium_small
  12  * vct_premium_onenand
  13  * vct_premium_onenand_small
  14  * vct_platinum
  15  * vct_platinum_small
  16  * vct_platinum_onenand
  17  * vct_platinum_onenand_small
  18  * vct_platinumavc
  19  * vct_platinumavc_small
  20  * vct_platinumavc_onenand
  21  * vct_platinumavc_onenand_small
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 #define CPU_CLOCK_RATE                  324000000 /* Clock for the MIPS core */
  28 #define CONFIG_SYS_MIPS_TIMER_FREQ      (CPU_CLOCK_RATE / 2)
  29
  30 #define CONFIG_SKIP_LOWLEVEL_INIT       /* SDRAM is initialized by the bootstrap code */
  31
  32 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
  33 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)
  34 #define CONFIG_SYS_MALLOC_LEN           (1 << 20)
  35 #define CONFIG_SYS_BOOTPARAMS_LEN       (128 << 10)
  36 #define CONFIG_SYS_INIT_SP_OFFSET       0x400000
  37
  38 #if !defined(CONFIG_VCT_NAND) && !defined(CONFIG_VCT_ONENAND)
  39 #define CONFIG_VCT_NOR
  40 #endif
  41
  42 /*
  43  * UART
  44  */
  45 #ifdef CONFIG_VCT_PLATINUMAVC
  46 #define UART_1_BASE             0xBDC30000
  47 #else
  48 #define UART_1_BASE             0xBF89C000
  49 #endif
  50
  51 #define CONFIG_SYS_NS16550_SERIAL
  52 #define CONFIG_SYS_NS16550_REG_SIZE     -4
  53 #define CONFIG_SYS_NS16550_COM1         UART_1_BASE
  54 #define CONFIG_SYS_NS16550_CLK          921600
  55
  56 /*
  57  * SDRAM
  58  */
  59 #define CONFIG_SYS_SDRAM_BASE           0x80000000
  60 #define CONFIG_SYS_MBYTES_SDRAM         128
  61 #define CONFIG_SYS_MEMTEST_START        0x80200000
  62 #define CONFIG_SYS_MEMTEST_END          0x80400000
  63 #define CONFIG_SYS_LOAD_ADDR            0x80400000      /* default load address */
  64
  65 #if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
  66 #define CONFIG_NET_RETRY_COUNT          20
  67 #endif
  68
  69 /*
  70  * Commands
  71  */
  72 #if defined(CONFIG_CMD_USB)
  73
  74 /*
  75  * USB/EHCI
  76  */
  77 #define CONFIG_USB_EHCI_VCT             /* on VCT platform              */
  78 #define CONFIG_EHCI_MMIO_BIG_ENDIAN
  79 #define CONFIG_EHCI_DESC_BIG_ENDIAN
  80 #define CONFIG_EHCI_IS_TDI
  81 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
  82 #endif /* CONFIG_CMD_USB */
  83
  84 /*
  85  * BOOTP options
  86  */
  87 #define CONFIG_BOOTP_BOOTFILESIZE
  88
  89 /*
  90  * Miscellaneous configurable options
  91  */
  92 #define CONFIG_SYS_CBSIZE       512             /* Console I/O Buffer Size      */
  93 #define CONFIG_TIMESTAMP                        /* Print image info with timestamp */
  94
  95 /*
  96  * FLASH and environment organization
  97  */
  98 #if defined(CONFIG_VCT_NOR)
  99 #define CONFIG_FLASH_NOT_MEM_MAPPED
 100
 101 /*
 102  * We need special accessor functions for the CFI FLASH driver. This
 103  * can be enabled via the CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS option.
 104  */
 105 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 106
 107 /*
 108  * For the non-memory-mapped NOR FLASH, we need to define the
 109  * NOR FLASH area. This can't be detected via the addr2info()
 110  * function, since we check for flash access in the very early
 111  * U-Boot code, before the NOR FLASH is detected.
 112  */
 113 #define CONFIG_FLASH_BASE               0xb0000000
 114 #define CONFIG_FLASH_END                0xbfffffff
 115
 116 /*
 117  * CFI driver settings
 118  */
 119 #define CONFIG_SYS_FLASH_CFI_AMD_RESET  1       /* Use AMD (Spansion) reset cmd */
 120 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT /* no byte writes on IXP4xx     */
 121
 122 #define CONFIG_SYS_FLASH_BASE           0xb0000000
 123 #define CONFIG_SYS_FLASH_BANKS_LIST    { CONFIG_SYS_FLASH_BASE }
 124 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 125 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 126
 127 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 128 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 129
 130 #ifdef CONFIG_ENV_IS_IN_FLASH
 131 /* Address and size of Redundant Environment Sector     */
 132 #endif /* CONFIG_ENV_IS_IN_FLASH */
 133 #endif /* CONFIG_VCT_NOR */
 134
 135 #if defined(CONFIG_VCT_ONENAND)
 136 #define CONFIG_USE_ONENAND_BOARD_INIT
 137 #define CONFIG_SYS_ONENAND_BASE         0x00000000      /* this is not real address */
 138 #define CONFIG_SYS_FLASH_BASE           0x00000000
 139 #endif /* CONFIG_VCT_ONENAND */
 140
 141 /*
 142  * I2C/EEPROM
 143  */
 144 #define CONFIG_SYS_I2C
 145 #define CONFIG_SYS_I2C_SOFT             /* I2C bit-banged */
 146 #define CONFIG_SYS_I2C_SOFT_SPEED       83000   /* 83 kHz is supposed to work */
 147 #define CONFIG_SYS_I2C_SOFT_SLAVE       0x7f
 148
 149 /*
 150  * Software (bit-bang) I2C driver configuration
 151  */
 152 #define CONFIG_SYS_GPIO_I2C_SCL         11
 153 #define CONFIG_SYS_GPIO_I2C_SDA         10
 154
 155 #ifndef __ASSEMBLY__
 156 int vct_gpio_dir(int pin, int dir);
 157 void vct_gpio_set(int pin, int val);
 158 int vct_gpio_get(int pin);
 159 #endif
 160
 161 #define I2C_INIT        vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SCL, 1)
 162 #define I2C_ACTIVE      vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 1)
 163 #define I2C_TRISTATE    vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 0)
 164 #define I2C_READ        vct_gpio_get(CONFIG_SYS_GPIO_I2C_SDA)
 165 #define I2C_SDA(bit)    vct_gpio_set(CONFIG_SYS_GPIO_I2C_SDA, bit)
 166 #define I2C_SCL(bit)    vct_gpio_set(CONFIG_SYS_GPIO_I2C_SCL, bit)
 167 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 168
 169 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 170 /* CAT24WC32 */
 171 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2       /* Bytes of address             */
 172 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5     /* The Catalyst CAT24WC32 has   */
 173                                         /* 32 byte page write mode using*/
 174                                         /* last 5 bits of the address   */
 175 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 176
 177 #define CONFIG_BOOTCOMMAND      "run test3"
 178
 179 /*
 180  * UBI configuration
 181  */
 182
 183 /*
 184  * We need a small, stripped down image to fit into the first 128k OneNAND
 185  * erase block (gzipped). This image only needs basic commands for FLASH
 186  * (NOR/OneNAND) usage and Linux kernel booting.
 187  */
 188 #if defined(CONFIG_VCT_SMALL_IMAGE)
 189 #undef CONFIG_SYS_I2C_SOFT
 190 #undef CONFIG_SOURCE
 191 #undef CONFIG_TIMESTAMP
 192 #endif /* CONFIG_VCT_SMALL_IMAGE */
 193
 194 #endif  /* __CONFIG_H */