include/configs/ve8313.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) Freescale Semiconductor, Inc. 2006.
   4  *
   5  * (C) Copyright 2010
   6  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   7  */
   8 /*
   9  * ve8313 board configuration file
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  */
  18 #define CONFIG_E300             1
  19
  20 #define CONFIG_PCI_INDIRECT_BRIDGE 1
  21
  22 /*
  23  * On-board devices
  24  *
  25  */
  26
  27 /*
  28  * Device configurations
  29  */
  30
  31 /*
  32  * DDR Setup
  33  */
  34 #define CONFIG_SYS_SDRAM_BASE           0x00000000 /* DDR is system memory*/
  35
  36 /*
  37  * Manually set up DDR parameters, as this board does not
  38  * have the SPD connected to I2C.
  39  */
  40 #define CONFIG_SYS_DDR_SIZE     128     /* MB */
  41 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  42                                 | CSCONFIG_AP \
  43                                 | CSCONFIG_ODT_RD_NEVER \
  44                                 | CSCONFIG_ODT_WR_ALL \
  45                                 | CSCONFIG_ROW_BIT_13 \
  46                                 | CSCONFIG_COL_BIT_10)
  47                                 /* 0x80840102 */
  48
  49 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  50 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  51                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  52                                 | (3 << TIMING_CFG0_RRT_SHIFT) \
  53                                 | (2 << TIMING_CFG0_WWT_SHIFT) \
  54                                 | (7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  55                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  56                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  57                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  58                                 /* 0x0e720802 */
  59 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  60                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  61                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  62                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  63                                 | (6 << TIMING_CFG1_REFREC_SHIFT) \
  64                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
  65                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  66                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
  67                                 /* 0x26256222 */
  68 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
  69                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
  70                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  71                                 | (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  72                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  73                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  74                                 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
  75                                 /* 0x029028c7 */
  76 #define CONFIG_SYS_DDR_INTERVAL ((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \
  77                                 | (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  78                                 /* 0x03202000 */
  79 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
  80                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  81                                 | SDRAM_CFG_DBW_32)
  82                                 /* 0x43080000 */
  83 #define CONFIG_SYS_SDRAM_CFG2   0x00401000
  84 #define CONFIG_SYS_DDR_MODE     ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
  85                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
  86                                 /* 0x44400232 */
  87 #define CONFIG_SYS_DDR_MODE_2   0x8000C000
  88
  89 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  90                                 /*0x02000000*/
  91 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  92                                 | DDRCDR_PZ_NOMZ \
  93                                 | DDRCDR_NZ_NOMZ \
  94                                 | DDRCDR_M_ODR)
  95                                 /* 0x73000002 */
  96
  97 /*
  98  * FLASH on the Local Bus
  99  */
 100 #define CONFIG_SYS_FLASH_BASE           0xFE000000
 101 #define CONFIG_SYS_FLASH_SIZE           32      /* size in MB */
 102 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
 103
 104 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 105 #define CONFIG_SYS_MAX_FLASH_SECT       256             /* sectors per dev */
 106
 107 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 108 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 109
 110 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 111
 112 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 113 #define CONFIG_SYS_RAMBOOT
 114 #endif
 115
 116 #define CONFIG_SYS_INIT_RAM_LOCK        1
 117 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000 /* Initial RAM address */
 118 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 119
 120 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 121                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 122 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 123
 124 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 125 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024)
 126 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)
 127
 128 /*
 129  * NAND settings
 130  */
 131 #define CONFIG_SYS_NAND_BASE            0x61000000
 132 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 133 #define CONFIG_NAND_FSL_ELBC 1
 134 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
 135
 136
 137
 138 /* Still needed for spl_minimal.c */
 139 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
 140 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
 141
 142
 143
 144 /*
 145  * Serial Port
 146  */
 147 #define CONFIG_SYS_NS16550_SERIAL
 148 #define CONFIG_SYS_NS16550_REG_SIZE     1
 149 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 150
 151 #define CONFIG_SYS_BAUDRATE_TABLE       \
 152         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 153
 154 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 155 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 156
 157 #if defined(CONFIG_PCI)
 158 /*
 159  * General PCI
 160  * Addresses are mapped 1-1.
 161  */
 162 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 163 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 164 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 165 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 166 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 167 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 168 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 169 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 170 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 171
 172 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 173 #endif
 174
 175 /*
 176  * TSEC
 177  */
 178
 179 #define CONFIG_TSEC1
 180 #ifdef CONFIG_TSEC1
 181 #define CONFIG_HAS_ETH0
 182 #define CONFIG_TSEC1_NAME       "TSEC1"
 183 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 184 #define TSEC1_PHY_ADDR          0x01
 185 #define TSEC1_FLAGS             0
 186 #define TSEC1_PHYIDX            0
 187 #endif
 188
 189 /* Options are: TSEC[0-1] */
 190 #define CONFIG_ETHPRIME                 "TSEC1"
 191
 192 /*
 193  * Environment
 194  */
 195 /* Address and size of Redundant Environment Sector */
 196
 197 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 198 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 199
 200 /*
 201  * BOOTP options
 202  */
 203 #define CONFIG_BOOTP_BOOTFILESIZE
 204
 205 /*
 206  * Command line configuration.
 207  */
 208
 209 /*
 210  * Miscellaneous configurable options
 211  */
 212 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 213 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 214
 215 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot arg Buffer size */
 216
 217 /*
 218  * For booting Linux, the board info and command line data
 219  * have to be in the first 256 MB of memory, since this is
 220  * the maximum mapped by the Linux kernel during initialization.
 221  */
 222                                 /* Initial Memory map for Linux*/
 223 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 224
 225 /* System IO Config */
 226 #define CONFIG_SYS_SICRH        (0x01000000 | \
 227                                 SICRH_ETSEC2_B | \
 228                                 SICRH_ETSEC2_C | \
 229                                 SICRH_ETSEC2_D | \
 230                                 SICRH_ETSEC2_E | \
 231                                 SICRH_ETSEC2_F | \
 232                                 SICRH_ETSEC2_G | \
 233                                 SICRH_TSOBI1 | \
 234                                 SICRH_TSOBI2)
 235                                 /* 0x010fff03 */
 236 #define CONFIG_SYS_SICRL        (SICRL_LBC | \
 237                                 SICRL_SPI_A | \
 238                                 SICRL_SPI_B | \
 239                                 SICRL_SPI_C | \
 240                                 SICRL_SPI_D | \
 241                                 SICRL_ETSEC2_A)
 242                                 /* 0x33fc0003) */
 243
 244 #define CONFIG_NETDEV           eth0
 245
 246 #define CONFIG_HOSTNAME         "ve8313"
 247 #define CONFIG_UBOOTPATH        ve8313/u-boot.bin
 248
 249 #define CONFIG_EXTRA_ENV_SETTINGS \
 250         "netdev=" __stringify(CONFIG_NETDEV) "\0"                       \
 251         "ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0"                 \
 252         "u-boot=" __stringify(CONFIG_UBOOTPATH) "\0"                    \
 253         "u-boot_addr_r=100000\0"                                        \
 254         "load=tftp ${u-boot_addr_r} ${u-boot}\0"                        \
 255         "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE)        \
 256                 " +${filesize};"        \
 257         "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};"    \
 258         "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE)     \
 259         " ${filesize};"                                                 \
 260         "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \
 261
 262 #endif  /* __CONFIG_H */