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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * WORK Microwave work_92105 board configuration file
4 *
5 * (C) Copyright 2014 DENX Software Engineering GmbH
6 * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
7 */
8
9 #ifndef __CONFIG_WORK_92105_H__
10 #define __CONFIG_WORK_92105_H__
11
12 /* SoC and board defines */
13 #include <linux/sizes.h>
14 #include <asm/arch/cpu.h>
15
16 /*
17 * Define work_92105 machine type by hand -- done only for compatibility
18 * with original board code
19 */
20 #define CONFIG_MACH_TYPE 736
21
22 #if !defined(CONFIG_SPL_BUILD)
23 #define CONFIG_SKIP_LOWLEVEL_INIT
24 #endif
25
26 /*
27 * Memory configurations
28 */
29 #define CONFIG_SYS_MALLOC_LEN SZ_1M
30 #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
31 #define CONFIG_SYS_SDRAM_SIZE SZ_128M
32 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K)
33 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M)
34
35 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K)
36
37 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \
38 - GENERATED_GBL_DATA_SIZE)
39
40 /*
41 * Serial Driver
42 */
43 #define CONFIG_SYS_LPC32XX_UART 5 /* UART5 - NS16550 */
44
45 /*
46 * Ethernet Driver
47 */
48
49 #define CONFIG_PHY_SMSC
50 #define CONFIG_LPC32XX_ETH
51 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
52 /* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */
53
54 /*
55 * I2C driver
56 */
57
58 #define CONFIG_SYS_I2C_LPC32XX
59 #define CONFIG_SYS_I2C
60 #define CONFIG_SYS_I2C_SPEED 350000
61
62 /*
63 * I2C EEPROM
64 */
65
66 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x56
67 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
68
69 /*
70 * I2C RTC
71 */
72
73 #define CONFIG_RTC_DS1374
74
75 /*
76 * U-Boot General Configurations
77 */
78 #define CONFIG_SYS_CBSIZE 1024
79 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
80
81 /*
82 * NAND chip timings for FIXME: which one?
83 */
84
85 #define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333
86 #define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000
87 #define CONFIG_LPC32XX_NAND_MLC_NAND_TA 18181818
88 #define CONFIG_LPC32XX_NAND_MLC_RD_HIGH 31250000
89 #define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545
90 #define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000
91 #define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333
92
93 /*
94 * NAND
95 */
96
97 /* driver configuration */
98 #define CONFIG_SYS_NAND_SELF_INIT
99 #define CONFIG_SYS_MAX_NAND_DEVICE 1
100 #define CONFIG_SYS_MAX_NAND_CHIPS 1
101 #define CONFIG_SYS_NAND_BASE MLC_NAND_BASE
102 #define CONFIG_NAND_LPC32XX_MLC
103
104 /*
105 * GPIO
106 */
107
108 #define CONFIG_LPC32XX_GPIO
109
110 /*
111 * SSP/SPI/DISPLAY
112 */
113
114 #define CONFIG_LPC32XX_SSP_TIMEOUT 100000
115 /*
116 * Environment
117 */
118
119 /*
120 * Boot Linux
121 */
122 #define CONFIG_CMDLINE_TAG
123 #define CONFIG_SETUP_MEMORY_TAGS
124 #define CONFIG_INITRD_TAG
125
126 #define CONFIG_BOOTFILE "uImage"
127 #define CONFIG_LOADADDR 0x80008000
128
129 /*
130 * SPL
131 */
132
133 /* SPL will be executed at offset 0 */
134 /* SPL will use SRAM as stack */
135 #define CONFIG_SPL_STACK 0x0000FFF8
136 /* Use the framework and generic lib */
137 /* SPL will use serial */
138 /* SPL will load U-Boot from NAND offset 0x40000 */
139 #define CONFIG_SPL_NAND_DRIVERS
140 #define CONFIG_SPL_NAND_BASE
141 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00040000
142 #define CONFIG_SPL_PAD_TO 0x20000
143 /* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
144 #define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */
145 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
146 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
147
148 /*
149 * Include SoC specific configuration
150 */
151 #include <asm/arch/config.h>
152
153 #endif /* __CONFIG_WORK_92105_H__*/