include/configs/work_92105.h

   1 /*
   2  * WORK Microwave work_92105 board configuration file
   3  *
   4  * (C) Copyright 2014  DENX Software Engineering GmbH
   5  * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __CONFIG_WORK_92105_H__
  11 #define __CONFIG_WORK_92105_H__
  12
  13 /* SoC and board defines */
  14 #include <linux/sizes.h>
  15 #include <asm/arch/cpu.h>
  16
  17 /*
  18  * Define work_92105 machine type by hand -- done only for compatibility
  19  * with original board code
  20  */
  21 #define CONFIG_MACH_TYPE                736
  22
  23 #define CONFIG_SYS_ICACHE_OFF
  24 #define CONFIG_SYS_DCACHE_OFF
  25 #if !defined(CONFIG_SPL_BUILD)
  26 #define CONFIG_SKIP_LOWLEVEL_INIT
  27 #endif
  28 #define CONFIG_BOARD_EARLY_INIT_R
  29
  30 /* generate LPC32XX-specific SPL image */
  31 #define CONFIG_LPC32XX_SPL
  32
  33 /*
  34  * Memory configurations
  35  */
  36 #define CONFIG_NR_DRAM_BANKS            1
  37 #define CONFIG_SYS_MALLOC_LEN           SZ_1M
  38 #define CONFIG_SYS_SDRAM_BASE           EMC_DYCS0_BASE
  39 #define CONFIG_SYS_SDRAM_SIZE           SZ_128M
  40 #define CONFIG_SYS_TEXT_BASE            0x80100000
  41 #define CONFIG_SYS_MEMTEST_START        (CONFIG_SYS_SDRAM_BASE + SZ_32K)
  42 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_TEXT_BASE - SZ_1M)
  43
  44 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + SZ_32K)
  45
  46 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + SZ_512K \
  47                                          - GENERATED_GBL_DATA_SIZE)
  48
  49 /*
  50  * Serial Driver
  51  */
  52 #define CONFIG_SYS_LPC32XX_UART         5   /* UART5 - NS16550 */
  53
  54 /*
  55  * Ethernet Driver
  56  */
  57
  58 #define CONFIG_PHY_SMSC
  59 #define CONFIG_LPC32XX_ETH
  60 #define CONFIG_PHYLIB
  61 #define CONFIG_PHY_ADDR 0
  62 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  63 /* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */
  64
  65 /*
  66  * I2C driver
  67  */
  68
  69 #define CONFIG_SYS_I2C_LPC32XX
  70 #define CONFIG_SYS_I2C
  71 #define CONFIG_SYS_I2C_SPEED 350000
  72
  73 /*
  74  * I2C EEPROM
  75  */
  76
  77 #define CONFIG_CMD_EEPROM
  78 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x56
  79 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  80
  81 /*
  82  * I2C RTC
  83  */
  84
  85 #define CONFIG_RTC_DS1374
  86
  87 /*
  88  * I2C Temperature Sensor (DTT)
  89  */
  90
  91 #define CONFIG_CMD_DTT
  92 #define CONFIG_DTT_SENSORS { 0, 1 }
  93 #define CONFIG_DTT_DS620
  94
  95 /*
  96  * U-Boot General Configurations
  97  */
  98 #define CONFIG_SYS_LONGHELP
  99 #define CONFIG_SYS_CBSIZE               1024
 100 #define CONFIG_SYS_PBSIZE               \
 101         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 102 #define CONFIG_SYS_MAXARGS              16
 103 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 104
 105 #define CONFIG_AUTO_COMPLETE
 106 #define CONFIG_CMDLINE_EDITING
 107
 108 /*
 109  * NAND chip timings for FIXME: which one?
 110  */
 111
 112 #define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY  333333333
 113 #define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY   10000000
 114 #define CONFIG_LPC32XX_NAND_MLC_NAND_TA      18181818
 115 #define CONFIG_LPC32XX_NAND_MLC_RD_HIGH      31250000
 116 #define CONFIG_LPC32XX_NAND_MLC_RD_LOW       45454545
 117 #define CONFIG_LPC32XX_NAND_MLC_WR_HIGH      40000000
 118 #define CONFIG_LPC32XX_NAND_MLC_WR_LOW       83333333
 119
 120 /*
 121  * NAND
 122  */
 123
 124 /* driver configuration */
 125 #define CONFIG_SYS_NAND_SELF_INIT
 126 #define CONFIG_SYS_MAX_NAND_DEVICE 1
 127 #define CONFIG_SYS_MAX_NAND_CHIPS 1
 128 #define CONFIG_SYS_NAND_BASE MLC_NAND_BASE
 129 #define CONFIG_NAND_LPC32XX_MLC
 130
 131 #define CONFIG_CMD_NAND
 132
 133 /*
 134  * GPIO
 135  */
 136
 137 #define CONFIG_LPC32XX_GPIO
 138
 139 /*
 140  * SSP/SPI/DISPLAY
 141  */
 142
 143 #define CONFIG_LPC32XX_SSP
 144 #define CONFIG_LPC32XX_SSP_TIMEOUT 100000
 145 #define CONFIG_CMD_MAX6957
 146 #define CONFIG_CMD_HD44760
 147 /*
 148  * Environment
 149  */
 150
 151 #define CONFIG_ENV_IS_IN_NAND           1
 152 #define CONFIG_ENV_SIZE                 0x00020000
 153 #define CONFIG_ENV_OFFSET               0x00100000
 154 #define CONFIG_ENV_OFFSET_REDUND        0x00120000
 155 #define CONFIG_ENV_ADDR                 0x80000100
 156
 157 /*
 158  * Boot Linux
 159  */
 160 #define CONFIG_CMDLINE_TAG
 161 #define CONFIG_SETUP_MEMORY_TAGS
 162 #define CONFIG_INITRD_TAG
 163
 164 #define CONFIG_BOOTFILE                 "uImage"
 165 #define CONFIG_BOOTARGS                 "console=ttyS2,115200n8"
 166 #define CONFIG_LOADADDR                 0x80008000
 167
 168 /*
 169  * SPL
 170  */
 171
 172 /* SPL will be executed at offset 0 */
 173 #define CONFIG_SPL_TEXT_BASE 0x00000000
 174 /* SPL will use SRAM as stack */
 175 #define CONFIG_SPL_STACK     0x0000FFF8
 176 #define CONFIG_SPL_BOARD_INIT
 177 /* Use the framework and generic lib */
 178 #define CONFIG_SPL_FRAMEWORK
 179 /* SPL will use serial */
 180 /* SPL will load U-Boot from NAND offset 0x40000 */
 181 #define CONFIG_SPL_NAND_DRIVERS
 182 #define CONFIG_SPL_NAND_BASE
 183 #define CONFIG_SPL_NAND_BOOT
 184 #define CONFIG_SYS_NAND_U_BOOT_OFFS  0x00040000
 185 #define CONFIG_SPL_PAD_TO 0x20000
 186 /* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
 187 #define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */
 188 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
 189 #define CONFIG_SYS_NAND_U_BOOT_DST   CONFIG_SYS_TEXT_BASE
 190
 191 /*
 192  * Include SoC specific configuration
 193  */
 194 #include <asm/arch/config.h>
 195
 196 #endif  /* __CONFIG_WORK_92105_H__*/