include/configs/xaeniax.h

   1 /*
   2  * (C) Copyright 2004-2005
   3  * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
   4  *
   5  * (C) Copyright 2004
   6  * Vincent Dubey, Xa SA, vincent.dubey@xa-ch.com
   7  *
   8  * (C) Copyright 2002
   9  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.ne
  10  *
  11  * (C) Copyright 2002
  12  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  13  * Marius Groeger <mgroeger@sysgo.de>
  14  *
  15  * Configuation settings for the xaeniax board.
  16  *
  17  * See file CREDITS for list of people who contributed to this
  18  * project.
  19  *
  20  * This program is free software; you can redistribute it and/or
  21  * modify it under the terms of the GNU General Public License as
  22  * published by the Free Software Foundation; either version 2 of
  23  * the License, or (at your option) any later version.
  24  *
  25  * This program is distributed in the hope that it will be useful,
  26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  28  * GNU General Public License for more details.
  29  *
  30  * You should have received a copy of the GNU General Public License
  31  * along with this program; if not, write to the Free Software
  32  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  33  * MA 02111-1307 USA
  34  */
  35
  36 #ifndef __CONFIG_H
  37 #define __CONFIG_H
  38
  39 /*
  40  * High Level Configuration Options
  41  * (easy to change)
  42  */
  43 #define CONFIG_PXA250           1       /* This is an PXA255 CPU    */
  44 #define CONFIG_XAENIAX          1       /* on a xaeniax board       */
  45
  46
  47 #define BOARD_LATE_INIT         1
  48
  49
  50 #undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff */
  51
  52 /*
  53  * select serial console configuration
  54  */
  55 #define CONFIG_BTUART          1       /* we use BTUART on XAENIAX */
  56
  57
  58 /* allow to overwrite serial and ethaddr */
  59 #define CONFIG_ENV_OVERWRITE
  60
  61 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  62
  63 #define CONFIG_BAUDRATE         115200
  64
  65 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 } /* valid baudrates */
  66
  67
  68 /*
  69  * Command line configuration.
  70  */
  71 #include <config_cmd_default.h>
  72
  73 #define CONFIG_CMD_DHCP
  74 #define CONFIG_CMD_DIAG
  75 #define CONFIG_CMD_NFS
  76 #define CONFIG_CMD_SDRAM
  77 #define CONFIG_CMD_SNTP
  78
  79 #undef CONFIG_CMD_DTT
  80
  81
  82 #define CONFIG_ETHADDR          08:00:3e:26:0a:5b
  83 #define CONFIG_NETMASK          255.255.255.0
  84 #define CONFIG_IPADDR           192.168.68.201
  85 #define CONFIG_SERVERIP         192.168.68.62
  86
  87 #define CONFIG_BOOTDELAY        3
  88 #define CONFIG_BOOTCOMMAND      "bootm 0x00100000"
  89 #define CONFIG_BOOTARGS         "console=ttyS1,115200"
  90 #define CONFIG_CMDLINE_TAG              1       /* enable passing of ATAGs */
  91 #define CONFIG_SETUP_MEMORY_TAGS        1
  92 #define CONFIG_INITRD_TAG               1
  93
  94 #if defined(CONFIG_CMD_KGDB)
  95 #define CONFIG_KGDB_BAUDRATE    115200                  /* speed to run kgdb serial port */
  96 #define CONFIG_KGDB_SER_INDEX   1                       /* which serial port to use */
  97 #endif
  98
  99 /*
 100  * Size of malloc() pool; this lives below the uppermost 128 KiB which are
 101  * used for the RAM copy of the uboot code
 102  */
 103 #define CFG_MALLOC_LEN      (CFG_ENV_SIZE + 128*1024)
 104 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 105
 106 /*
 107  * Miscellaneous configurable options
 108  */
 109 #define CFG_LONGHELP                            /* undef to save memory */
 110 #define CFG_HUSH_PARSER         1
 111
 112 #define CFG_PROMPT_HUSH_PS2     "> "
 113
 114 #ifdef CFG_HUSH_PARSER
 115 #define CFG_PROMPT              "u-boot$ "      /* Monitor Command Prompt */
 116 #else
 117 #define CFG_PROMPT              "u-boot=> "     /* Monitor Command Prompt */
 118 #endif
 119 #define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
 120 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 121 #define CFG_MAXARGS             16              /* max number of command args   */
 122 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 123 #define CFG_DEVICE_NULLDEV      1
 124
 125 #define CFG_MEMTEST_START       0xa0400000      /* memtest works on     */
 126 #define CFG_MEMTEST_END         0xa0800000      /* 4 ... 8 MB in DRAM   */
 127
 128 #undef  CFG_CLKS_IN_HZ                          /* everything, incl board info, in Hz */
 129
 130 #define CFG_LOAD_ADDR           0xa1000000      /* default load address */
 131
 132 #define CFG_HZ                  3686400         /* incrementer freq: 3.6864 MHz */
 133 #define CFG_CPUSPEED            0x141           /* set core clock to 400/200/100 MHz */
 134
 135 /*
 136  * Physical Memory Map
 137  */
 138 #define CONFIG_NR_DRAM_BANKS    1          /* we have 1 banks (partition) of DRAM */
 139 #define PHYS_SDRAM_1            0xa0000000 /* SDRAM Bank #1 */
 140 #define PHYS_SDRAM_1_SIZE       0x04000000 /* 64 MB */
 141 #define PHYS_SDRAM_2            0xa4000000 /* SDRAM Bank #2 */
 142 #define PHYS_SDRAM_2_SIZE       0x00000000 /* 0 MB */
 143 #define PHYS_SDRAM_3            0xa8000000 /* SDRAM Bank #3 */
 144 #define PHYS_SDRAM_3_SIZE       0x00000000 /* 0 MB */
 145 #define PHYS_SDRAM_4            0xac000000 /* SDRAM Bank #4 */
 146 #define PHYS_SDRAM_4_SIZE       0x00000000 /* 0 MB */
 147
 148 #define PHYS_FLASH_1            0x00000000 /* Flash Bank #1 */
 149 #define PHYS_FLASH_2            0x04000000 /* Flash Bank #2 */
 150 #define PHYS_FLASH_SIZE         0x02000000 /* 32 MB */
 151 #define PHYS_FLASH_BANK_SIZE    0x02000000 /* 32 MB Banks */
 152 #define PHYS_FLASH_SECT_SIZE    0x00040000 /* 256 KB sectors (x2) */
 153
 154 #define CFG_DRAM_BASE           0xa0000000
 155 #define CFG_DRAM_SIZE           0x04000000
 156
 157 #define CFG_FLASH_BASE          PHYS_FLASH_1
 158
 159 /*
 160  * FLASH and environment organization
 161  */
 162 #define CFG_MAX_FLASH_BANKS     1    /* max number of memory banks              */
 163 #define CFG_MAX_FLASH_SECT      128  /* max number of sectors on one chip    */
 164
 165 /* timeout values are in ticks */
 166 #define CFG_FLASH_ERASE_TOUT    (25*CFG_HZ) /* Timeout for Flash Erase */
 167 #define CFG_FLASH_WRITE_TOUT    (25*CFG_HZ) /* Timeout for Flash Write */
 168
 169 /* FIXME */
 170 #define CFG_ENV_IS_IN_FLASH     1
 171 #define CFG_ENV_ADDR            (PHYS_FLASH_1 + 0x40000)/* Addr of Environment Sector   */
 172 #define CFG_ENV_SIZE            0x40000                 /* Total Size of Environment Sector     */
 173
 174 /*
 175  * Stack sizes
 176  *
 177  * The stack sizes are set up in start.S using the settings below
 178  */
 179 #define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
 180 #ifdef CONFIG_USE_IRQ
 181 #define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
 182 #define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
 183 #endif
 184
 185 /*
 186  * SMSC91C111 Network Card
 187  */
 188 #define CONFIG_DRIVER_SMC91111          1
 189 #define CONFIG_SMC91111_BASE            0x10000300  /* chip select 3         */
 190 #define CONFIG_SMC_USE_32_BIT           1          /* 32 bit bus  */
 191 #undef  CONFIG_SMC_91111_EXT_PHY                   /* we use internal phy   */
 192 #undef  CONFIG_SHOW_ACTIVITY
 193 #define CONFIG_NET_RETRY_COUNT          10         /* # of retries          */
 194
 195 /*
 196  * GPIO settings
 197  */
 198
 199 /*
 200  * GP05 == nUSBReset  is 1
 201  * GP10 == CFReset   is 1
 202  * GP13 == nCFDataEnable is 1
 203  * GP14 == nCFAddrEnable is 1
 204  * GP15 == nCS1      is 1
 205  * GP21 == ComBrdReset is 1
 206  * GP24 == SFRM      is 1
 207  * GP25 == TXD       is 1
 208  * GP31 == SYNC      is 1
 209  * GP33 == nCS5      is 1
 210  * GP39 == FFTXD     is 1
 211  * GP41 == RTS       is 1
 212  * GP43 == BTTXD     is 1
 213  * GP45 == BTRTS     is 1
 214  * GP47 == TXD       is 1
 215  * GP48 == nPOE      is 1
 216  * GP49 == nPWE      is 1
 217  * GP50 == nPIOR     is 1
 218  * GP51 == nPIOW     is 1
 219  * GP52 == nPCE[1]   is 1
 220  * GP53 == nPCE[2]   is 1
 221  * GP54 == nPSKTSEL  is 1
 222  * GP55 == nPREG     is 1
 223  * GP78 == nCS2      is 1
 224  * GP79 == nCS3      is 1
 225  * GP80 == nCS4      is 1
 226  * GP82 == NSSPSFRM  is 1
 227  * GP83 == NSSPTXD   is 1
 228  */
 229 #define CFG_GPSR0_VAL           0x8320E420
 230 #define CFG_GPSR1_VAL           0x00FFAA82
 231 #define CFG_GPSR2_VAL           0x000DC000
 232
 233 /*
 234  * GP03 == LANReset  is 0
 235  * GP06 == USBWakeUp  is 0
 236  * GP11 == USBControl is 0
 237  * GP12 == Buzzer     is 0
 238  * GP16 == PWM0       is 0
 239  * GP17 == PWM1       is 0
 240  * GP23 == SCLK      is 0
 241  * GP30 == SDATA_OUT is 0
 242  * GP81 == NSSPCLK   is 0
 243  */
 244 #define CFG_GPCR0_VAL           0x40C31848
 245 #define CFG_GPCR1_VAL           0x00000000
 246 #define CFG_GPCR2_VAL           0x00020000
 247
 248 /*
 249  * GP00 == CPUWakeUpUSB is input
 250  * GP01 == GP reset is input
 251  * GP02 == LANInterrupt is input
 252  * GP03 == LANReset     is output
 253  * GP04 == USBInterrupt is input
 254  * GP05 == nUSBReset    is output
 255  * GP06 == USBWakeUp    is output
 256  * GP07 == CFReady/nBusy is input
 257  * GP08 == nCFCardDetect1 is input
 258  * GP09 == nCFCardDetect2 is input
 259  * GP10 == nCFReset   is output
 260  * GP11 == USBControl is output
 261  * GP12 == Buzzer     is output
 262  * GP13 == CFDataEnable is output
 263  * GP14 == CFAddressEnable is output
 264  * GP15 == nCS1      is output
 265  * GP16 == PWM0      is output
 266  * GP17 == PWM1      is output
 267  * GP18 == RDY       is input
 268  * GP19 == ReaderReady is input
 269  * GP20 == ReaderReset is input
 270  * GP21 == ComBrdReset is output
 271  * GP23 == SCLK      is output
 272  * GP24 == SFRM      is output
 273  * GP25 == TXD       is output
 274  * GP26 == RXD       is input
 275  * GP27 == EXTCLK    is input
 276  * GP28 == BITCLK    is output
 277  * GP29 == SDATA_IN0 is input
 278  * GP30 == SDATA_OUT is output
 279  * GP31 == SYNC      is output
 280  * GP32 == SYSSCLK   is output
 281  * GP33 == nCS5      is output
 282  * GP34 == FFRXD     is input
 283  * GP35 == CTS       is input
 284  * GP36 == DCD       is input
 285  * GP37 == DSR       is input
 286  * GP38 == RI        is input
 287  * GP39 == FFTXD     is output
 288  * GP40 == DTR       is output
 289  * GP41 == RTS       is output
 290  * GP42 == BTRXD     is input
 291  * GP43 == BTTXD     is output
 292  * GP44 == BTCTS     is input
 293  * GP45 == BTRTS     is output
 294  * GP46 == RXD       is input
 295  * GP47 == TXD       is output
 296  * GP48 == nPOE      is output
 297  * GP49 == nPWE      is output
 298  * GP50 == nPIOR     is output
 299  * GP51 == nPIOW     is output
 300  * GP52 == nPCE[1]   is output
 301  * GP53 == nPCE[2]   is output
 302  * GP54 == nPSKTSEL  is output
 303  * GP55 == nPREG     is output
 304  * GP56 == nPWAIT    is input
 305  * GP57 == nPIOS16   is input
 306  * GP58 == LDD[0]    is output
 307  * GP59 == LDD[1]    is output
 308  * GP60 == LDD[2]    is output
 309  * GP61 == LDD[3]    is output
 310  * GP62 == LDD[4]    is output
 311  * GP63 == LDD[5]    is output
 312  * GP64 == LDD[6]    is output
 313  * GP65 == LDD[7]    is output
 314  * GP66 == LDD[8]    is output
 315  * GP67 == LDD[9]    is output
 316  * GP68 == LDD[10]   is output
 317  * GP69 == LDD[11]   is output
 318  * GP70 == LDD[12]   is output
 319  * GP71 == LDD[13]   is output
 320  * GP72 == LDD[14]   is output
 321  * GP73 == LDD[15]   is output
 322  * GP74 == LCD_FCLK  is output
 323  * GP75 == LCD_LCLK  is output
 324  * GP76 == LCD_PCLK  is output
 325  * GP77 == LCD_ACBIAS is output
 326  * GP78 == nCS2      is output
 327  * GP79 == nCS3      is output
 328  * GP80 == nCS4      is output
 329  * GP81 == NSSPCLK   is output
 330  * GP82 == NSSPSFRM  is output
 331  * GP83 == NSSPTXD   is output
 332  * GP84 == NSSPRXD   is input
 333  */
 334 #define CFG_GPDR0_VAL           0xD3E3FC68
 335 #define CFG_GPDR1_VAL           0xFCFFAB83
 336 #define CFG_GPDR2_VAL           0x000FFFFF
 337
 338 /*
 339  * GP01 == GP reset is AF01
 340  * GP15 == nCS1     is AF10
 341  * GP16 == PWM0     is AF10
 342  * GP17 == PWM1     is AF10
 343  * GP18 == RDY      is AF01
 344  * GP23 == SCLK     is AF10
 345  * GP24 == SFRM     is AF10
 346  * GP25 == TXD      is AF10
 347  * GP26 == RXD      is AF01
 348  * GP27 == EXTCLK   is AF01
 349  * GP28 == BITCLK   is AF01
 350  * GP29 == SDATA_IN0 is AF10
 351  * GP30 == SDATA_OUT is AF01
 352  * GP31 == SYNC     is AF01
 353  * GP32 == SYSCLK   is AF01
 354  * GP33 == nCS5  is AF10
 355  * GP34 == FFRXD is AF01
 356  * GP35 == CTS   is AF01
 357  * GP36 == DCD   is AF01
 358  * GP37 == DSR   is AF01
 359  * GP38 == RI    is AF01
 360  * GP39 == FFTXD is AF10
 361  * GP40 == DTR   is AF10
 362  * GP41 == RTS   is AF10
 363  * GP42 == BTRXD is AF01
 364  * GP43 == BTTXD is AF10
 365  * GP44 == BTCTS is AF01
 366  * GP45 == BTRTS is AF10
 367  * GP46 == RXD   is AF10
 368  * GP47 == TXD   is AF01
 369  * GP48 == nPOE  is AF10
 370  * GP49 == nPWE  is AF10
 371  * GP50 == nPIOR is AF10
 372  * GP51 == nPIOW is AF10
 373  * GP52 == nPCE[1] is AF10
 374  * GP53 == nPCE[2] is AF10
 375  * GP54 == nPSKTSEL is AF10
 376  * GP55 == nPREG   is AF10
 377  * GP56 == nPWAIT  is AF01
 378  * GP57 == nPIOS16 is AF01
 379  * GP58 == LDD[0]  is AF10
 380  * GP59 == LDD[1]  is AF10
 381  * GP60 == LDD[2]  is AF10
 382  * GP61 == LDD[3]  is AF10
 383  * GP62 == LDD[4]  is AF10
 384  * GP63 == LDD[5]  is AF10
 385  * GP64 == LDD[6]  is AF10
 386  * GP65 == LDD[7]  is AF10
 387  * GP66 == LDD[8]  is AF10
 388  * GP67 == LDD[9]  is AF10
 389  * GP68 == LDD[10] is AF10
 390  * GP69 == LDD[11] is AF10
 391  * GP70 == LDD[12] is AF10
 392  * GP71 == LDD[13] is AF10
 393  * GP72 == LDD[14] is AF10
 394  * GP73 == LDD[15] is AF10
 395  * GP74 == LCD_FCLK is AF10
 396  * GP75 == LCD_LCLK is AF10
 397  * GP76 == LCD_PCLK is AF10
 398  * GP77 == LCD_ACBIAS is AF10
 399  * GP78 == nCS2     is AF10
 400  * GP79 == nCS3     is AF10
 401  * GP80 == nCS4     is AF10
 402  * GP81 == NSSPCLK  is AF01
 403  * GP82 == NSSPSFRM is AF01
 404  * GP83 == NSSPTXD  is AF01
 405  * GP84 == NSSPRXD  is AF10
 406  */
 407 #define CFG_GAFR0_L_VAL         0x80000004
 408 #define CFG_GAFR0_U_VAL         0x595A801A
 409 #define CFG_GAFR1_L_VAL         0x699A9559
 410 #define CFG_GAFR1_U_VAL         0xAAA5AAAA
 411 #define CFG_GAFR2_L_VAL         0xAAAAAAAA
 412 #define CFG_GAFR2_U_VAL         0x00000256
 413
 414 /*
 415  * clock settings
 416  */
 417 /* RDH = 1
 418  * PH  = 0
 419  * VFS = 0
 420  * BFS = 0
 421  * SSS = 0
 422  */
 423 #define CFG_PSSR_VAL            0x00000030
 424
 425 #define CFG_CKEN_VAL            0x00000080  /*  */
 426 #define CFG_ICMR_VAL            0x00000000  /* No interrupts enabled        */
 427
 428
 429 /*
 430  * Memory settings
 431  *
 432  * This is the configuration for nCS0/1 -> flash banks
 433  * configuration for nCS1 :
 434  * [31]    0    -
 435  * [30:28] 000  -
 436  * [27:24] 0000 -
 437  * [23:20] 0000 -
 438  * [19]    0    -
 439  * [18:16] 000  -
 440  * configuration for nCS0:
 441  * [15]    0    - Slower Device
 442  * [14:12] 010  - CS deselect to CS time: 2*(2*MemClk) = 40 ns
 443  * [11:08] 0011 - Address to data valid in bursts: (3+1)*MemClk = 40 ns
 444  * [07:04] 1111 - " for first access: (23+2)*MemClk = 250 ns (fixme 12+2?)
 445  * [03]    0    - 32 Bit bus width
 446  * [02:00] 010  - burst OF 4 ROM or FLASH
 447 */
 448 #define CFG_MSC0_VAL            0x000023D2
 449
 450 /* This is the configuration for nCS2/3 -> USB controller, LAN
 451  * configuration for nCS3: LAN
 452  * [31]    0    - Slower Device
 453  * [30:28] 001  - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
 454  * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
 455  * [23:20] 0010 - RDF3: Address for first access: (2+1)*MemClk = 30 ns
 456  * [19]    0    - 32 Bit bus width
 457  * [18:16] 100  - variable latency I/O
 458  * configuration for nCS2: USB
 459  * [15]    1    - Faster Device
 460  * [14:12] 010  - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns
 461  * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns
 462  * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns
 463  * [03]    1    - 16 Bit bus width
 464  * [02:00] 100  - variable latency I/O
 465  */
 466 #define CFG_MSC1_VAL            0x1224A26C
 467
 468 /* This is the configuration for nCS4/5 -> LAN
 469  * configuration for nCS5:
 470  * [31]    0    -
 471  * [30:28] 000  -
 472  * [27:24] 0000 -
 473  * [23:20] 0000 -
 474  * [19]    0    -
 475  * [18:16] 000  -
 476  * configuration for nCS4: LAN
 477  * [15]    1    - Faster Device
 478  * [14:12] 010  - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns
 479  * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns
 480  * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns
 481  * [03]    0    - 32 Bit bus width
 482  * [02:00] 100  - variable latency I/O
 483  */
 484 #define CFG_MSC2_VAL            0x00001224
 485
 486 /* MDCNFG: SDRAM Configuration Register
 487  *
 488  * [31:29]   000 - reserved
 489  * [28]      0   - no SA1111 compatiblity mode
 490  * [27]      0   - latch return data with return clock
 491  * [26]      0   - alternate addressing for pair 2/3
 492  * [25:24]   00  - timings
 493  * [23]      0   - internal banks in lower partition 2/3 (not used)
 494  * [22:21]   00  - row address bits for partition 2/3 (not used)
 495  * [20:19]   00  - column address bits for partition 2/3 (not used)
 496  * [18]      0   - SDRAM partition 2/3 width is 32 bit
 497  * [17]      0   - SDRAM partition 3 disabled
 498  * [16]      0   - SDRAM partition 2 disabled
 499  * [15:13]   000 - reserved
 500  * [12]      0   - no SA1111 compatiblity mode
 501  * [11]      1   - latch return data with return clock
 502  * [10]      0   - no alternate addressing for pair 0/1
 503  * [09:08]   10  - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
 504  * [7]       1   - 4 internal banks in lower partition pair
 505  * [06:05]   10  - 13 row address bits for partition 0/1
 506  * [04:03]   01  - 9 column address bits for partition 0/1
 507  * [02]      0   - SDRAM partition 0/1 width is 32 bit
 508  * [01]      0   - disable SDRAM partition 1
 509  * [00]      1   - enable  SDRAM partition 0
 510  */
 511 /* use the configuration above but disable partition 0 */
 512 #define CFG_MDCNFG_VAL          0x00000AC9
 513
 514 /* MDREFR: SDRAM Refresh Control Register
 515  *
 516  * [32:26] 0     - reserved
 517  * [25]    0     - K2FREE: not free running
 518  * [24]    0     - K1FREE: not free running
 519  * [23]    0     - K0FREE: not free running
 520  * [22]    0     - SLFRSH: self refresh disabled
 521  * [21]    0     - reserved
 522  * [20]    1     - APD: auto power down
 523  * [19]    0     - K2DB2: SDCLK2 is MemClk
 524  * [18]    0     - K2RUN: disable SDCLK2
 525  * [17]    0     - K1DB2: SDCLK1 is MemClk
 526  * [16]    1     - K1RUN: enable SDCLK1
 527  * [15]    1     - E1PIN: SDRAM clock enable
 528  * [14]    0     - K0DB2: SDCLK0 is MemClk
 529  * [13]    0     - K0RUN: disable SDCLK0
 530  * [12]    0     - E0PIN: disable SDCKE0
 531  * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
 532  */
 533 #define CFG_MDREFR_VAL          0x00138018 /* mh: was 0x00118018 */
 534
 535 /* MDMRS: Mode Register Set Configuration Register
 536  *
 537  * [31]      0       - reserved
 538  * [30:23]   00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
 539  * [22:20]   011     - MDCL2:  SDRAM2/3 Cas Latency.  (not used)
 540  * [19]      0       - MDADD2: SDRAM2/3 burst Type. Fixed to sequential.  (not used)
 541  * [18:16]   010     - MDBL2:  SDRAM2/3 burst Length. Fixed to 4.  (not used)
 542  * [15]      0       - reserved
 543  * [14:07]   00000000- MDMRS0: SDRAM0/1 MRS Value.
 544  * [06:04]   011     - MDCL0:  SDRAM0/1 Cas Latency.
 545  * [03]      0       - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
 546  * [02:00]   010     - MDBL0:  SDRAM0/1 burst Length. Fixed to 4.
 547  */
 548 #define CFG_MDMRS_VAL           0x00320032
 549
 550 /*
 551  * PCMCIA and CF Interfaces
 552  */
 553 #define CFG_MECR_VAL            0x00000000
 554 #define CFG_MCMEM0_VAL          0x00010504
 555 #define CFG_MCMEM1_VAL          0x00010504
 556 #define CFG_MCATT0_VAL          0x00010504
 557 #define CFG_MCATT1_VAL          0x00010504
 558 #define CFG_MCIO0_VAL           0x00004715
 559 #define CFG_MCIO1_VAL           0x00004715
 560
 561
 562 #endif  /* __CONFIG_H */