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git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/xpedite517x.h
684388723f1d1b8ffacb73648d033f05085ad04c
2 * Copyright 2009 Extreme Engineering Solutions, Inc.
3 * Copyright 2007-2008 Freescale Semiconductor, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
9 * xpedite517x board configuration file
15 * High Level Configuration Options
17 #define CONFIG_MPC8641 1 /* MPC8641 specific */
18 #define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */
19 #define CONFIG_SYS_BOARD_NAME "XPedite5170"
20 #define CONFIG_SYS_FORM_3U_VPX 1
21 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
22 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
23 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */
24 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
25 #define CONFIG_ALTIVEC 1
27 #define CONFIG_SYS_TEXT_BASE 0xfff00000
29 #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
30 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
31 #define CONFIG_PCIE1 1 /* PCIE controller 1 */
32 #define CONFIG_PCIE2 1 /* PCIE controller 2 */
33 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
34 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
35 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
36 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
41 #define CONFIG_SYS_FSL_DDR2
42 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
43 #define CONFIG_DDR_SPD
44 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
45 #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
46 #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
47 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
48 #define CONFIG_NUM_DDR_CONTROLLERS 2
49 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
50 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
51 #define CONFIG_DDR_ECC
52 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
53 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
54 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
55 #define CONFIG_VERY_BIG_RAM
56 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
59 * virtual address to be used for temporary mappings. There
60 * should be 128k free at this VA.
62 #define CONFIG_SYS_SCRATCH_VA 0xe0000000
65 extern unsigned long get_board_sys_clk(unsigned long dummy
);
68 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */
75 #define L2_ENABLE (L2CR_L2E)
78 * Base addresses -- Note these are effective addresses where the
79 * actual resources get mapped (not physical addresses)
81 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
82 #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
83 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
84 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
85 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
86 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
91 #define CONFIG_SYS_ALT_MEMTEST
92 #define CONFIG_SYS_MEMTEST_START 0x10000000
93 #define CONFIG_SYS_MEMTEST_END 0x20000000
94 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY |\
96 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_DS1621_ADDR, \
97 CONFIG_SYS_I2C_DS4510_ADDR, \
98 CONFIG_SYS_I2C_EEPROM_ADDR, \
99 CONFIG_SYS_I2C_LM90_ADDR, \
100 CONFIG_SYS_I2C_PCA9553_ADDR, \
101 CONFIG_SYS_I2C_PCA953X_ADDR0, \
102 CONFIG_SYS_I2C_PCA953X_ADDR1, \
103 CONFIG_SYS_I2C_PCA953X_ADDR2, \
104 CONFIG_SYS_I2C_PCA953X_ADDR3, \
105 CONFIG_SYS_I2C_PEX8518_ADDR, \
106 CONFIG_SYS_I2C_RTC_ADDR}
107 /* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */
108 #define I2C_ADDR_IGNORE_LIST {0x50}
112 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
113 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
114 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
115 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
116 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
117 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
118 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
119 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
120 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
121 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
124 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
127 * NAND flash configuration
129 #define CONFIG_SYS_NAND_BASE 0xef800000
130 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
131 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2}
132 #define CONFIG_SYS_MAX_NAND_DEVICE 2
133 #define CONFIG_NAND_ACTL
134 #define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */
135 #define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */
136 #define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */
137 #define CONFIG_SYS_NAND_ACTL_DELAY 25
138 #define CONFIG_JFFS2_NAND
141 * NOR flash configuration
143 #define CONFIG_SYS_FLASH_BASE 0xf8000000
144 #define CONFIG_SYS_FLASH_BASE2 0xf0000000
145 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
146 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
147 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
148 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
149 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
150 #define CONFIG_FLASH_CFI_DRIVER
151 #define CONFIG_SYS_FLASH_CFI
152 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
153 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \
154 {0xf7f00000, 0xc0000} }
155 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
156 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
159 * Chip select configuration
161 /* NOR Flash 0 on CS0 */
162 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
165 #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\
174 /* NOR Flash 1 on CS1 */
175 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\
178 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
180 /* NAND flash on CS2 */
181 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\
184 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\
192 /* Optional NAND flash on CS3 */
193 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\
196 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
199 * Use L1 as initial stack
201 #define CONFIG_SYS_INIT_RAM_LOCK 1
202 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
203 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
205 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
206 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
208 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
209 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
214 #define CONFIG_CONS_INDEX 1
215 #define CONFIG_SYS_NS16550_SERIAL
216 #define CONFIG_SYS_NS16550_REG_SIZE 1
217 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
218 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
219 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
220 #define CONFIG_SYS_BAUDRATE_TABLE \
221 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
222 #define CONFIG_BAUDRATE 115200
223 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
224 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
229 #define CONFIG_SYS_I2C
230 #define CONFIG_SYS_I2C_FSL
231 #define CONFIG_SYS_FSL_I2C_SPEED 100000
232 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
233 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
234 #define CONFIG_SYS_FSL_I2C2_SPEED 100000
235 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
236 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
238 /* PEX8518 slave I2C interface */
239 #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
241 /* I2C DS1631 temperature sensor */
242 #define CONFIG_SYS_I2C_DS1621_ADDR 0x48
243 #define CONFIG_DTT_DS1621
244 #define CONFIG_DTT_SENSORS { 0 }
245 #define CONFIG_SYS_I2C_LM90_ADDR 0x4c
247 /* I2C EEPROM - AT24C128B */
248 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
249 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
250 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
251 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
254 #define CONFIG_RTC_M41T11 1
255 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
256 #define CONFIG_SYS_M41T11_BASE_YEAR 2000
258 /* GPIO/EEPROM/SRAM */
259 #define CONFIG_DS4510
260 #define CONFIG_SYS_I2C_DS4510_ADDR 0x51
263 #define CONFIG_PCA953X
264 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
265 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
266 #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
267 #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
268 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
269 #define CONFIG_SYS_I2C_PCA9553_ADDR 0x62
272 * PU = pulled high, PD = pulled low
273 * I = input, O = output, IO = input/output
276 #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
277 #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
278 #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
279 #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
280 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
281 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
284 #define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
285 #define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */
286 #define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
287 #define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
288 #define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
289 #define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
290 #define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
291 #define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
294 #define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
295 #define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
296 #define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
297 #define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
298 #define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
299 #define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */
300 #define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */
303 #define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */
304 #define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */
305 #define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */
306 #define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */
310 * Memory space is mapped 1-1, but I/O space must start from 0.
312 /* PCIE1 - PEX8518 */
313 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
314 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
315 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
316 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
317 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
318 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
321 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
322 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
323 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
324 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
325 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
326 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
331 #define CONFIG_TSEC_ENET /* tsec ethernet support */
332 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
333 #define CONFIG_MII 1 /* MII PHY management */
334 #define CONFIG_ETHPRIME "eTSEC1"
336 #define CONFIG_TSEC1 1
337 #define CONFIG_TSEC1_NAME "eTSEC1"
338 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
339 #define TSEC1_PHY_ADDR 1
340 #define TSEC1_PHYIDX 0
341 #define CONFIG_HAS_ETH0
343 #define CONFIG_TSEC2 1
344 #define CONFIG_TSEC2_NAME "eTSEC2"
345 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
346 #define TSEC2_PHY_ADDR 2
347 #define TSEC2_PHYIDX 0
348 #define CONFIG_HAS_ETH1
353 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
354 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
358 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\
362 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
365 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
369 * BAT0 2G Cacheable, non-guarded
372 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
373 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
374 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
375 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
378 * BAT1 1G Cache-inhibited, guarded
379 * 0x8000_0000 1G PCI-Express 1 Memory
381 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
385 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\
389 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
392 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
395 * BAT2 512M Cache-inhibited, guarded
396 * 0xc000_0000 512M PCI-Express 2 Memory
398 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
402 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\
406 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
409 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
412 * BAT3 1M Cache-inhibited, guarded
413 * 0xe000_0000 1M CCSR
415 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\
419 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\
423 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\
426 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
429 * BAT4 32M Cache-inhibited, guarded
430 * 0xe200_0000 16M PCI-Express 1 I/O
431 * 0xe300_0000 16M PCI-Express 2 I/0
433 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
437 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\
441 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
444 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
447 * BAT5 128K Cacheable, non-guarded
448 * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory)
450 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\
453 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\
457 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
458 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
461 * BAT6 256M Cache-inhibited, guarded
462 * 0xf000_0000 256M FLASH
464 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\
468 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\
472 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\
475 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
477 /* Map the last 1M of flash where we're running from reset */
478 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
482 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE |\
486 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
489 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
492 * BAT7 64M Cache-inhibited, guarded
493 * 0xe800_0000 64K NAND FLASH
494 * 0xe804_0000 128K DUART Registers
496 #define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\
500 #define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\
504 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\
507 #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
510 * Command configuration.
512 #define CONFIG_CMD_DATE
513 #define CONFIG_CMD_DS4510
514 #define CONFIG_CMD_DS4510_INFO
515 #define CONFIG_CMD_DTT
516 #define CONFIG_CMD_EEPROM
517 #define CONFIG_CMD_IRQ
518 #define CONFIG_CMD_JFFS2
519 #define CONFIG_CMD_NAND
520 #define CONFIG_CMD_PCA953X
521 #define CONFIG_CMD_PCA953X_INFO
522 #define CONFIG_CMD_PCI
523 #define CONFIG_CMD_PCI_ENUM
524 #define CONFIG_CMD_REGINFO
527 * Miscellaneous configurable options
529 #define CONFIG_SYS_LONGHELP /* undef to save memory */
530 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
531 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
532 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
533 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
534 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
535 #define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */
536 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
537 #define CONFIG_PANIC_HANG /* do not reset board on panic */
538 #define CONFIG_PREBOOT /* enable preboot variable */
539 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
542 * For booting Linux, the board info and command line data
543 * have to be in the first 16 MB of memory, since this is
544 * the maximum mapped by the Linux kernel during initialization.
546 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
547 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
550 * Environment Configuration
552 #define CONFIG_ENV_IS_IN_FLASH 1
553 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
554 #define CONFIG_ENV_SIZE 0x8000
555 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
559 * fffc0000 - ffffffff Pri FDT (256KB)
560 * fff80000 - fffbffff Pri U-Boot Environment (256 KB)
561 * fff00000 - fff7ffff Pri U-Boot (512 KB)
562 * fef00000 - ffefffff Pri OS image (16MB)
563 * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
565 * f7fc0000 - f7ffffff Sec FDT (256KB)
566 * f7f80000 - f7fbffff Sec U-Boot Environment (256 KB)
567 * f7f00000 - f7f7ffff Sec U-Boot (512 KB)
568 * f6f00000 - f7efffff Sec OS image (16MB)
569 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
571 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff00000)
572 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f00000)
573 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfffc0000)
574 #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7fc0000)
575 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
576 #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
578 #define CONFIG_PROG_UBOOT1 \
579 "$download_cmd $loadaddr $ubootfile; " \
580 "if test $? -eq 0; then " \
581 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
582 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
583 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
584 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
585 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
586 "if test $? -ne 0; then " \
587 "echo PROGRAM FAILED; " \
589 "echo PROGRAM SUCCEEDED; " \
592 "echo DOWNLOAD FAILED; " \
595 #define CONFIG_PROG_UBOOT2 \
596 "$download_cmd $loadaddr $ubootfile; " \
597 "if test $? -eq 0; then " \
598 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
599 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
600 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
601 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
602 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
603 "if test $? -ne 0; then " \
604 "echo PROGRAM FAILED; " \
606 "echo PROGRAM SUCCEEDED; " \
609 "echo DOWNLOAD FAILED; " \
612 #define CONFIG_BOOT_OS_NET \
613 "$download_cmd $osaddr $osfile; " \
614 "if test $? -eq 0; then " \
615 "if test -n $fdtaddr; then " \
616 "$download_cmd $fdtaddr $fdtfile; " \
617 "if test $? -eq 0; then " \
618 "bootm $osaddr - $fdtaddr; " \
620 "echo FDT DOWNLOAD FAILED; " \
626 "echo OS DOWNLOAD FAILED; " \
629 #define CONFIG_PROG_OS1 \
630 "$download_cmd $osaddr $osfile; " \
631 "if test $? -eq 0; then " \
632 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
633 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
634 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
635 "if test $? -ne 0; then " \
636 "echo OS PROGRAM FAILED; " \
638 "echo OS PROGRAM SUCCEEDED; " \
641 "echo OS DOWNLOAD FAILED; " \
644 #define CONFIG_PROG_OS2 \
645 "$download_cmd $osaddr $osfile; " \
646 "if test $? -eq 0; then " \
647 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
648 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
649 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
650 "if test $? -ne 0; then " \
651 "echo OS PROGRAM FAILED; " \
653 "echo OS PROGRAM SUCCEEDED; " \
656 "echo OS DOWNLOAD FAILED; " \
659 #define CONFIG_PROG_FDT1 \
660 "$download_cmd $fdtaddr $fdtfile; " \
661 "if test $? -eq 0; then " \
662 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
663 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
664 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
665 "if test $? -ne 0; then " \
666 "echo FDT PROGRAM FAILED; " \
668 "echo FDT PROGRAM SUCCEEDED; " \
671 "echo FDT DOWNLOAD FAILED; " \
674 #define CONFIG_PROG_FDT2 \
675 "$download_cmd $fdtaddr $fdtfile; " \
676 "if test $? -eq 0; then " \
677 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
678 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
679 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
680 "if test $? -ne 0; then " \
681 "echo FDT PROGRAM FAILED; " \
683 "echo FDT PROGRAM SUCCEEDED; " \
686 "echo FDT DOWNLOAD FAILED; " \
689 #define CONFIG_EXTRA_ENV_SETTINGS \
691 "download_cmd=tftp\0" \
692 "console_args=console=ttyS0,115200\0" \
693 "root_args=root=/dev/nfs rw\0" \
694 "misc_args=ip=on\0" \
695 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
696 "bootfile=/home/user/file\0" \
697 "osfile=/home/user/board.uImage\0" \
698 "fdtfile=/home/user/board.dtb\0" \
699 "ubootfile=/home/user/u-boot.bin\0" \
700 "fdtaddr=0x1e00000\0" \
701 "osaddr=0x1000000\0" \
702 "loadaddr=0x1000000\0" \
703 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
704 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
705 "prog_os1="CONFIG_PROG_OS1"\0" \
706 "prog_os2="CONFIG_PROG_OS2"\0" \
707 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
708 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
709 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
710 "bootcmd_flash1=run set_bootargs; " \
711 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
712 "bootcmd_flash2=run set_bootargs; " \
713 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
714 "bootcmd=run bootcmd_flash1\0"
715 #endif /* __CONFIG_H */