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Convert CONFIG_USE_PREBOOT and CONFIG_PREBOOT to Kconfig
[thirdparty/u-boot.git] / include / configs / xpedite520x.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright 2008 Extreme Engineering Solutions, Inc.
4 * Copyright 2004-2008 Freescale Semiconductor, Inc.
5 */
6
7 /*
8 * xpedite520x board configuration file
9 */
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12
13 /*
14 * High Level Configuration Options
15 */
16 #define CONFIG_SYS_BOARD_NAME "XPedite5200"
17 #define CONFIG_SYS_FORM_PMC_XMC 1
18
19 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
20 #define CONFIG_PCI1 1 /* PCI controller 1 */
21 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
22 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
23 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
24
25 /*
26 * DDR config
27 */
28 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
29 #define CONFIG_DDR_SPD
30 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
31 #define SPD_EEPROM_ADDRESS 0x54
32 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
33 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
34 #define CONFIG_DDR_ECC
35 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
36 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
37 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
38 #define CONFIG_VERY_BIG_RAM
39
40 #define CONFIG_SYS_CLK_FREQ 66666666
41
42 /*
43 * These can be toggled for performance analysis, otherwise use default.
44 */
45 #define CONFIG_L2_CACHE /* toggle L2 cache */
46 #define CONFIG_BTB /* toggle branch predition */
47 #define CONFIG_ENABLE_36BIT_PHYS 1
48
49 #define CONFIG_SYS_CCSRBAR 0xef000000
50 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
51
52 /*
53 * Diagnostics
54 */
55 #define CONFIG_SYS_MEMTEST_START 0x10000000
56 #define CONFIG_SYS_MEMTEST_END 0x20000000
57 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
58 CONFIG_SYS_POST_I2C)
59 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_MAX1237_ADDR, \
60 CONFIG_SYS_I2C_EEPROM_ADDR, \
61 CONFIG_SYS_I2C_PCA953X_ADDR0, \
62 CONFIG_SYS_I2C_PCA953X_ADDR1, \
63 CONFIG_SYS_I2C_RTC_ADDR}
64
65 /*
66 * Memory map
67 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
68 * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable
69 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
70 * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable
71 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
72 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
73 * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable
74 * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable
75 */
76
77 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
78
79 /*
80 * NAND flash configuration
81 */
82 #define CONFIG_SYS_NAND_BASE 0xef800000
83 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
84 #define CONFIG_SYS_MAX_NAND_DEVICE 1
85 #define CONFIG_NAND_ACTL
86 #define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */
87 #define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */
88 #define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */
89 #define CONFIG_SYS_NAND_ACTL_DELAY 25
90
91 /*
92 * NOR flash configuration
93 */
94 #define CONFIG_SYS_FLASH_BASE 0xfc000000
95 #define CONFIG_SYS_FLASH_BASE2 0xf8000000
96 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
97 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
98 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
99 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
100 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
101 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
102 {0xfbf40000, 0xc0000} }
103 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
104
105 /*
106 * Chip select configuration
107 */
108 /* NOR Flash 0 on CS0 */
109 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
110 BR_PS_16 | \
111 BR_V)
112 #define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | \
113 OR_GPCM_ACS_DIV4 | \
114 OR_GPCM_SCY_8)
115
116 /* NOR Flash 1 on CS1 */
117 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
118 BR_PS_16 | \
119 BR_V)
120 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
121
122 /* NAND flash on CS2 */
123 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
124 BR_PS_8 | \
125 BR_V)
126
127 /* NAND flash on CS2 */
128 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
129 OR_GPCM_BCTLD | \
130 OR_GPCM_CSNT | \
131 OR_GPCM_ACS_DIV4 | \
132 OR_GPCM_SCY_4 | \
133 OR_GPCM_TRLX | \
134 OR_GPCM_EHTR)
135
136 /* NAND flash on CS3 */
137 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
138 BR_PS_8 | \
139 BR_V)
140 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
141
142 /*
143 * Use L1 as initial stack
144 */
145 #define CONFIG_SYS_INIT_RAM_LOCK 1
146 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
147 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000
148
149 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
150 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
151
152 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
153 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
154
155 /*
156 * Serial Port
157 */
158 #define CONFIG_SYS_NS16550_SERIAL
159 #define CONFIG_SYS_NS16550_REG_SIZE 1
160 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
161 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
162 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
163 #define CONFIG_SYS_BAUDRATE_TABLE \
164 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
165 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
166 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
167
168 /*
169 * I2C
170 */
171 #define CONFIG_SYS_I2C
172 #define CONFIG_SYS_I2C_FSL
173 #define CONFIG_SYS_FSL_I2C_SPEED 400000
174 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
175 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
176 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
177 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
178 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
179
180 /* I2C EEPROM */
181 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
182 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
183 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
184 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
185
186 /* I2C RTC */
187 #define CONFIG_RTC_M41T11 1
188 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
189 #define CONFIG_SYS_M41T11_BASE_YEAR 2000
190
191 /* GPIO */
192 #define CONFIG_PCA953X
193 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
194 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19
195 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
196
197 /* PCA957 @ 0x18 */
198 #define CONFIG_SYS_PCA953X_BRD_CFG0 0x01
199 #define CONFIG_SYS_PCA953X_BRD_CFG1 0x02
200 #define CONFIG_SYS_PCA953X_BRD_CFG2 0x04
201 #define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08
202 #define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10
203 #define CONFIG_SYS_PCA953X_NVM_WP 0x20
204 #define CONFIG_SYS_PCA953X_MONARCH 0x40
205 #define CONFIG_SYS_PCA953X_EREADY 0x80
206
207 /* PCA957 @ 0x19 */
208 #define CONFIG_SYS_PCA953X_P14_IO0 0x01
209 #define CONFIG_SYS_PCA953X_P14_IO1 0x02
210 #define CONFIG_SYS_PCA953X_P14_IO2 0x04
211 #define CONFIG_SYS_PCA953X_P14_IO3 0x08
212 #define CONFIG_SYS_PCA953X_P14_IO4 0x10
213 #define CONFIG_SYS_PCA953X_P14_IO5 0x20
214 #define CONFIG_SYS_PCA953X_P14_IO6 0x40
215 #define CONFIG_SYS_PCA953X_P14_IO7 0x80
216
217 /* 12-bit ADC used to measure CPU diode */
218 #define CONFIG_SYS_I2C_MAX1237_ADDR 0x34
219
220 /*
221 * General PCI
222 * Memory space is mapped 1-1, but I/O space must start from 0.
223 */
224 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
225 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
226 #define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */
227 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
228 #define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000
229 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */
230
231 /*
232 * Networking options
233 */
234 #define CONFIG_ETHPRIME "eTSEC1"
235
236 #define CONFIG_TSEC1 1
237 #define CONFIG_TSEC1_NAME "eTSEC1"
238 #define TSEC1_FLAGS TSEC_GIGABIT
239 #define TSEC1_PHY_ADDR 1
240 #define TSEC1_PHYIDX 0
241 #define CONFIG_HAS_ETH0
242
243 #define CONFIG_TSEC2 1
244 #define CONFIG_TSEC2_NAME "eTSEC2"
245 #define TSEC2_FLAGS TSEC_GIGABIT
246 #define TSEC2_PHY_ADDR 2
247 #define TSEC2_PHYIDX 0
248 #define CONFIG_HAS_ETH1
249
250 #define CONFIG_TSEC3 1
251 #define CONFIG_TSEC3_NAME "eTSEC3"
252 #define TSEC3_FLAGS TSEC_GIGABIT
253 #define TSEC3_PHY_ADDR 3
254 #define TSEC3_PHYIDX 0
255 #define CONFIG_HAS_ETH2
256
257 #define CONFIG_TSEC4 1
258 #define CONFIG_TSEC4_NAME "eTSEC4"
259 #define TSEC4_FLAGS TSEC_GIGABIT
260 #define TSEC4_PHY_ADDR 4
261 #define TSEC4_PHYIDX 0
262 #define CONFIG_HAS_ETH3
263
264 /*
265 * BOOTP options
266 */
267 #define CONFIG_BOOTP_BOOTFILESIZE
268
269 /*
270 * Miscellaneous configurable options
271 */
272 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
273 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
274 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
275 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
276
277 /*
278 * For booting Linux, the board info and command line data
279 * have to be in the first 16 MB of memory, since this is
280 * the maximum mapped by the Linux kernel during initialization.
281 */
282 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
283 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
284
285 /*
286 * Environment Configuration
287 */
288 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
289 #define CONFIG_ENV_SIZE 0x8000
290 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
291
292 /*
293 * Flash memory map:
294 * fff80000 - ffffffff Pri U-Boot (512 KB)
295 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
296 * fff00000 - fff3ffff Pri FDT (256KB)
297 * fef00000 - ffefffff Pri OS image (16MB)
298 * fc000000 - feefffff Pri OS Use/Filesystem (47MB)
299 *
300 * fbf80000 - fbffffff Sec U-Boot (512 KB)
301 * fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB)
302 * fbf00000 - fbf3ffff Sec FDT (256KB)
303 * faf00000 - fbefffff Sec OS image (16MB)
304 * f8000000 - faefffff Sec OS Use/Filesystem (47MB)
305 */
306 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
307 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xfbf80000)
308 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
309 #define CONFIG_FDT2_ENV_ADDR __stringify(0xfbf00000)
310 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
311 #define CONFIG_OS2_ENV_ADDR __stringify(0xfaf00000)
312
313 #define CONFIG_PROG_UBOOT1 \
314 "$download_cmd $loadaddr $ubootfile; " \
315 "if test $? -eq 0; then " \
316 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
317 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
318 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
319 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
320 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
321 "if test $? -ne 0; then " \
322 "echo PROGRAM FAILED; " \
323 "else; " \
324 "echo PROGRAM SUCCEEDED; " \
325 "fi; " \
326 "else; " \
327 "echo DOWNLOAD FAILED; " \
328 "fi;"
329
330 #define CONFIG_PROG_UBOOT2 \
331 "$download_cmd $loadaddr $ubootfile; " \
332 "if test $? -eq 0; then " \
333 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
334 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
335 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
336 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
337 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
338 "if test $? -ne 0; then " \
339 "echo PROGRAM FAILED; " \
340 "else; " \
341 "echo PROGRAM SUCCEEDED; " \
342 "fi; " \
343 "else; " \
344 "echo DOWNLOAD FAILED; " \
345 "fi;"
346
347 #define CONFIG_BOOT_OS_NET \
348 "$download_cmd $osaddr $osfile; " \
349 "if test $? -eq 0; then " \
350 "if test -n $fdtaddr; then " \
351 "$download_cmd $fdtaddr $fdtfile; " \
352 "if test $? -eq 0; then " \
353 "bootm $osaddr - $fdtaddr; " \
354 "else; " \
355 "echo FDT DOWNLOAD FAILED; " \
356 "fi; " \
357 "else; " \
358 "bootm $osaddr; " \
359 "fi; " \
360 "else; " \
361 "echo OS DOWNLOAD FAILED; " \
362 "fi;"
363
364 #define CONFIG_PROG_OS1 \
365 "$download_cmd $osaddr $osfile; " \
366 "if test $? -eq 0; then " \
367 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
368 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
369 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
370 "if test $? -ne 0; then " \
371 "echo OS PROGRAM FAILED; " \
372 "else; " \
373 "echo OS PROGRAM SUCCEEDED; " \
374 "fi; " \
375 "else; " \
376 "echo OS DOWNLOAD FAILED; " \
377 "fi;"
378
379 #define CONFIG_PROG_OS2 \
380 "$download_cmd $osaddr $osfile; " \
381 "if test $? -eq 0; then " \
382 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
383 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
384 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
385 "if test $? -ne 0; then " \
386 "echo OS PROGRAM FAILED; " \
387 "else; " \
388 "echo OS PROGRAM SUCCEEDED; " \
389 "fi; " \
390 "else; " \
391 "echo OS DOWNLOAD FAILED; " \
392 "fi;"
393
394 #define CONFIG_PROG_FDT1 \
395 "$download_cmd $fdtaddr $fdtfile; " \
396 "if test $? -eq 0; then " \
397 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
398 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
399 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
400 "if test $? -ne 0; then " \
401 "echo FDT PROGRAM FAILED; " \
402 "else; " \
403 "echo FDT PROGRAM SUCCEEDED; " \
404 "fi; " \
405 "else; " \
406 "echo FDT DOWNLOAD FAILED; " \
407 "fi;"
408
409 #define CONFIG_PROG_FDT2 \
410 "$download_cmd $fdtaddr $fdtfile; " \
411 "if test $? -eq 0; then " \
412 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
413 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
414 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
415 "if test $? -ne 0; then " \
416 "echo FDT PROGRAM FAILED; " \
417 "else; " \
418 "echo FDT PROGRAM SUCCEEDED; " \
419 "fi; " \
420 "else; " \
421 "echo FDT DOWNLOAD FAILED; " \
422 "fi;"
423
424 #define CONFIG_EXTRA_ENV_SETTINGS \
425 "autoload=yes\0" \
426 "download_cmd=tftp\0" \
427 "console_args=console=ttyS0,115200\0" \
428 "root_args=root=/dev/nfs rw\0" \
429 "misc_args=ip=on\0" \
430 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
431 "bootfile=/home/user/file\0" \
432 "osfile=/home/user/board.uImage\0" \
433 "fdtfile=/home/user/board.dtb\0" \
434 "ubootfile=/home/user/u-boot.bin\0" \
435 "fdtaddr=0x1e00000\0" \
436 "osaddr=0x1000000\0" \
437 "loadaddr=0x1000000\0" \
438 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
439 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
440 "prog_os1="CONFIG_PROG_OS1"\0" \
441 "prog_os2="CONFIG_PROG_OS2"\0" \
442 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
443 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
444 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
445 "bootcmd_flash1=run set_bootargs; " \
446 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
447 "bootcmd_flash2=run set_bootargs; " \
448 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
449 "bootcmd=run bootcmd_flash1\0"
450 #endif /* __CONFIG_H */