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1 /*
2 * Copyright 2008 Extreme Engineering Solutions, Inc.
3 * Copyright 2004-2008 Freescale Semiconductor, Inc.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 /*
9 * xpedite520x board configuration file
10 */
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 /*
15 * High Level Configuration Options
16 */
17 #define CONFIG_BOOKE 1 /* BOOKE */
18 #define CONFIG_E500 1 /* BOOKE e500 family */
19 #define CONFIG_MPC8548 1
20 #define CONFIG_XPEDITE5200 1
21 #define CONFIG_SYS_BOARD_NAME "XPedite5200"
22 #define CONFIG_SYS_FORM_PMC_XMC 1
23 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
24
25 #ifndef CONFIG_SYS_TEXT_BASE
26 #define CONFIG_SYS_TEXT_BASE 0xfff80000
27 #endif
28
29 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
30 #define CONFIG_PCI1 1 /* PCI controller 1 */
31 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
32 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
33 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
34 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
35
36 /*
37 * DDR config
38 */
39 #define CONFIG_SYS_FSL_DDR2
40 #undef CONFIG_FSL_DDR_INTERACTIVE
41 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
42 #define CONFIG_DDR_SPD
43 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
44 #define SPD_EEPROM_ADDRESS 0x54
45 #define CONFIG_NUM_DDR_CONTROLLERS 1
46 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
47 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
48 #define CONFIG_DDR_ECC
49 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
50 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
51 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
52 #define CONFIG_VERY_BIG_RAM
53
54 #define CONFIG_SYS_CLK_FREQ 66666666
55
56 /*
57 * These can be toggled for performance analysis, otherwise use default.
58 */
59 #define CONFIG_L2_CACHE /* toggle L2 cache */
60 #define CONFIG_BTB /* toggle branch predition */
61 #define CONFIG_ENABLE_36BIT_PHYS 1
62
63 #define CONFIG_SYS_CCSRBAR 0xef000000
64 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
65
66 /*
67 * Diagnostics
68 */
69 #define CONFIG_SYS_ALT_MEMTEST
70 #define CONFIG_SYS_MEMTEST_START 0x10000000
71 #define CONFIG_SYS_MEMTEST_END 0x20000000
72 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
73 CONFIG_SYS_POST_I2C)
74 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_MAX1237_ADDR, \
75 CONFIG_SYS_I2C_EEPROM_ADDR, \
76 CONFIG_SYS_I2C_PCA953X_ADDR0, \
77 CONFIG_SYS_I2C_PCA953X_ADDR1, \
78 CONFIG_SYS_I2C_RTC_ADDR}
79
80 /*
81 * Memory map
82 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
83 * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable
84 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
85 * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable
86 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
87 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
88 * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable
89 * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable
90 */
91
92 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
93
94 /*
95 * NAND flash configuration
96 */
97 #define CONFIG_SYS_NAND_BASE 0xef800000
98 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
99 #define CONFIG_SYS_MAX_NAND_DEVICE 1
100 #define CONFIG_NAND_ACTL
101 #define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */
102 #define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */
103 #define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */
104 #define CONFIG_SYS_NAND_ACTL_DELAY 25
105
106 /*
107 * NOR flash configuration
108 */
109 #define CONFIG_SYS_FLASH_BASE 0xfc000000
110 #define CONFIG_SYS_FLASH_BASE2 0xf8000000
111 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
112 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
113 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
114 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
115 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
116 #define CONFIG_FLASH_CFI_DRIVER
117 #define CONFIG_SYS_FLASH_CFI
118 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
119 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
120 {0xfbf40000, 0xc0000} }
121 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
122
123 /*
124 * Chip select configuration
125 */
126 /* NOR Flash 0 on CS0 */
127 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
128 BR_PS_16 | \
129 BR_V)
130 #define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | \
131 OR_GPCM_ACS_DIV4 | \
132 OR_GPCM_SCY_8)
133
134 /* NOR Flash 1 on CS1 */
135 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
136 BR_PS_16 | \
137 BR_V)
138 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
139
140 /* NAND flash on CS2 */
141 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
142 BR_PS_8 | \
143 BR_V)
144
145 /* NAND flash on CS2 */
146 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
147 OR_GPCM_BCTLD | \
148 OR_GPCM_CSNT | \
149 OR_GPCM_ACS_DIV4 | \
150 OR_GPCM_SCY_4 | \
151 OR_GPCM_TRLX | \
152 OR_GPCM_EHTR)
153
154 /* NAND flash on CS3 */
155 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
156 BR_PS_8 | \
157 BR_V)
158 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
159
160 /*
161 * Use L1 as initial stack
162 */
163 #define CONFIG_SYS_INIT_RAM_LOCK 1
164 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
165 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000
166
167 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
168 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
169
170 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
171 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
172
173 /*
174 * Serial Port
175 */
176 #define CONFIG_CONS_INDEX 1
177 #define CONFIG_SYS_NS16550_SERIAL
178 #define CONFIG_SYS_NS16550_REG_SIZE 1
179 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
180 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
181 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
182 #define CONFIG_SYS_BAUDRATE_TABLE \
183 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
184 #define CONFIG_BAUDRATE 115200
185 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
186 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
187
188 /*
189 * I2C
190 */
191 #define CONFIG_SYS_I2C
192 #define CONFIG_SYS_I2C_FSL
193 #define CONFIG_SYS_FSL_I2C_SPEED 400000
194 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
195 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
196 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
197 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
198 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
199
200 /* I2C EEPROM */
201 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
202 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
203 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
204 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
205
206 /* I2C RTC */
207 #define CONFIG_RTC_M41T11 1
208 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
209 #define CONFIG_SYS_M41T11_BASE_YEAR 2000
210
211 /* GPIO */
212 #define CONFIG_PCA953X
213 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
214 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19
215 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
216
217 /* PCA957 @ 0x18 */
218 #define CONFIG_SYS_PCA953X_BRD_CFG0 0x01
219 #define CONFIG_SYS_PCA953X_BRD_CFG1 0x02
220 #define CONFIG_SYS_PCA953X_BRD_CFG2 0x04
221 #define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08
222 #define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10
223 #define CONFIG_SYS_PCA953X_NVM_WP 0x20
224 #define CONFIG_SYS_PCA953X_MONARCH 0x40
225 #define CONFIG_SYS_PCA953X_EREADY 0x80
226
227 /* PCA957 @ 0x19 */
228 #define CONFIG_SYS_PCA953X_P14_IO0 0x01
229 #define CONFIG_SYS_PCA953X_P14_IO1 0x02
230 #define CONFIG_SYS_PCA953X_P14_IO2 0x04
231 #define CONFIG_SYS_PCA953X_P14_IO3 0x08
232 #define CONFIG_SYS_PCA953X_P14_IO4 0x10
233 #define CONFIG_SYS_PCA953X_P14_IO5 0x20
234 #define CONFIG_SYS_PCA953X_P14_IO6 0x40
235 #define CONFIG_SYS_PCA953X_P14_IO7 0x80
236
237 /* 12-bit ADC used to measure CPU diode */
238 #define CONFIG_SYS_I2C_MAX1237_ADDR 0x34
239
240 /*
241 * General PCI
242 * Memory space is mapped 1-1, but I/O space must start from 0.
243 */
244 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
245 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
246 #define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */
247 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
248 #define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000
249 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */
250
251 /*
252 * Networking options
253 */
254 #define CONFIG_TSEC_ENET /* tsec ethernet support */
255 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
256 #define CONFIG_MII 1 /* MII PHY management */
257 #define CONFIG_ETHPRIME "eTSEC1"
258
259 #define CONFIG_TSEC1 1
260 #define CONFIG_TSEC1_NAME "eTSEC1"
261 #define TSEC1_FLAGS TSEC_GIGABIT
262 #define TSEC1_PHY_ADDR 1
263 #define TSEC1_PHYIDX 0
264 #define CONFIG_HAS_ETH0
265
266 #define CONFIG_TSEC2 1
267 #define CONFIG_TSEC2_NAME "eTSEC2"
268 #define TSEC2_FLAGS TSEC_GIGABIT
269 #define TSEC2_PHY_ADDR 2
270 #define TSEC2_PHYIDX 0
271 #define CONFIG_HAS_ETH1
272
273 #define CONFIG_TSEC3 1
274 #define CONFIG_TSEC3_NAME "eTSEC3"
275 #define TSEC3_FLAGS TSEC_GIGABIT
276 #define TSEC3_PHY_ADDR 3
277 #define TSEC3_PHYIDX 0
278 #define CONFIG_HAS_ETH2
279
280 #define CONFIG_TSEC4 1
281 #define CONFIG_TSEC4_NAME "eTSEC4"
282 #define TSEC4_FLAGS TSEC_GIGABIT
283 #define TSEC4_PHY_ADDR 4
284 #define TSEC4_PHYIDX 0
285 #define CONFIG_HAS_ETH3
286
287 /*
288 * BOOTP options
289 */
290 #define CONFIG_BOOTP_BOOTFILESIZE
291 #define CONFIG_BOOTP_BOOTPATH
292 #define CONFIG_BOOTP_GATEWAY
293
294 /*
295 * Command configuration.
296 */
297 #define CONFIG_CMD_DATE
298 #define CONFIG_CMD_EEPROM
299 #define CONFIG_CMD_JFFS2
300 #define CONFIG_CMD_NAND
301 #define CONFIG_CMD_PCA953X
302 #define CONFIG_CMD_PCA953X_INFO
303 #define CONFIG_CMD_PCI
304 #define CONFIG_CMD_PCI_ENUM
305 #define CONFIG_CMD_REGINFO
306
307 /*
308 * Miscellaneous configurable options
309 */
310 #define CONFIG_SYS_LONGHELP /* undef to save memory */
311 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
312 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
313 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
314 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
315 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
316 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
317 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
318 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
319 #define CONFIG_PANIC_HANG /* do not reset board on panic */
320 #define CONFIG_PREBOOT /* enable preboot variable */
321 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
322 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
323
324 /*
325 * For booting Linux, the board info and command line data
326 * have to be in the first 16 MB of memory, since this is
327 * the maximum mapped by the Linux kernel during initialization.
328 */
329 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
330 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
331
332 /*
333 * Environment Configuration
334 */
335 #define CONFIG_ENV_IS_IN_FLASH 1
336 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
337 #define CONFIG_ENV_SIZE 0x8000
338 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
339
340 /*
341 * Flash memory map:
342 * fff80000 - ffffffff Pri U-Boot (512 KB)
343 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
344 * fff00000 - fff3ffff Pri FDT (256KB)
345 * fef00000 - ffefffff Pri OS image (16MB)
346 * fc000000 - feefffff Pri OS Use/Filesystem (47MB)
347 *
348 * fbf80000 - fbffffff Sec U-Boot (512 KB)
349 * fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB)
350 * fbf00000 - fbf3ffff Sec FDT (256KB)
351 * faf00000 - fbefffff Sec OS image (16MB)
352 * f8000000 - faefffff Sec OS Use/Filesystem (47MB)
353 */
354 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
355 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xfbf80000)
356 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
357 #define CONFIG_FDT2_ENV_ADDR __stringify(0xfbf00000)
358 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
359 #define CONFIG_OS2_ENV_ADDR __stringify(0xfaf00000)
360
361 #define CONFIG_PROG_UBOOT1 \
362 "$download_cmd $loadaddr $ubootfile; " \
363 "if test $? -eq 0; then " \
364 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
365 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
366 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
367 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
368 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
369 "if test $? -ne 0; then " \
370 "echo PROGRAM FAILED; " \
371 "else; " \
372 "echo PROGRAM SUCCEEDED; " \
373 "fi; " \
374 "else; " \
375 "echo DOWNLOAD FAILED; " \
376 "fi;"
377
378 #define CONFIG_PROG_UBOOT2 \
379 "$download_cmd $loadaddr $ubootfile; " \
380 "if test $? -eq 0; then " \
381 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
382 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
383 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
384 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
385 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
386 "if test $? -ne 0; then " \
387 "echo PROGRAM FAILED; " \
388 "else; " \
389 "echo PROGRAM SUCCEEDED; " \
390 "fi; " \
391 "else; " \
392 "echo DOWNLOAD FAILED; " \
393 "fi;"
394
395 #define CONFIG_BOOT_OS_NET \
396 "$download_cmd $osaddr $osfile; " \
397 "if test $? -eq 0; then " \
398 "if test -n $fdtaddr; then " \
399 "$download_cmd $fdtaddr $fdtfile; " \
400 "if test $? -eq 0; then " \
401 "bootm $osaddr - $fdtaddr; " \
402 "else; " \
403 "echo FDT DOWNLOAD FAILED; " \
404 "fi; " \
405 "else; " \
406 "bootm $osaddr; " \
407 "fi; " \
408 "else; " \
409 "echo OS DOWNLOAD FAILED; " \
410 "fi;"
411
412 #define CONFIG_PROG_OS1 \
413 "$download_cmd $osaddr $osfile; " \
414 "if test $? -eq 0; then " \
415 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
416 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
417 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
418 "if test $? -ne 0; then " \
419 "echo OS PROGRAM FAILED; " \
420 "else; " \
421 "echo OS PROGRAM SUCCEEDED; " \
422 "fi; " \
423 "else; " \
424 "echo OS DOWNLOAD FAILED; " \
425 "fi;"
426
427 #define CONFIG_PROG_OS2 \
428 "$download_cmd $osaddr $osfile; " \
429 "if test $? -eq 0; then " \
430 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
431 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
432 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
433 "if test $? -ne 0; then " \
434 "echo OS PROGRAM FAILED; " \
435 "else; " \
436 "echo OS PROGRAM SUCCEEDED; " \
437 "fi; " \
438 "else; " \
439 "echo OS DOWNLOAD FAILED; " \
440 "fi;"
441
442 #define CONFIG_PROG_FDT1 \
443 "$download_cmd $fdtaddr $fdtfile; " \
444 "if test $? -eq 0; then " \
445 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
446 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
447 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
448 "if test $? -ne 0; then " \
449 "echo FDT PROGRAM FAILED; " \
450 "else; " \
451 "echo FDT PROGRAM SUCCEEDED; " \
452 "fi; " \
453 "else; " \
454 "echo FDT DOWNLOAD FAILED; " \
455 "fi;"
456
457 #define CONFIG_PROG_FDT2 \
458 "$download_cmd $fdtaddr $fdtfile; " \
459 "if test $? -eq 0; then " \
460 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
461 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
462 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
463 "if test $? -ne 0; then " \
464 "echo FDT PROGRAM FAILED; " \
465 "else; " \
466 "echo FDT PROGRAM SUCCEEDED; " \
467 "fi; " \
468 "else; " \
469 "echo FDT DOWNLOAD FAILED; " \
470 "fi;"
471
472 #define CONFIG_EXTRA_ENV_SETTINGS \
473 "autoload=yes\0" \
474 "download_cmd=tftp\0" \
475 "console_args=console=ttyS0,115200\0" \
476 "root_args=root=/dev/nfs rw\0" \
477 "misc_args=ip=on\0" \
478 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
479 "bootfile=/home/user/file\0" \
480 "osfile=/home/user/board.uImage\0" \
481 "fdtfile=/home/user/board.dtb\0" \
482 "ubootfile=/home/user/u-boot.bin\0" \
483 "fdtaddr=0x1e00000\0" \
484 "osaddr=0x1000000\0" \
485 "loadaddr=0x1000000\0" \
486 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
487 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
488 "prog_os1="CONFIG_PROG_OS1"\0" \
489 "prog_os2="CONFIG_PROG_OS2"\0" \
490 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
491 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
492 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
493 "bootcmd_flash1=run set_bootargs; " \
494 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
495 "bootcmd_flash2=run set_bootargs; " \
496 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
497 "bootcmd=run bootcmd_flash1\0"
498 #endif /* __CONFIG_H */