include/configs/xpedite550x.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2010 Extreme Engineering Solutions, Inc.
   4  * Copyright 2007-2008 Freescale Semiconductor, Inc.
   5  */
   6
   7 /*
   8  * xpedite550x board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /*
  14  * High Level Configuration Options
  15  */
  16 #define CONFIG_SYS_BOARD_NAME   "XPedite5500"
  17 #define CONFIG_SYS_FORM_PMC_XMC 1
  18 #define CONFIG_PRPMC_PCI_ALIAS  "pci0"  /* Processor PMC interface on pci0 */
  19
  20 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup */
  21 #define CONFIG_PCIE1            1       /* PCIE controller 1 (PEX8112 or XMC) */
  22 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  23 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  24 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  25
  26 /*
  27  * Multicore config
  28  */
  29 #define CONFIG_BPTR_VIRT_ADDR   0xee000000      /* virt boot page address */
  30 #define CONFIG_MPC8xxx_DISABLE_BPTR             /* Don't leave BPTR enabled */
  31
  32 /*
  33  * DDR config
  34  */
  35 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  36 #define CONFIG_DDR_SPD
  37 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  38 #define SPD_EEPROM_ADDRESS                      0x54
  39 #define SPD_EEPROM_OFFSET               0x200   /* OFFSET of SPD in EEPROM */
  40 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  41 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
  42 #define CONFIG_DDR_ECC
  43 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  44 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000 /* DDR is system memory*/
  45 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  46 #define CONFIG_VERY_BIG_RAM
  47
  48 #ifndef __ASSEMBLY__
  49 #include <linux/stringify.h>
  50 extern unsigned long get_board_sys_clk(unsigned long dummy);
  51 extern unsigned long get_board_ddr_clk(unsigned long dummy);
  52 #endif
  53
  54 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /* sysclk for MPC85xx */
  55 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk(0) /* ddrclk for MPC85xx */
  56
  57 /*
  58  * These can be toggled for performance analysis, otherwise use default.
  59  */
  60 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  61 #define CONFIG_BTB                      /* toggle branch predition */
  62 #define CONFIG_ENABLE_36BIT_PHYS        1
  63
  64 #define CONFIG_SYS_CCSRBAR              0xef000000
  65 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  66
  67 /*
  68  * Diagnostics
  69  */
  70 #define CONFIG_POST                     (CONFIG_SYS_POST_MEMORY | \
  71                                          CONFIG_SYS_POST_I2C)
  72 #define I2C_ADDR_LIST                   {CONFIG_SYS_I2C_EEPROM_ADDR,    \
  73                                          CONFIG_SYS_I2C_LM75_ADDR,      \
  74                                          CONFIG_SYS_I2C_LM90_ADDR,      \
  75                                          CONFIG_SYS_I2C_PCA953X_ADDR0,  \
  76                                          CONFIG_SYS_I2C_PCA953X_ADDR2,  \
  77                                          CONFIG_SYS_I2C_PCA953X_ADDR3,  \
  78                                          CONFIG_SYS_I2C_RTC_ADDR}
  79
  80 /*
  81  * Memory map
  82  * 0x0000_0000 0x7fff_ffff      DDR                     2G Cacheable
  83  * 0x8000_0000 0xbfff_ffff      PCIe1 Mem               1G non-cacheable
  84  * 0xe000_0000 0xe7ff_ffff      SRAM/SSRAM/L1 Cache     128M non-cacheable
  85  * 0xe800_0000 0xe87f_ffff      PCIe1 IO                8M non-cacheable
  86  * 0xee00_0000 0xee00_ffff      Boot page translation   4K non-cacheable
  87  * 0xef00_0000 0xef0f_ffff      CCSR/IMMR               1M non-cacheable
  88  * 0xef80_0000 0xef8f_ffff      NAND Flash              1M non-cacheable
  89  * 0xf000_0000 0xf7ff_ffff      NOR Flash 2             128M non-cacheable
  90  * 0xf800_0000 0xffff_ffff      NOR Flash 1             128M non-cacheable
  91  */
  92
  93 #define CONFIG_SYS_LBC_LCRR     (LCRR_CLKDIV_8 | LCRR_EADC_3)
  94
  95 /*
  96  * NAND flash configuration
  97  */
  98 #define CONFIG_SYS_NAND_BASE            0xef800000
  99 #define CONFIG_SYS_NAND_BASE2           0xef840000 /* Unused at this time */
 100 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE, \
 101                                          CONFIG_SYS_NAND_BASE2}
 102 #define CONFIG_SYS_MAX_NAND_DEVICE      2
 103 #define CONFIG_NAND_FSL_ELBC
 104
 105 /*
 106  * NOR flash configuration
 107  */
 108 #define CONFIG_SYS_FLASH_BASE           0xf8000000
 109 #define CONFIG_SYS_FLASH_BASE2          0xf0000000
 110 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
 111 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 112 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 113 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 114 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 115 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST       { {0xfff40000, 0xc0000}, \
 116                                                   {0xf7f40000, 0xc0000} }
 117 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 118
 119 /*
 120  * Chip select configuration
 121  */
 122 /* NOR Flash 0 on CS0 */
 123 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE  | \
 124                                  BR_PS_16               | \
 125                                  BR_V)
 126 #define CONFIG_SYS_OR0_PRELIM   (OR_AM_128MB            | \
 127                                  OR_GPCM_CSNT           | \
 128                                  OR_GPCM_XACS           | \
 129                                  OR_GPCM_ACS_DIV2       | \
 130                                  OR_GPCM_SCY_8          | \
 131                                  OR_GPCM_TRLX           | \
 132                                  OR_GPCM_EHTR           | \
 133                                  OR_GPCM_EAD)
 134
 135 /* NOR Flash 1 on CS1 */
 136 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_FLASH_BASE2 | \
 137                                  BR_PS_16               | \
 138                                  BR_V)
 139 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 140
 141 /* NAND flash on CS2 */
 142 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_NAND_BASE   | \
 143                                  (2<<BR_DECC_SHIFT)     | \
 144                                  BR_PS_8                | \
 145                                  BR_MS_FCM              | \
 146                                  BR_V)
 147
 148 /* NAND flash on CS2 */
 149 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_256KB    | \
 150                                  OR_FCM_PGS     | \
 151                                  OR_FCM_CSCT    | \
 152                                  OR_FCM_CST     | \
 153                                  OR_FCM_CHT     | \
 154                                  OR_FCM_SCY_1   | \
 155                                  OR_FCM_TRLX    | \
 156                                  OR_FCM_EHTR)
 157
 158 /* NAND flash on CS3 */
 159 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_NAND_BASE2  | \
 160                                  (2<<BR_DECC_SHIFT)     | \
 161                                  BR_PS_8                | \
 162                                  BR_MS_FCM              | \
 163                                  BR_V)
 164 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 165
 166 /*
 167  * Use L1 as initial stack
 168  */
 169 #define CONFIG_SYS_INIT_RAM_LOCK        1
 170 #define CONFIG_SYS_INIT_RAM_ADDR        0xe0000000
 171 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 172
 173 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 174 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 175
 176 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 KB for Mon */
 177 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 178
 179 /*
 180  * Serial Port
 181  */
 182 #define CONFIG_SYS_NS16550_SERIAL
 183 #define CONFIG_SYS_NS16550_REG_SIZE     1
 184 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 185 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 186 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 187 #define CONFIG_SYS_BAUDRATE_TABLE       \
 188         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 189 #define CONFIG_LOADS_ECHO               1       /* echo on for serial download */
 190 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 191
 192
 193 /*
 194  * I2C
 195  */
 196 #define CONFIG_SYS_I2C
 197 #define CONFIG_SYS_I2C_FSL
 198 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 199 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 200 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 201 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 202 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 203 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 204
 205 /* I2C DS7505 temperature sensor */
 206 #define CONFIG_SYS_I2C_LM75_ADDR        0x48
 207
 208 /* I2C ADT7461 temperature sensor */
 209 #define CONFIG_SYS_I2C_LM90_ADDR        0x4C
 210
 211 /* I2C EEPROM - AT24C128B */
 212 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x54
 213 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 214 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6       /* 64 byte pages */
 215 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* take up to 10 msec */
 216
 217 /* I2C RTC */
 218 #define CONFIG_RTC_M41T11               1
 219 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 220 #define CONFIG_SYS_M41T11_BASE_YEAR     2000
 221
 222 /* GPIO */
 223 #define CONFIG_PCA953X
 224 #define CONFIG_SYS_I2C_PCA953X_ADDR0    0x18
 225 #define CONFIG_SYS_I2C_PCA953X_ADDR1    0x1c
 226 #define CONFIG_SYS_I2C_PCA953X_ADDR2    0x1e
 227 #define CONFIG_SYS_I2C_PCA953X_ADDR3    0x1f
 228 #define CONFIG_SYS_I2C_PCA953X_ADDR     CONFIG_SYS_I2C_PCA953X_ADDR0
 229
 230 /*
 231  * GPIO pin definitions, PU = pulled high, PD = pulled low
 232  */
 233 /* PCA9557 @ 0x18*/
 234 #define CONFIG_SYS_PCA953X_C0_SER0_EN           0x01 /* PU; UART0 enable (1: enabled) */
 235 #define CONFIG_SYS_PCA953X_C0_SER0_MODE         0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232) */
 236 #define CONFIG_SYS_PCA953X_C0_SER1_EN           0x04 /* PU; UART1 enable (1: enabled) */
 237 #define CONFIG_SYS_PCA953X_C0_SER1_MODE         0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232) */
 238 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS     0x10 /* PU; Boot flash CS select */
 239 #define CONFIG_SYS_PCA953X_NVM_WP               0x20 /* PU; Write protection (0: disabled, 1: enabled) */
 240
 241 /* PCA9557 @ 0x1e*/
 242 #define CONFIG_SYS_PCA953X_XMC_GA0              0x01 /* PU; */
 243 #define CONFIG_SYS_PCA953X_XMC_GA1              0x02 /* PU; */
 244 #define CONFIG_SYS_PCA953X_XMC_GA2              0x04 /* PU; */
 245 #define CONFIG_SYS_PCA953X_XMC_WAKE             0x10 /* PU; */
 246 #define CONFIG_SYS_PCA953X_XMC_BIST             0x20 /* Enable XMC BIST */
 247 #define CONFIG_SYS_PCA953X_PMC_EREADY           0x40 /* PU; PMC PCI eready */
 248 #define CONFIG_SYS_PCA953X_PMC_MONARCH          0x80 /* PMC monarch mode enable */
 249
 250 /* PCA9557 @ 0x1f */
 251 #define CONFIG_SYS_PCA953X_MC_GPIO0             0x01 /* PU; */
 252 #define CONFIG_SYS_PCA953X_MC_GPIO1             0x02 /* PU; */
 253 #define CONFIG_SYS_PCA953X_MC_GPIO2             0x04 /* PU; */
 254 #define CONFIG_SYS_PCA953X_MC_GPIO3             0x08 /* PU; */
 255 #define CONFIG_SYS_PCA953X_MC_GPIO4             0x10 /* PU; */
 256 #define CONFIG_SYS_PCA953X_MC_GPIO5             0x20 /* PU; */
 257 #define CONFIG_SYS_PCA953X_MC_GPIO6             0x40 /* PU; */
 258 #define CONFIG_SYS_PCA953X_MC_GPIO7             0x80 /* PU; */
 259
 260 /*
 261  * General PCI
 262  * Memory space is mapped 1-1, but I/O space must start from 0.
 263  */
 264
 265 /* controller 1 - PEX8112 or XMC, depending on build option */
 266 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 267 #define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BUS
 268 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x40000000      /* 1G */
 269 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 270 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe8000000
 271 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000      /* 8M */
 272
 273 /*
 274  * Networking options
 275  */
 276 #define CONFIG_TSEC_TBI
 277 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 278 #define CONFIG_ETHPRIME         "eTSEC2"
 279
 280 /*
 281  * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
 282  * 1000mbps SGMII link
 283  */
 284 #define CONFIG_TSEC_TBICR_SETTINGS ( \
 285                 TBICR_PHY_RESET \
 286                 | TBICR_FULL_DUPLEX \
 287                 | TBICR_SPEED1_SET \
 288                 )
 289
 290 #define CONFIG_TSEC1            1
 291 #define CONFIG_TSEC1_NAME       "eTSEC1"
 292 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 293 #define TSEC1_PHY_ADDR          1
 294 #define TSEC1_PHYIDX            0
 295 #define CONFIG_HAS_ETH0
 296
 297 #define CONFIG_TSEC2            1
 298 #define CONFIG_TSEC2_NAME       "eTSEC2"
 299 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 300 #define TSEC2_PHY_ADDR          2
 301 #define TSEC2_PHYIDX            0
 302 #define CONFIG_HAS_ETH1
 303
 304 #define CONFIG_TSEC3            1
 305 #define CONFIG_TSEC3_NAME       "eTSEC3"
 306 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 307 #define TSEC3_PHY_ADDR          3
 308 #define TSEC3_PHYIDX            0
 309 #define CONFIG_HAS_ETH2
 310
 311 /*
 312  * USB
 313  */
 314 #define CONFIG_USB_EHCI_FSL
 315 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 316
 317 /*
 318  * Miscellaneous configurable options
 319  */
 320 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 321 #define CONFIG_LOADADDR         0x1000000       /* default location for tftp and bootm */
 322 #define CONFIG_INTEGRITY                        /* support booting INTEGRITY OS */
 323
 324 /*
 325  * For booting Linux, the board info and command line data
 326  * have to be in the first 16 MB of memory, since this is
 327  * the maximum mapped by the Linux kernel during initialization.
 328  */
 329 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20)      /* Initial Memory map for Linux*/
 330 #define CONFIG_SYS_BOOTM_LEN    (16 << 20)      /* Increase max gunzip size */
 331
 332 /*
 333  * Environment Configuration
 334  */
 335
 336 /*
 337  * Flash memory map:
 338  * fff80000 - ffffffff     Pri U-Boot (512 KB)
 339  * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
 340  * fff00000 - fff3ffff     Pri FDT (256KB)
 341  * fef00000 - ffefffff     Pri OS image (16MB)
 342  * f8000000 - feefffff     Pri OS Use/Filesystem (111MB)
 343  *
 344  * f7f80000 - f7ffffff     Sec U-Boot (512 KB)
 345  * f7f40000 - f7f7ffff     Sec U-Boot Environment (256 KB)
 346  * f7f00000 - f7f3ffff     Sec FDT (256KB)
 347  * f6f00000 - f7efffff     Sec OS image (16MB)
 348  * f0000000 - f6efffff     Sec OS Use/Filesystem (111MB)
 349  */
 350 #define CONFIG_UBOOT1_ENV_ADDR  __stringify(0xfff80000)
 351 #define CONFIG_UBOOT2_ENV_ADDR  __stringify(0xf7f80000)
 352 #define CONFIG_FDT1_ENV_ADDR    __stringify(0xfff00000)
 353 #define CONFIG_FDT2_ENV_ADDR    __stringify(0xf7f00000)
 354 #define CONFIG_OS1_ENV_ADDR     __stringify(0xfef00000)
 355 #define CONFIG_OS2_ENV_ADDR     __stringify(0xf6f00000)
 356
 357 #define CONFIG_PROG_UBOOT1                                              \
 358         "$download_cmd $loadaddr $ubootfile; "                          \
 359         "if test $? -eq 0; then "                                       \
 360                 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "         \
 361                 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "               \
 362                 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "       \
 363                 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "          \
 364                 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "      \
 365                 "if test $? -ne 0; then "                               \
 366                         "echo PROGRAM FAILED; "                         \
 367                 "else; "                                                \
 368                         "echo PROGRAM SUCCEEDED; "                      \
 369                 "fi; "                                                  \
 370         "else; "                                                        \
 371                 "echo DOWNLOAD FAILED; "                                \
 372         "fi;"
 373
 374 #define CONFIG_PROG_UBOOT2                                              \
 375         "$download_cmd $loadaddr $ubootfile; "                          \
 376         "if test $? -eq 0; then "                                       \
 377                 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "         \
 378                 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "               \
 379                 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "       \
 380                 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "          \
 381                 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "      \
 382                 "if test $? -ne 0; then "                               \
 383                         "echo PROGRAM FAILED; "                         \
 384                 "else; "                                                \
 385                         "echo PROGRAM SUCCEEDED; "                      \
 386                 "fi; "                                                  \
 387         "else; "                                                        \
 388                 "echo DOWNLOAD FAILED; "                                \
 389         "fi;"
 390
 391 #define CONFIG_BOOT_OS_NET                                              \
 392         "$download_cmd $osaddr $osfile; "                               \
 393         "if test $? -eq 0; then "                                       \
 394                 "if test -n $fdtaddr; then "                            \
 395                         "$download_cmd $fdtaddr $fdtfile; "             \
 396                         "if test $? -eq 0; then "                       \
 397                                 "bootm $osaddr - $fdtaddr; "            \
 398                         "else; "                                        \
 399                                 "echo FDT DOWNLOAD FAILED; "            \
 400                         "fi; "                                          \
 401                 "else; "                                                \
 402                         "bootm $osaddr; "                               \
 403                 "fi; "                                                  \
 404         "else; "                                                        \
 405                 "echo OS DOWNLOAD FAILED; "                             \
 406         "fi;"
 407
 408 #define CONFIG_PROG_OS1                                                 \
 409         "$download_cmd $osaddr $osfile; "                               \
 410         "if test $? -eq 0; then "                                       \
 411                 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; "              \
 412                 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "        \
 413                 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "       \
 414                 "if test $? -ne 0; then "                               \
 415                         "echo OS PROGRAM FAILED; "                      \
 416                 "else; "                                                \
 417                         "echo OS PROGRAM SUCCEEDED; "                   \
 418                 "fi; "                                                  \
 419         "else; "                                                        \
 420                 "echo OS DOWNLOAD FAILED; "                             \
 421         "fi;"
 422
 423 #define CONFIG_PROG_OS2                                                 \
 424         "$download_cmd $osaddr $osfile; "                               \
 425         "if test $? -eq 0; then "                                       \
 426                 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; "              \
 427                 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "        \
 428                 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "       \
 429                 "if test $? -ne 0; then "                               \
 430                         "echo OS PROGRAM FAILED; "                      \
 431                 "else; "                                                \
 432                         "echo OS PROGRAM SUCCEEDED; "                   \
 433                 "fi; "                                                  \
 434         "else; "                                                        \
 435                 "echo OS DOWNLOAD FAILED; "                             \
 436         "fi;"
 437
 438 #define CONFIG_PROG_FDT1                                                \
 439         "$download_cmd $fdtaddr $fdtfile; "                             \
 440         "if test $? -eq 0; then "                                       \
 441                 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"              \
 442                 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "      \
 443                 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "     \
 444                 "if test $? -ne 0; then "                               \
 445                         "echo FDT PROGRAM FAILED; "                     \
 446                 "else; "                                                \
 447                         "echo FDT PROGRAM SUCCEEDED; "                  \
 448                 "fi; "                                                  \
 449         "else; "                                                        \
 450                 "echo FDT DOWNLOAD FAILED; "                            \
 451         "fi;"
 452
 453 #define CONFIG_PROG_FDT2                                                \
 454         "$download_cmd $fdtaddr $fdtfile; "                             \
 455         "if test $? -eq 0; then "                                       \
 456                 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"              \
 457                 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "      \
 458                 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "     \
 459                 "if test $? -ne 0; then "                               \
 460                         "echo FDT PROGRAM FAILED; "                     \
 461                 "else; "                                                \
 462                         "echo FDT PROGRAM SUCCEEDED; "                  \
 463                 "fi; "                                                  \
 464         "else; "                                                        \
 465                 "echo FDT DOWNLOAD FAILED; "                            \
 466         "fi;"
 467
 468 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 469         "autoload=yes\0"                                                \
 470         "download_cmd=tftp\0"                                           \
 471         "console_args=console=ttyS0,115200\0"                           \
 472         "root_args=root=/dev/nfs rw\0"                                  \
 473         "misc_args=ip=on\0"                                             \
 474         "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
 475         "bootfile=/home/user/file\0"                                    \
 476         "osfile=/home/user/board.uImage\0"                              \
 477         "fdtfile=/home/user/board.dtb\0"                                \
 478         "ubootfile=/home/user/u-boot.bin\0"                             \
 479         "fdtaddr=0x1e00000\0"                                           \
 480         "osaddr=0x1000000\0"                                            \
 481         "loadaddr=0x1000000\0"                                          \
 482         "prog_uboot1="CONFIG_PROG_UBOOT1"\0"                            \
 483         "prog_uboot2="CONFIG_PROG_UBOOT2"\0"                            \
 484         "prog_os1="CONFIG_PROG_OS1"\0"                                  \
 485         "prog_os2="CONFIG_PROG_OS2"\0"                                  \
 486         "prog_fdt1="CONFIG_PROG_FDT1"\0"                                \
 487         "prog_fdt2="CONFIG_PROG_FDT2"\0"                                \
 488         "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"          \
 489         "bootcmd_flash1=run set_bootargs; "                             \
 490                 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
 491         "bootcmd_flash2=run set_bootargs; "                             \
 492                 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
 493         "bootcmd=run bootcmd_flash1\0"
 494 #endif  /* __CONFIG_H */