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git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/yosemite.h
2 * (C) Copyright 2005-2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /************************************************************************
25 * yosemite.h - configuration for Yosemite & Yellowstone boards
26 ***********************************************************************/
30 /*-----------------------------------------------------------------------
31 * High Level Configuration Options
32 *----------------------------------------------------------------------*/
33 /* This config file is used for Yosemite (440EP) and Yellowstone (440GR)*/
34 #ifndef CONFIG_YELLOWSTONE
35 #define CONFIG_440EP 1 /* Specific PPC440EP support */
36 #define CONFIG_HOSTNAME yosemite
38 #define CONFIG_440GR 1 /* Specific PPC440GR support */
39 #define CONFIG_HOSTNAME yellowstone
41 #define CONFIG_440 1 /* ... PPC440 family */
42 #define CONFIG_4xx 1 /* ... PPC4xx family */
43 #define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
45 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
46 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
47 #define CONFIG_BOARD_RESET 1 /* call board_reset() */
49 /*-----------------------------------------------------------------------
50 * Base addresses -- Note these are effective addresses where the
51 * actual resources get mapped (not physical addresses)
52 *----------------------------------------------------------------------*/
53 #define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
54 #define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
55 #define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
56 #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
57 #define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
58 #define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
59 #define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
60 #define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
61 #define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
63 /*Don't change either of these*/
64 #define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/
65 #define CFG_PCI_BASE 0xe0000000 /* internal PCI regs*/
66 /*Don't change either of these*/
68 #define CFG_USB_DEVICE 0x50000000
69 #define CFG_NVRAM_BASE_ADDR 0x80000000
70 #define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000)
71 #define CFG_BOOT_BASE_ADDR 0xf0000000
73 /*-----------------------------------------------------------------------
74 * Initial RAM & stack pointer (placed in SDRAM)
75 *----------------------------------------------------------------------*/
76 #define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */
77 #define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
78 #define CFG_INIT_RAM_END (8 << 10)
79 #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/
80 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
81 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
83 /*-----------------------------------------------------------------------
85 *----------------------------------------------------------------------*/
86 #define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
87 #define CONFIG_BAUDRATE 115200
88 #define CONFIG_SERIAL_MULTI 1
89 /*define this if you want console on UART1*/
90 #undef CONFIG_UART1_CONSOLE
92 #define CFG_BAUDRATE_TABLE \
93 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
95 /*-----------------------------------------------------------------------
97 *----------------------------------------------------------------------*/
99 * Define here the location of the environment variables (FLASH or EEPROM).
100 * Note: DENX encourages to use redundant environment in FLASH.
103 #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
105 #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
108 /*-----------------------------------------------------------------------
110 *----------------------------------------------------------------------*/
111 #define CFG_FLASH_CFI /* The flash is CFI compatible */
112 #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
113 #define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */
115 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
116 #define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
118 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
119 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
121 #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
123 #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
125 #ifdef CFG_ENV_IS_IN_FLASH
126 #define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
127 #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
128 #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
130 /* Address and size of Redundant Environment Sector */
131 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
132 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
133 #endif /* CFG_ENV_IS_IN_FLASH */
135 /*-----------------------------------------------------------------------
137 *----------------------------------------------------------------------*/
138 #undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
139 #define CFG_KBYTES_SDRAM (128 * 1024) /* 128MB */
140 #define CFG_SDRAM_BANKS (2)
143 /*-----------------------------------------------------------------------
145 *----------------------------------------------------------------------*/
146 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
147 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
148 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
149 #define CFG_I2C_SLAVE 0x7F
151 #define CFG_I2C_MULTI_EEPROMS
152 #define CFG_I2C_EEPROM_ADDR (0xa8>>1)
153 #define CFG_I2C_EEPROM_ADDR_LEN 1
154 #define CFG_EEPROM_PAGE_WRITE_ENABLE
155 #define CFG_EEPROM_PAGE_WRITE_BITS 3
156 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
158 #ifdef CFG_ENV_IS_IN_EEPROM
159 #define CFG_ENV_SIZE 0x200 /* Size of Environment vars */
160 #define CFG_ENV_OFFSET 0x0
161 #endif /* CFG_ENV_IS_IN_EEPROM */
163 #define CONFIG_PREBOOT "echo;" \
164 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
167 #undef CONFIG_BOOTARGS
169 /* Setup some board specific values for the default environment variables */
170 #ifndef CONFIG_YELLOWSTONE
171 #define CONFIG_HOSTNAME yosemite
172 #define CFG_BOOTFILE "bootfile=/tftpboot/yosemite/uImage\0"
173 #define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0"
175 #define CONFIG_HOSTNAME yellowstone
176 #define CFG_BOOTFILE "bootfile=/tftpboot/yellowstone/uImage\0"
177 #define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xx\0"
180 #define CONFIG_EXTRA_ENV_SETTINGS \
184 "nfsargs=setenv bootargs root=/dev/nfs rw " \
185 "nfsroot=${serverip}:${rootpath}\0" \
186 "ramargs=setenv bootargs root=/dev/ram rw\0" \
187 "addip=setenv bootargs ${bootargs} " \
188 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
189 ":${hostname}:${netdev}:off panic=1\0" \
190 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
191 "flash_nfs=run nfsargs addip addtty;" \
192 "bootm ${kernel_addr}\0" \
193 "flash_self=run ramargs addip addtty;" \
194 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
195 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
197 "bootfile=/tftpboot/${hostname}/uImage\0" \
198 "kernel_addr=fc000000\0" \
199 "ramdisk_addr=fc180000\0" \
200 "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
201 "update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \
202 "cp.b 200000 fff80000 80000;" \
203 "setenv filesize;saveenv\0" \
204 "upd=run load;run update\0" \
206 #define CONFIG_BOOTCOMMAND "run flash_self"
209 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
211 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
214 #define CONFIG_BAUDRATE 115200
216 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
217 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
219 #define CONFIG_MII 1 /* MII PHY management */
220 #define CONFIG_NET_MULTI 1 /* required for netconsole */
221 #define CONFIG_PHY1_ADDR 3
222 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
223 #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
225 #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
227 #define CONFIG_NETCONSOLE /* include NetConsole support */
230 #define CONFIG_MAC_PARTITION
231 #define CONFIG_DOS_PARTITION
232 #define CONFIG_ISO_PARTITION
236 #define CONFIG_USB_OHCI
237 #define CONFIG_USB_STORAGE
239 /* Comment this out to enable USB 1.1 device */
240 #define USB_2_0_DEVICE
242 #define CMD_USB (CFG_CMD_USB | CFG_CMD_FAT | CFG_CMD_EXT2)
244 #define CONFIG_SUPPORT_VFAT
246 #define CMD_USB 0 /* no USB on 440GR */
247 #endif /* CONFIG_440EP */
250 #define CONFIG_PANIC_HANG
252 #define CONFIG_HW_WATCHDOG /* watchdog */
255 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
272 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
273 #include <cmd_confdefs.h>
276 * Miscellaneous configurable options
278 #define CFG_LONGHELP /* undef to save memory */
279 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
280 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
281 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
283 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
285 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
286 #define CFG_MAXARGS 16 /* max number of command args */
287 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
289 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
290 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
292 #define CFG_LOAD_ADDR 0x100000 /* default load address */
293 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
294 #define CONFIG_LYNXKDI 1 /* support kdi files */
296 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
298 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
299 #define CONFIG_LOOPW 1 /* enable loopw command */
300 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
301 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
302 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
304 /*-----------------------------------------------------------------------
306 *-----------------------------------------------------------------------
309 #define CONFIG_PCI /* include pci support */
310 #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
311 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
312 #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
314 /* Board-specific PCI */
315 #define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
316 #define CFG_PCI_TARGET_INIT
317 #define CFG_PCI_MASTER_INIT
319 #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
320 #define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
323 * For booting Linux, the board info and command line data
324 * have to be in the first 8 MB of memory, since this is
325 * the maximum mapped by the Linux kernel during initialization.
327 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
329 /*-----------------------------------------------------------------------
330 * External Bus Controller (EBC) Setup
331 *----------------------------------------------------------------------*/
332 #define CFG_FLASH CFG_FLASH_BASE
333 #define CFG_CPLD 0x80000000
335 /* Memory Bank 0 (NOR-FLASH) initialization */
336 #define CFG_EBC_PB0AP 0x03017300
337 #define CFG_EBC_PB0CR (CFG_FLASH | 0xda000)
339 /* Memory Bank 2 (CPLD) initialization */
340 #define CFG_EBC_PB2AP 0x04814500
341 #define CFG_EBC_PB2CR (CFG_CPLD | 0x18000)
343 /*-----------------------------------------------------------------------
344 * Cache Configuration
346 #define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
347 #define CFG_CACHELINE_SIZE 32 /* ... */
348 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
349 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
353 * Internal Definitions
357 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
358 #define BOOTFLAG_WARM 0x02 /* Software reboot */
360 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
361 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
362 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
365 #endif /* __CONFIG_H */