include/configs/zynq_cse.h

   1 /*
   2  * (C) Copyright 2013 - 2017 Xilinx.
   3  *
   4  * Configuration settings for the Xilinx Zynq CSE board.
   5  * See zynq-common.h for Zynq common configs
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __CONFIG_ZYNQ_CSE_H
  11 #define __CONFIG_ZYNQ_CSE_H
  12
  13 #define CONFIG_SKIP_LOWLEVEL_INIT
  14 #define CONFIG_SYS_DCACHE_OFF
  15 #define CONFIG_SYS_ICACHE_OFF
  16
  17 #include <configs/zynq-common.h>
  18
  19 /* Undef unneeded configs */
  20 #undef CONFIG_EXTRA_ENV_SETTINGS
  21 #undef CONFIG_BOARD_LATE_INIT
  22 #undef CONFIG_ENV_SIZE
  23 #undef CONFIG_CMDLINE_EDITING
  24 #undef CONFIG_AUTO_COMPLETE
  25 #undef CONFIG_ZLIB
  26 #undef CONFIG_GZIP
  27
  28 #undef CONFIG_SYS_LONGHELP
  29
  30 #undef CONFIG_SYS_CBSIZE
  31 #undef CONFIG_BOOTM_VXWORKS
  32 #undef CONFIG_BOOTM_LINUX
  33
  34 #define CONFIG_SYS_CBSIZE       1024
  35
  36 #define CONFIG_ENV_SIZE         400
  37 #undef CONFIG_SYS_INIT_RAM_ADDR
  38 #undef CONFIG_SYS_INIT_RAM_SIZE
  39 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFFDE000
  40 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000
  41 #undef CONFIG_SPL_BSS_START_ADDR
  42 #undef CONFIG_SPL_BSS_MAX_SIZE
  43 #define CONFIG_SPL_BSS_START_ADDR       0x20000
  44 #define CONFIG_SPL_BSS_MAX_SIZE         0x8000
  45
  46 #undef CONFIG_SYS_MALLOC_LEN
  47 #define CONFIG_SYS_MALLOC_LEN   0x1000
  48
  49 #define CONFIG_SYS_SDRAM_BASE   0xfffc0000
  50 #define CONFIG_SYS_SDRAM_SIZE   0x40000
  51
  52 #endif /* __CONFIG_ZYNQ_CSE_H */