2 * Copyright © 2008 Keith Packard
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
23 #ifndef _DRM_DP_HELPER_H_
24 #define _DRM_DP_HELPER_H_
26 #include <linux/delay.h>
27 #include <linux/i2c.h>
29 #include <drm/display/drm_dp.h>
30 #include <drm/drm_connector.h>
36 bool drm_dp_channel_eq_ok(const u8 link_status
[DP_LINK_STATUS_SIZE
],
38 bool drm_dp_clock_recovery_ok(const u8 link_status
[DP_LINK_STATUS_SIZE
],
40 u8
drm_dp_get_adjust_request_voltage(const u8 link_status
[DP_LINK_STATUS_SIZE
],
42 u8
drm_dp_get_adjust_request_pre_emphasis(const u8 link_status
[DP_LINK_STATUS_SIZE
],
44 u8
drm_dp_get_adjust_tx_ffe_preset(const u8 link_status
[DP_LINK_STATUS_SIZE
],
47 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux
*aux
, const u8 dpcd
[DP_RECEIVER_CAP_SIZE
],
48 enum drm_dp_phy dp_phy
, bool uhbr
);
49 int drm_dp_read_channel_eq_delay(struct drm_dp_aux
*aux
, const u8 dpcd
[DP_RECEIVER_CAP_SIZE
],
50 enum drm_dp_phy dp_phy
, bool uhbr
);
52 void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux
*aux
,
53 const u8 dpcd
[DP_RECEIVER_CAP_SIZE
]);
54 void drm_dp_lttpr_link_train_clock_recovery_delay(void);
55 void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux
*aux
,
56 const u8 dpcd
[DP_RECEIVER_CAP_SIZE
]);
57 void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux
*aux
,
58 const u8 caps
[DP_LTTPR_PHY_CAP_SIZE
]);
60 int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux
*aux
);
61 bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status
[DP_LINK_STATUS_SIZE
],
63 bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status
[DP_LINK_STATUS_SIZE
],
65 bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status
[DP_LINK_STATUS_SIZE
]);
66 bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status
[DP_LINK_STATUS_SIZE
]);
67 bool drm_dp_128b132b_link_training_failed(const u8 link_status
[DP_LINK_STATUS_SIZE
]);
69 u8
drm_dp_link_rate_to_bw_code(int link_rate
);
70 int drm_dp_bw_code_to_link_rate(u8 link_bw
);
72 const char *drm_dp_phy_name(enum drm_dp_phy dp_phy
);
75 * struct drm_dp_vsc_sdp - drm DP VSC SDP
77 * This structure represents a DP VSC SDP of drm
78 * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and
79 * [Table 2-117: VSC SDP Payload for DB16 through DB18]
81 * @sdp_type: secondary-data packet type
82 * @revision: revision number
83 * @length: number of valid data bytes
84 * @pixelformat: pixel encoding format
85 * @colorimetry: colorimetry format
87 * @dynamic_range: dynamic range information
88 * @content_type: CTA-861-G defines content types and expected processing by a sink device
90 struct drm_dp_vsc_sdp
{
91 unsigned char sdp_type
;
92 unsigned char revision
;
94 enum dp_pixelformat pixelformat
;
95 enum dp_colorimetry colorimetry
;
97 enum dp_dynamic_range dynamic_range
;
98 enum dp_content_type content_type
;
101 void drm_dp_vsc_sdp_log(struct drm_printer
*p
, const struct drm_dp_vsc_sdp
*vsc
);
103 int drm_dp_psr_setup_time(const u8 psr_cap
[EDP_PSR_RECEIVER_CAP_SIZE
]);
106 drm_dp_max_link_rate(const u8 dpcd
[DP_RECEIVER_CAP_SIZE
])
108 return drm_dp_bw_code_to_link_rate(dpcd
[DP_MAX_LINK_RATE
]);
112 drm_dp_max_lane_count(const u8 dpcd
[DP_RECEIVER_CAP_SIZE
])
114 return dpcd
[DP_MAX_LANE_COUNT
] & DP_MAX_LANE_COUNT_MASK
;
118 drm_dp_enhanced_frame_cap(const u8 dpcd
[DP_RECEIVER_CAP_SIZE
])
120 return dpcd
[DP_DPCD_REV
] >= 0x11 &&
121 (dpcd
[DP_MAX_LANE_COUNT
] & DP_ENHANCED_FRAME_CAP
);
125 drm_dp_fast_training_cap(const u8 dpcd
[DP_RECEIVER_CAP_SIZE
])
127 return dpcd
[DP_DPCD_REV
] >= 0x11 &&
128 (dpcd
[DP_MAX_DOWNSPREAD
] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING
);
132 drm_dp_tps3_supported(const u8 dpcd
[DP_RECEIVER_CAP_SIZE
])
134 return dpcd
[DP_DPCD_REV
] >= 0x12 &&
135 dpcd
[DP_MAX_LANE_COUNT
] & DP_TPS3_SUPPORTED
;
139 drm_dp_max_downspread(const u8 dpcd
[DP_RECEIVER_CAP_SIZE
])
141 return dpcd
[DP_DPCD_REV
] >= 0x11 ||
142 dpcd
[DP_MAX_DOWNSPREAD
] & DP_MAX_DOWNSPREAD_0_5
;
146 drm_dp_tps4_supported(const u8 dpcd
[DP_RECEIVER_CAP_SIZE
])
148 return dpcd
[DP_DPCD_REV
] >= 0x14 &&
149 dpcd
[DP_MAX_DOWNSPREAD
] & DP_TPS4_SUPPORTED
;
153 drm_dp_training_pattern_mask(const u8 dpcd
[DP_RECEIVER_CAP_SIZE
])
155 return (dpcd
[DP_DPCD_REV
] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4
:
156 DP_TRAINING_PATTERN_MASK
;
160 drm_dp_is_branch(const u8 dpcd
[DP_RECEIVER_CAP_SIZE
])
162 return dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
;
165 /* DP/eDP DSC support */
166 u8
drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd
[DP_DSC_RECEIVER_CAP_SIZE
]);
167 u8
drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd
[DP_DSC_RECEIVER_CAP_SIZE
],
169 u8
drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd
[DP_DSC_RECEIVER_CAP_SIZE
]);
170 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc
[DP_DSC_RECEIVER_CAP_SIZE
],
174 drm_dp_sink_supports_dsc(const u8 dsc_dpcd
[DP_DSC_RECEIVER_CAP_SIZE
])
176 return dsc_dpcd
[DP_DSC_SUPPORT
- DP_DSC_SUPPORT
] &
177 DP_DSC_DECOMPRESSION_IS_SUPPORTED
;
181 drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd
[DP_DSC_RECEIVER_CAP_SIZE
])
183 return dsc_dpcd
[DP_DSC_MAX_BITS_PER_PIXEL_LOW
- DP_DSC_SUPPORT
] |
184 ((dsc_dpcd
[DP_DSC_MAX_BITS_PER_PIXEL_HI
- DP_DSC_SUPPORT
] &
185 DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK
) << 8);
189 drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd
[DP_DSC_RECEIVER_CAP_SIZE
])
191 /* Max Slicewidth = Number of Pixels * 320 */
192 return dsc_dpcd
[DP_DSC_MAX_SLICE_WIDTH
- DP_DSC_SUPPORT
] *
193 DP_DSC_SLICE_WIDTH_MULTIPLIER
;
197 * drm_dp_dsc_sink_supports_format() - check if sink supports DSC with given output format
198 * @dsc_dpcd : DSC-capability DPCDs of the sink
199 * @output_format: output_format which is to be checked
201 * Returns true if the sink supports DSC with the given output_format, false otherwise.
204 drm_dp_dsc_sink_supports_format(const u8 dsc_dpcd
[DP_DSC_RECEIVER_CAP_SIZE
], u8 output_format
)
206 return dsc_dpcd
[DP_DSC_DEC_COLOR_FORMAT_CAP
- DP_DSC_SUPPORT
] & output_format
;
209 /* Forward Error Correction Support on DP 1.4 */
211 drm_dp_sink_supports_fec(const u8 fec_capable
)
213 return fec_capable
& DP_FEC_CAPABLE
;
217 drm_dp_channel_coding_supported(const u8 dpcd
[DP_RECEIVER_CAP_SIZE
])
219 return dpcd
[DP_MAIN_LINK_CHANNEL_CODING
] & DP_CAP_ANSI_8B10B
;
223 drm_dp_alternate_scrambler_reset_cap(const u8 dpcd
[DP_RECEIVER_CAP_SIZE
])
225 return dpcd
[DP_EDP_CONFIGURATION_CAP
] &
226 DP_ALTERNATE_SCRAMBLER_RESET_CAP
;
229 /* Ignore MSA timing for Adaptive Sync support on DP 1.4 */
231 drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd
[DP_RECEIVER_CAP_SIZE
])
233 return dpcd
[DP_DOWN_STREAM_PORT_COUNT
] &
234 DP_MSA_TIMING_PAR_IGNORED
;
238 * drm_edp_backlight_supported() - Check an eDP DPCD for VESA backlight support
239 * @edp_dpcd: The DPCD to check
241 * Note that currently this function will return %false for panels which support various DPCD
242 * backlight features but which require the brightness be set through PWM, and don't support setting
243 * the brightness level via the DPCD.
245 * Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false
249 drm_edp_backlight_supported(const u8 edp_dpcd
[EDP_DISPLAY_CTL_CAP_SIZE
])
251 return !!(edp_dpcd
[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP
);
255 * drm_dp_is_uhbr_rate - Determine if a link rate is UHBR
256 * @link_rate: link rate in 10kbits/s units
258 * Determine if the provided link rate is an UHBR rate.
260 * Returns: %True if @link_rate is an UHBR rate.
262 static inline bool drm_dp_is_uhbr_rate(int link_rate
)
264 return link_rate
>= 1000000;
268 * DisplayPort AUX channel
272 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction
273 * @address: address of the (first) register to access
274 * @request: contains the type of transaction (see DP_AUX_* macros)
275 * @reply: upon completion, contains the reply type of the transaction
276 * @buffer: pointer to a transmission or reception buffer
277 * @size: size of @buffer
279 struct drm_dp_aux_msg
{
280 unsigned int address
;
288 struct drm_connector
;
292 * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX
293 * @lock: mutex protecting this struct
294 * @adap: the CEC adapter for CEC-Tunneling-over-AUX support.
295 * @connector: the connector this CEC adapter is associated with
296 * @unregister_work: unregister the CEC adapter
298 struct drm_dp_aux_cec
{
300 struct cec_adapter
*adap
;
301 struct drm_connector
*connector
;
302 struct delayed_work unregister_work
;
306 * struct drm_dp_aux - DisplayPort AUX channel
308 * An AUX channel can also be used to transport I2C messages to a sink. A
309 * typical application of that is to access an EDID that's present in the sink
310 * device. The @transfer() function can also be used to execute such
311 * transactions. The drm_dp_aux_register() function registers an I2C adapter
312 * that can be passed to drm_probe_ddc(). Upon removal, drivers should call
313 * drm_dp_aux_unregister() to remove the I2C adapter. The I2C adapter uses long
314 * transfers by default; if a partial response is received, the adapter will
315 * drop down to the size given by the partial response for this transaction
320 * @name: user-visible name of this AUX channel and the
321 * I2C-over-AUX adapter.
323 * It's also used to specify the name of the I2C adapter. If set
324 * to %NULL, dev_name() of @dev will be used.
329 * @ddc: I2C adapter that can be used for I2C-over-AUX
332 struct i2c_adapter ddc
;
335 * @dev: pointer to struct device that is the parent for this
341 * @drm_dev: pointer to the &drm_device that owns this AUX channel.
342 * Beware, this may be %NULL before drm_dp_aux_register() has been
345 * It should be set to the &drm_device that will be using this AUX
346 * channel as early as possible. For many graphics drivers this should
347 * happen before drm_dp_aux_init(), however it's perfectly fine to set
348 * this field later so long as it's assigned before calling
349 * drm_dp_aux_register().
351 struct drm_device
*drm_dev
;
354 * @crtc: backpointer to the crtc that is currently using this
357 struct drm_crtc
*crtc
;
360 * @hw_mutex: internal mutex used for locking transfers.
362 * Note that if the underlying hardware is shared among multiple
363 * channels, the driver needs to do additional locking to
364 * prevent concurrent access.
366 struct mutex hw_mutex
;
369 * @crc_work: worker that captures CRCs for each frame
371 struct work_struct crc_work
;
374 * @crc_count: counter of captured frame CRCs
379 * @transfer: transfers a message representing a single AUX
382 * This is a hardware-specific implementation of how
383 * transactions are executed that the drivers must provide.
385 * A pointer to a &drm_dp_aux_msg structure describing the
386 * transaction is passed into this function. Upon success, the
387 * implementation should return the number of payload bytes that
388 * were transferred, or a negative error-code on failure.
390 * Helpers will propagate these errors, with the exception of
391 * the %-EBUSY error, which causes a transaction to be retried.
392 * On a short, helpers will return %-EPROTO to make it simpler
393 * to check for failure.
395 * The @transfer() function must only modify the reply field of
396 * the &drm_dp_aux_msg structure. The retry logic and i2c
397 * helpers assume this is the case.
399 * Also note that this callback can be called no matter the
400 * state @dev is in and also no matter what state the panel is
403 * - If the @dev providing the AUX bus is currently unpowered then
404 * it will power itself up for the transfer.
406 * - If we're on eDP (using a drm_panel) and the panel is not in a
407 * state where it can respond (it's not powered or it's in a
408 * low power state) then this function may return an error, but
409 * not crash. It's up to the caller of this code to make sure that
410 * the panel is powered on if getting an error back is not OK. If a
411 * drm_panel driver is initiating a DP AUX transfer it may power
412 * itself up however it wants. All other code should ensure that
413 * the pre_enable() bridge chain (which eventually calls the
414 * drm_panel prepare function) has powered the panel.
416 ssize_t (*transfer
)(struct drm_dp_aux
*aux
,
417 struct drm_dp_aux_msg
*msg
);
420 * @wait_hpd_asserted: wait for HPD to be asserted
422 * This is mainly useful for eDP panels drivers to wait for an eDP
423 * panel to finish powering on. This is an optional function.
425 * This function will efficiently wait for the HPD signal to be
426 * asserted. The `wait_us` parameter that is passed in says that we
427 * know that the HPD signal is expected to be asserted within `wait_us`
428 * microseconds. This function could wait for longer than `wait_us` if
429 * the logic in the DP controller has a long debouncing time. The
430 * important thing is that if this function returns success that the
431 * DP controller is ready to send AUX transactions.
433 * This function returns 0 if HPD was asserted or -ETIMEDOUT if time
434 * expired and HPD wasn't asserted. This function should not print
435 * timeout errors to the log.
437 * The semantics of this function are designed to match the
438 * readx_poll_timeout() function. That means a `wait_us` of 0 means
439 * to wait forever. Like readx_poll_timeout(), this function may sleep.
441 * NOTE: this function specifically reports the state of the HPD pin
442 * that's associated with the DP AUX channel. This is different from
443 * the HPD concept in much of the rest of DRM which is more about
444 * physical presence of a display. For eDP, for instance, a display is
445 * assumed always present even if the HPD pin is deasserted.
447 int (*wait_hpd_asserted
)(struct drm_dp_aux
*aux
, unsigned long wait_us
);
450 * @i2c_nack_count: Counts I2C NACKs, used for DP validation.
452 unsigned i2c_nack_count
;
454 * @i2c_defer_count: Counts I2C DEFERs, used for DP validation.
456 unsigned i2c_defer_count
;
458 * @cec: struct containing fields used for CEC-Tunneling-over-AUX.
460 struct drm_dp_aux_cec cec
;
462 * @is_remote: Is this AUX CH actually using sideband messaging.
467 int drm_dp_dpcd_probe(struct drm_dp_aux
*aux
, unsigned int offset
);
468 ssize_t
drm_dp_dpcd_read(struct drm_dp_aux
*aux
, unsigned int offset
,
469 void *buffer
, size_t size
);
470 ssize_t
drm_dp_dpcd_write(struct drm_dp_aux
*aux
, unsigned int offset
,
471 void *buffer
, size_t size
);
474 * drm_dp_dpcd_readb() - read a single byte from the DPCD
475 * @aux: DisplayPort AUX channel
476 * @offset: address of the register to read
477 * @valuep: location where the value of the register will be stored
479 * Returns the number of bytes transferred (1) on success, or a negative
480 * error code on failure.
482 static inline ssize_t
drm_dp_dpcd_readb(struct drm_dp_aux
*aux
,
483 unsigned int offset
, u8
*valuep
)
485 return drm_dp_dpcd_read(aux
, offset
, valuep
, 1);
489 * drm_dp_dpcd_writeb() - write a single byte to the DPCD
490 * @aux: DisplayPort AUX channel
491 * @offset: address of the register to write
492 * @value: value to write to the register
494 * Returns the number of bytes transferred (1) on success, or a negative
495 * error code on failure.
497 static inline ssize_t
drm_dp_dpcd_writeb(struct drm_dp_aux
*aux
,
498 unsigned int offset
, u8 value
)
500 return drm_dp_dpcd_write(aux
, offset
, &value
, 1);
503 int drm_dp_read_dpcd_caps(struct drm_dp_aux
*aux
,
504 u8 dpcd
[DP_RECEIVER_CAP_SIZE
]);
506 int drm_dp_dpcd_read_link_status(struct drm_dp_aux
*aux
,
507 u8 status
[DP_LINK_STATUS_SIZE
]);
509 int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux
*aux
,
510 enum drm_dp_phy dp_phy
,
511 u8 link_status
[DP_LINK_STATUS_SIZE
]);
513 bool drm_dp_send_real_edid_checksum(struct drm_dp_aux
*aux
,
514 u8 real_edid_checksum
);
516 int drm_dp_read_downstream_info(struct drm_dp_aux
*aux
,
517 const u8 dpcd
[DP_RECEIVER_CAP_SIZE
],
518 u8 downstream_ports
[DP_MAX_DOWNSTREAM_PORTS
]);
519 bool drm_dp_downstream_is_type(const u8 dpcd
[DP_RECEIVER_CAP_SIZE
],
520 const u8 port_cap
[4], u8 type
);
521 bool drm_dp_downstream_is_tmds(const u8 dpcd
[DP_RECEIVER_CAP_SIZE
],
522 const u8 port_cap
[4],
523 const struct drm_edid
*drm_edid
);
524 int drm_dp_downstream_max_dotclock(const u8 dpcd
[DP_RECEIVER_CAP_SIZE
],
525 const u8 port_cap
[4]);
526 int drm_dp_downstream_max_tmds_clock(const u8 dpcd
[DP_RECEIVER_CAP_SIZE
],
527 const u8 port_cap
[4],
528 const struct drm_edid
*drm_edid
);
529 int drm_dp_downstream_min_tmds_clock(const u8 dpcd
[DP_RECEIVER_CAP_SIZE
],
530 const u8 port_cap
[4],
531 const struct drm_edid
*drm_edid
);
532 int drm_dp_downstream_max_bpc(const u8 dpcd
[DP_RECEIVER_CAP_SIZE
],
533 const u8 port_cap
[4],
534 const struct drm_edid
*drm_edid
);
535 bool drm_dp_downstream_420_passthrough(const u8 dpcd
[DP_RECEIVER_CAP_SIZE
],
536 const u8 port_cap
[4]);
537 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd
[DP_RECEIVER_CAP_SIZE
],
538 const u8 port_cap
[4]);
539 struct drm_display_mode
*drm_dp_downstream_mode(struct drm_device
*dev
,
540 const u8 dpcd
[DP_RECEIVER_CAP_SIZE
],
541 const u8 port_cap
[4]);
542 int drm_dp_downstream_id(struct drm_dp_aux
*aux
, char id
[6]);
543 void drm_dp_downstream_debug(struct seq_file
*m
,
544 const u8 dpcd
[DP_RECEIVER_CAP_SIZE
],
545 const u8 port_cap
[4],
546 const struct drm_edid
*drm_edid
,
547 struct drm_dp_aux
*aux
);
548 enum drm_mode_subconnector
549 drm_dp_subconnector_type(const u8 dpcd
[DP_RECEIVER_CAP_SIZE
],
550 const u8 port_cap
[4]);
551 void drm_dp_set_subconnector_property(struct drm_connector
*connector
,
552 enum drm_connector_status status
,
554 const u8 port_cap
[4]);
557 bool drm_dp_read_sink_count_cap(struct drm_connector
*connector
,
558 const u8 dpcd
[DP_RECEIVER_CAP_SIZE
],
559 const struct drm_dp_desc
*desc
);
560 int drm_dp_read_sink_count(struct drm_dp_aux
*aux
);
562 int drm_dp_read_lttpr_common_caps(struct drm_dp_aux
*aux
,
563 const u8 dpcd
[DP_RECEIVER_CAP_SIZE
],
564 u8 caps
[DP_LTTPR_COMMON_CAP_SIZE
]);
565 int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux
*aux
,
566 const u8 dpcd
[DP_RECEIVER_CAP_SIZE
],
567 enum drm_dp_phy dp_phy
,
568 u8 caps
[DP_LTTPR_PHY_CAP_SIZE
]);
569 int drm_dp_lttpr_count(const u8 cap
[DP_LTTPR_COMMON_CAP_SIZE
]);
570 int drm_dp_lttpr_max_link_rate(const u8 caps
[DP_LTTPR_COMMON_CAP_SIZE
]);
571 int drm_dp_lttpr_max_lane_count(const u8 caps
[DP_LTTPR_COMMON_CAP_SIZE
]);
572 bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps
[DP_LTTPR_PHY_CAP_SIZE
]);
573 bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps
[DP_LTTPR_PHY_CAP_SIZE
]);
575 void drm_dp_remote_aux_init(struct drm_dp_aux
*aux
);
576 void drm_dp_aux_init(struct drm_dp_aux
*aux
);
577 int drm_dp_aux_register(struct drm_dp_aux
*aux
);
578 void drm_dp_aux_unregister(struct drm_dp_aux
*aux
);
580 int drm_dp_start_crc(struct drm_dp_aux
*aux
, struct drm_crtc
*crtc
);
581 int drm_dp_stop_crc(struct drm_dp_aux
*aux
);
583 struct drm_dp_dpcd_ident
{
592 * struct drm_dp_desc - DP branch/sink device descriptor
593 * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch).
594 * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks.
597 struct drm_dp_dpcd_ident ident
;
601 int drm_dp_read_desc(struct drm_dp_aux
*aux
, struct drm_dp_desc
*desc
,
605 * enum drm_dp_quirk - Display Port sink/branch device specific quirks
607 * Display Port sink and branch devices in the wild have a variety of bugs, try
608 * to collect them here. The quirks are shared, but it's up to the drivers to
609 * implement workarounds for them.
613 * @DP_DPCD_QUIRK_CONSTANT_N:
615 * The device requires main link attributes Mvid and Nvid to be limited
616 * to 16 bits. So will give a constant value (0x8000) for compatability.
618 DP_DPCD_QUIRK_CONSTANT_N
,
620 * @DP_DPCD_QUIRK_NO_PSR:
622 * The device does not support PSR even if reports that it supports or
623 * driver still need to implement proper handling for such device.
625 DP_DPCD_QUIRK_NO_PSR
,
627 * @DP_DPCD_QUIRK_NO_SINK_COUNT:
629 * The device does not set SINK_COUNT to a non-zero value.
630 * The driver should ignore SINK_COUNT during detection. Note that
631 * drm_dp_read_sink_count_cap() automatically checks for this quirk.
633 DP_DPCD_QUIRK_NO_SINK_COUNT
,
635 * @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD:
637 * The device supports MST DSC despite not supporting Virtual DPCD.
638 * The DSC caps can be read from the physical aux instead.
640 DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD
,
642 * @DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS:
644 * The device supports a link rate of 3.24 Gbps (multiplier 0xc) despite
645 * the DP_MAX_LINK_RATE register reporting a lower max multiplier.
647 DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS
,
649 * @DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC:
651 * The device applies HBLANK expansion for some modes, but this
652 * requires enabling DSC.
654 DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC
,
658 * drm_dp_has_quirk() - does the DP device have a specific quirk
659 * @desc: Device descriptor filled by drm_dp_read_desc()
660 * @quirk: Quirk to query for
662 * Return true if DP device identified by @desc has @quirk.
665 drm_dp_has_quirk(const struct drm_dp_desc
*desc
, enum drm_dp_quirk quirk
)
667 return desc
->quirks
& BIT(quirk
);
671 * struct drm_edp_backlight_info - Probed eDP backlight info struct
672 * @pwmgen_bit_count: The pwmgen bit count
673 * @pwm_freq_pre_divider: The PWM frequency pre-divider value being used for this backlight, if any
674 * @max: The maximum backlight level that may be set
675 * @lsb_reg_used: Do we also write values to the DP_EDP_BACKLIGHT_BRIGHTNESS_LSB register?
676 * @aux_enable: Does the panel support the AUX enable cap?
677 * @aux_set: Does the panel support setting the brightness through AUX?
679 * This structure contains various data about an eDP backlight, which can be populated by using
680 * drm_edp_backlight_init().
682 struct drm_edp_backlight_info
{
684 u8 pwm_freq_pre_divider
;
687 bool lsb_reg_used
: 1;
693 drm_edp_backlight_init(struct drm_dp_aux
*aux
, struct drm_edp_backlight_info
*bl
,
694 u16 driver_pwm_freq_hz
, const u8 edp_dpcd
[EDP_DISPLAY_CTL_CAP_SIZE
],
695 u16
*current_level
, u8
*current_mode
);
696 int drm_edp_backlight_set_level(struct drm_dp_aux
*aux
, const struct drm_edp_backlight_info
*bl
,
698 int drm_edp_backlight_enable(struct drm_dp_aux
*aux
, const struct drm_edp_backlight_info
*bl
,
700 int drm_edp_backlight_disable(struct drm_dp_aux
*aux
, const struct drm_edp_backlight_info
*bl
);
702 #if IS_ENABLED(CONFIG_DRM_KMS_HELPER) && (IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \
703 (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE)))
705 int drm_panel_dp_aux_backlight(struct drm_panel
*panel
, struct drm_dp_aux
*aux
);
709 static inline int drm_panel_dp_aux_backlight(struct drm_panel
*panel
,
710 struct drm_dp_aux
*aux
)
717 #ifdef CONFIG_DRM_DP_CEC
718 void drm_dp_cec_irq(struct drm_dp_aux
*aux
);
719 void drm_dp_cec_register_connector(struct drm_dp_aux
*aux
,
720 struct drm_connector
*connector
);
721 void drm_dp_cec_unregister_connector(struct drm_dp_aux
*aux
);
722 void drm_dp_cec_attach(struct drm_dp_aux
*aux
, u16 source_physical_address
);
723 void drm_dp_cec_set_edid(struct drm_dp_aux
*aux
, const struct edid
*edid
);
724 void drm_dp_cec_unset_edid(struct drm_dp_aux
*aux
);
726 static inline void drm_dp_cec_irq(struct drm_dp_aux
*aux
)
731 drm_dp_cec_register_connector(struct drm_dp_aux
*aux
,
732 struct drm_connector
*connector
)
736 static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux
*aux
)
740 static inline void drm_dp_cec_attach(struct drm_dp_aux
*aux
,
741 u16 source_physical_address
)
745 static inline void drm_dp_cec_set_edid(struct drm_dp_aux
*aux
,
746 const struct edid
*edid
)
750 static inline void drm_dp_cec_unset_edid(struct drm_dp_aux
*aux
)
757 * struct drm_dp_phy_test_params - DP Phy Compliance parameters
758 * @link_rate: Requested Link rate from DPCD 0x219
759 * @num_lanes: Number of lanes requested by sing through DPCD 0x220
760 * @phy_pattern: DP Phy test pattern from DPCD 0x248
761 * @hbr2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B
762 * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259
763 * @enhanced_frame_cap: flag for enhanced frame capability.
765 struct drm_dp_phy_test_params
{
771 bool enhanced_frame_cap
;
774 int drm_dp_get_phy_test_pattern(struct drm_dp_aux
*aux
,
775 struct drm_dp_phy_test_params
*data
);
776 int drm_dp_set_phy_test_pattern(struct drm_dp_aux
*aux
,
777 struct drm_dp_phy_test_params
*data
, u8 dp_rev
);
778 int drm_dp_get_pcon_max_frl_bw(const u8 dpcd
[DP_RECEIVER_CAP_SIZE
],
779 const u8 port_cap
[4]);
780 int drm_dp_pcon_frl_prepare(struct drm_dp_aux
*aux
, bool enable_frl_ready_hpd
);
781 bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux
*aux
);
782 int drm_dp_pcon_frl_configure_1(struct drm_dp_aux
*aux
, int max_frl_gbps
,
784 int drm_dp_pcon_frl_configure_2(struct drm_dp_aux
*aux
, int max_frl_mask
,
786 int drm_dp_pcon_reset_frl_config(struct drm_dp_aux
*aux
);
787 int drm_dp_pcon_frl_enable(struct drm_dp_aux
*aux
);
789 bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux
*aux
);
790 int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux
*aux
, u8
*frl_trained_mask
);
791 void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux
*aux
,
792 struct drm_connector
*connector
);
793 bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd
[DP_PCON_DSC_ENCODER_CAP_SIZE
]);
794 int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd
[DP_PCON_DSC_ENCODER_CAP_SIZE
]);
795 int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd
[DP_PCON_DSC_ENCODER_CAP_SIZE
]);
796 int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd
[DP_PCON_DSC_ENCODER_CAP_SIZE
]);
797 int drm_dp_pcon_pps_default(struct drm_dp_aux
*aux
);
798 int drm_dp_pcon_pps_override_buf(struct drm_dp_aux
*aux
, u8 pps_buf
[128]);
799 int drm_dp_pcon_pps_override_param(struct drm_dp_aux
*aux
, u8 pps_param
[6]);
800 bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd
[DP_RECEIVER_CAP_SIZE
],
801 const u8 port_cap
[4], u8 color_spc
);
802 int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux
*aux
, u8 color_spc
);
804 #define DRM_DP_BW_OVERHEAD_MST BIT(0)
805 #define DRM_DP_BW_OVERHEAD_UHBR BIT(1)
806 #define DRM_DP_BW_OVERHEAD_SSC_REF_CLK BIT(2)
807 #define DRM_DP_BW_OVERHEAD_FEC BIT(3)
808 #define DRM_DP_BW_OVERHEAD_DSC BIT(4)
810 int drm_dp_bw_overhead(int lane_count
, int hactive
,
812 int bpp_x16
, unsigned long flags
);
813 int drm_dp_bw_channel_coding_efficiency(bool is_uhbr
);
815 #endif /* _DRM_DP_HELPER_H_ */