include/dt-bindings/clock/intel,lgm-clk.h

   1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
   2 /*
   3  * Copyright (C) 2020 Intel Corporation.
   4  * Lei Chuanhua <Chuanhua.lei@intel.com>
   5  * Zhu Yixin <Yixin.zhu@intel.com>
   6  */
   7 #ifndef __INTEL_LGM_CLK_H
   8 #define __INTEL_LGM_CLK_H
   9
  10 /* PLL clocks */
  11 #define LGM_CLK_OSC             1
  12 #define LGM_CLK_PLLPP           2
  13 #define LGM_CLK_PLL2            3
  14 #define LGM_CLK_PLL0CZ          4
  15 #define LGM_CLK_PLL0B           5
  16 #define LGM_CLK_PLL1            6
  17 #define LGM_CLK_LJPLL3          7
  18 #define LGM_CLK_LJPLL4          8
  19 #define LGM_CLK_PLL0CM0         9
  20 #define LGM_CLK_PLL0CM1         10
  21
  22 /* clocks from PLLs */
  23
  24 /* ROPLL clocks */
  25 #define LGM_CLK_PP_HW           15
  26 #define LGM_CLK_PP_UC           16
  27 #define LGM_CLK_PP_FXD          17
  28 #define LGM_CLK_PP_TBM          18
  29
  30 /* PLL2 clocks */
  31 #define LGM_CLK_DDR             20
  32
  33 /* PLL0CZ */
  34 #define LGM_CLK_CM              25
  35 #define LGM_CLK_IC              26
  36 #define LGM_CLK_SDXC3           27
  37
  38 /* PLL0B */
  39 #define LGM_CLK_NGI             30
  40 #define LGM_CLK_NOC4            31
  41 #define LGM_CLK_SW              32
  42 #define LGM_CLK_QSPI            33
  43 #define LGM_CLK_CQEM            LGM_CLK_SW
  44 #define LGM_CLK_EMMC5           LGM_CLK_NOC4
  45
  46 /* PLL1 */
  47 #define LGM_CLK_CT              35
  48 #define LGM_CLK_DSP             36
  49 #define LGM_CLK_VIF             37
  50
  51 /* LJPLL3 */
  52 #define LGM_CLK_CML             40
  53 #define LGM_CLK_SERDES          41
  54 #define LGM_CLK_POOL            42
  55 #define LGM_CLK_PTP             43
  56
  57 /* LJPLL4 */
  58 #define LGM_CLK_PCIE            45
  59 #define LGM_CLK_SATA            LGM_CLK_PCIE
  60
  61 /* PLL0CM0 */
  62 #define LGM_CLK_CPU0            50
  63
  64 /* PLL0CM1 */
  65 #define LGM_CLK_CPU1            55
  66
  67 /* Miscellaneous clocks */
  68 #define LGM_CLK_EMMC4           60
  69 #define LGM_CLK_SDXC2           61
  70 #define LGM_CLK_EMMC            62
  71 #define LGM_CLK_SDXC            63
  72 #define LGM_CLK_SLIC            64
  73 #define LGM_CLK_DCL             65
  74 #define LGM_CLK_DOCSIS          66
  75 #define LGM_CLK_PCM             67
  76 #define LGM_CLK_DDR_PHY         68
  77 #define LGM_CLK_PONDEF          69
  78 #define LGM_CLK_PL25M           70
  79 #define LGM_CLK_PL10M           71
  80 #define LGM_CLK_PL1544K         72
  81 #define LGM_CLK_PL2048K         73
  82 #define LGM_CLK_PL8K            74
  83 #define LGM_CLK_PON_NTR         75
  84 #define LGM_CLK_SYNC0           76
  85 #define LGM_CLK_SYNC1           77
  86 #define LGM_CLK_PROGDIV         78
  87 #define LGM_CLK_OD0             79
  88 #define LGM_CLK_OD1             80
  89 #define LGM_CLK_CBPHY0          81
  90 #define LGM_CLK_CBPHY1          82
  91 #define LGM_CLK_CBPHY2          83
  92 #define LGM_CLK_CBPHY3          84
  93
  94 /* Gate clocks */
  95 /* Gate CLK0 */
  96 #define LGM_GCLK_C55            100
  97 #define LGM_GCLK_QSPI           101
  98 #define LGM_GCLK_EIP197         102
  99 #define LGM_GCLK_VAULT          103
 100 #define LGM_GCLK_TOE            104
 101 #define LGM_GCLK_SDXC           105
 102 #define LGM_GCLK_EMMC           106
 103 #define LGM_GCLK_SPI_DBG        107
 104 #define LGM_GCLK_DMA3           108
 105
 106 /* Gate CLK1 */
 107 #define LGM_GCLK_DMA0           120
 108 #define LGM_GCLK_LEDC0          121
 109 #define LGM_GCLK_LEDC1          122
 110 #define LGM_GCLK_I2S0           123
 111 #define LGM_GCLK_I2S1           124
 112 #define LGM_GCLK_EBU            125
 113 #define LGM_GCLK_PWM            126
 114 #define LGM_GCLK_I2C0           127
 115 #define LGM_GCLK_I2C1           128
 116 #define LGM_GCLK_I2C2           129
 117 #define LGM_GCLK_I2C3           130
 118 #define LGM_GCLK_SSC0           131
 119 #define LGM_GCLK_SSC1           132
 120 #define LGM_GCLK_SSC2           133
 121 #define LGM_GCLK_SSC3           134
 122 #define LGM_GCLK_GPTC0          135
 123 #define LGM_GCLK_GPTC1          136
 124 #define LGM_GCLK_GPTC2          137
 125 #define LGM_GCLK_GPTC3          138
 126 #define LGM_GCLK_ASC0           139
 127 #define LGM_GCLK_ASC1           140
 128 #define LGM_GCLK_ASC2           141
 129 #define LGM_GCLK_ASC3           142
 130 #define LGM_GCLK_PCM0           143
 131 #define LGM_GCLK_PCM1           144
 132 #define LGM_GCLK_PCM2           145
 133
 134 /* Gate CLK2 */
 135 #define LGM_GCLK_PCIE10         150
 136 #define LGM_GCLK_PCIE11         151
 137 #define LGM_GCLK_PCIE30         152
 138 #define LGM_GCLK_PCIE31         153
 139 #define LGM_GCLK_PCIE20         154
 140 #define LGM_GCLK_PCIE21         155
 141 #define LGM_GCLK_PCIE40         156
 142 #define LGM_GCLK_PCIE41         157
 143 #define LGM_GCLK_XPCS0          158
 144 #define LGM_GCLK_XPCS1          159
 145 #define LGM_GCLK_XPCS2          160
 146 #define LGM_GCLK_XPCS3          161
 147 #define LGM_GCLK_SATA0          162
 148 #define LGM_GCLK_SATA1          163
 149 #define LGM_GCLK_SATA2          164
 150 #define LGM_GCLK_SATA3          165
 151
 152 /* Gate CLK3 */
 153 #define LGM_GCLK_ARCEM4         170
 154 #define LGM_GCLK_IDMAR1         171
 155 #define LGM_GCLK_IDMAT0         172
 156 #define LGM_GCLK_IDMAT1         173
 157 #define LGM_GCLK_IDMAT2         174
 158 #define LGM_GCLK_PPV4           175
 159 #define LGM_GCLK_GSWIPO         176
 160 #define LGM_GCLK_CQEM           177
 161 #define LGM_GCLK_XPCS5          178
 162 #define LGM_GCLK_USB1           179
 163 #define LGM_GCLK_USB2           180
 164
 165 #endif /* __INTEL_LGM_CLK_H */