include/dt-bindings/clock/mediatek,mt8365-clk.h

   1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2  *
   3  * Copyright (c) 2022 MediaTek Inc.
   4  */
   5
   6 #ifndef _DT_BINDINGS_CLK_MT8365_H
   7 #define _DT_BINDINGS_CLK_MT8365_H
   8
   9 /* TOPCKGEN */
  10 #define CLK_TOP_CLK_NULL                0
  11 #define CLK_TOP_I2S0_BCK                1
  12 #define CLK_TOP_DSI0_LNTC_DSICK         2
  13 #define CLK_TOP_VPLL_DPIX               3
  14 #define CLK_TOP_LVDSTX_CLKDIG_CTS       4
  15 #define CLK_TOP_MFGPLL                  5
  16 #define CLK_TOP_SYSPLL_D2               6
  17 #define CLK_TOP_SYSPLL1_D2              7
  18 #define CLK_TOP_SYSPLL1_D4              8
  19 #define CLK_TOP_SYSPLL1_D8              9
  20 #define CLK_TOP_SYSPLL1_D16             10
  21 #define CLK_TOP_SYSPLL_D3               11
  22 #define CLK_TOP_SYSPLL2_D2              12
  23 #define CLK_TOP_SYSPLL2_D4              13
  24 #define CLK_TOP_SYSPLL2_D8              14
  25 #define CLK_TOP_SYSPLL_D5               15
  26 #define CLK_TOP_SYSPLL3_D2              16
  27 #define CLK_TOP_SYSPLL3_D4              17
  28 #define CLK_TOP_SYSPLL_D7               18
  29 #define CLK_TOP_SYSPLL4_D2              19
  30 #define CLK_TOP_SYSPLL4_D4              20
  31 #define CLK_TOP_UNIVPLL                 21
  32 #define CLK_TOP_UNIVPLL_D2              22
  33 #define CLK_TOP_UNIVPLL1_D2             23
  34 #define CLK_TOP_UNIVPLL1_D4             24
  35 #define CLK_TOP_UNIVPLL_D3              25
  36 #define CLK_TOP_UNIVPLL2_D2             26
  37 #define CLK_TOP_UNIVPLL2_D4             27
  38 #define CLK_TOP_UNIVPLL2_D8             28
  39 #define CLK_TOP_UNIVPLL2_D32            29
  40 #define CLK_TOP_UNIVPLL_D5              30
  41 #define CLK_TOP_UNIVPLL3_D2             31
  42 #define CLK_TOP_UNIVPLL3_D4             32
  43 #define CLK_TOP_MMPLL                   33
  44 #define CLK_TOP_MMPLL_D2                34
  45 #define CLK_TOP_LVDSPLL_D2              35
  46 #define CLK_TOP_LVDSPLL_D4              36
  47 #define CLK_TOP_LVDSPLL_D8              37
  48 #define CLK_TOP_LVDSPLL_D16             38
  49 #define CLK_TOP_USB20_192M              39
  50 #define CLK_TOP_USB20_192M_D4           40
  51 #define CLK_TOP_USB20_192M_D8           41
  52 #define CLK_TOP_USB20_192M_D16          42
  53 #define CLK_TOP_USB20_192M_D32          43
  54 #define CLK_TOP_APLL1                   44
  55 #define CLK_TOP_APLL1_D2                45
  56 #define CLK_TOP_APLL1_D4                46
  57 #define CLK_TOP_APLL1_D8                47
  58 #define CLK_TOP_APLL2                   48
  59 #define CLK_TOP_APLL2_D2                49
  60 #define CLK_TOP_APLL2_D4                50
  61 #define CLK_TOP_APLL2_D8                51
  62 #define CLK_TOP_SYS_26M_D2              52
  63 #define CLK_TOP_MSDCPLL                 53
  64 #define CLK_TOP_MSDCPLL_D2              54
  65 #define CLK_TOP_DSPPLL                  55
  66 #define CLK_TOP_DSPPLL_D2               56
  67 #define CLK_TOP_DSPPLL_D4               57
  68 #define CLK_TOP_DSPPLL_D8               58
  69 #define CLK_TOP_APUPLL                  59
  70 #define CLK_TOP_CLK26M_D52              60
  71 #define CLK_TOP_AXI_SEL                 61
  72 #define CLK_TOP_MEM_SEL                 62
  73 #define CLK_TOP_MM_SEL                  63
  74 #define CLK_TOP_SCP_SEL                 64
  75 #define CLK_TOP_MFG_SEL                 65
  76 #define CLK_TOP_ATB_SEL                 66
  77 #define CLK_TOP_CAMTG_SEL               67
  78 #define CLK_TOP_CAMTG1_SEL              68
  79 #define CLK_TOP_UART_SEL                69
  80 #define CLK_TOP_SPI_SEL                 70
  81 #define CLK_TOP_MSDC50_0_HC_SEL         71
  82 #define CLK_TOP_MSDC2_2_HC_SEL          72
  83 #define CLK_TOP_MSDC50_0_SEL            73
  84 #define CLK_TOP_MSDC50_2_SEL            74
  85 #define CLK_TOP_MSDC30_1_SEL            75
  86 #define CLK_TOP_AUDIO_SEL               76
  87 #define CLK_TOP_AUD_INTBUS_SEL          77
  88 #define CLK_TOP_AUD_1_SEL               78
  89 #define CLK_TOP_AUD_2_SEL               79
  90 #define CLK_TOP_AUD_ENGEN1_SEL          80
  91 #define CLK_TOP_AUD_ENGEN2_SEL          81
  92 #define CLK_TOP_AUD_SPDIF_SEL           82
  93 #define CLK_TOP_DISP_PWM_SEL            83
  94 #define CLK_TOP_DXCC_SEL                84
  95 #define CLK_TOP_SSUSB_SYS_SEL           85
  96 #define CLK_TOP_SSUSB_XHCI_SEL          86
  97 #define CLK_TOP_SPM_SEL                 87
  98 #define CLK_TOP_I2C_SEL                 88
  99 #define CLK_TOP_PWM_SEL                 89
 100 #define CLK_TOP_SENIF_SEL               90
 101 #define CLK_TOP_AES_FDE_SEL             91
 102 #define CLK_TOP_CAMTM_SEL               92
 103 #define CLK_TOP_DPI0_SEL                93
 104 #define CLK_TOP_DPI1_SEL                94
 105 #define CLK_TOP_DSP_SEL                 95
 106 #define CLK_TOP_NFI2X_SEL               96
 107 #define CLK_TOP_NFIECC_SEL              97
 108 #define CLK_TOP_ECC_SEL                 98
 109 #define CLK_TOP_ETH_SEL                 99
 110 #define CLK_TOP_GCPU_SEL                100
 111 #define CLK_TOP_GCPU_CPM_SEL            101
 112 #define CLK_TOP_APU_SEL                 102
 113 #define CLK_TOP_APU_IF_SEL              103
 114 #define CLK_TOP_MBIST_DIAG_SEL          104
 115 #define CLK_TOP_APLL_I2S0_SEL           105
 116 #define CLK_TOP_APLL_I2S1_SEL           106
 117 #define CLK_TOP_APLL_I2S2_SEL           107
 118 #define CLK_TOP_APLL_I2S3_SEL           108
 119 #define CLK_TOP_APLL_TDMOUT_SEL         109
 120 #define CLK_TOP_APLL_TDMIN_SEL          110
 121 #define CLK_TOP_APLL_SPDIF_SEL          111
 122 #define CLK_TOP_APLL12_CK_DIV0          112
 123 #define CLK_TOP_APLL12_CK_DIV1          113
 124 #define CLK_TOP_APLL12_CK_DIV2          114
 125 #define CLK_TOP_APLL12_CK_DIV3          115
 126 #define CLK_TOP_APLL12_CK_DIV4          116
 127 #define CLK_TOP_APLL12_CK_DIV4B         117
 128 #define CLK_TOP_APLL12_CK_DIV5          118
 129 #define CLK_TOP_APLL12_CK_DIV5B         119
 130 #define CLK_TOP_APLL12_CK_DIV6          120
 131 #define CLK_TOP_AUD_I2S0_M              121
 132 #define CLK_TOP_AUD_I2S1_M              122
 133 #define CLK_TOP_AUD_I2S2_M              123
 134 #define CLK_TOP_AUD_I2S3_M              124
 135 #define CLK_TOP_AUD_TDMOUT_M            125
 136 #define CLK_TOP_AUD_TDMOUT_B            126
 137 #define CLK_TOP_AUD_TDMIN_M             127
 138 #define CLK_TOP_AUD_TDMIN_B             128
 139 #define CLK_TOP_AUD_SPDIF_M             129
 140 #define CLK_TOP_USB20_48M_EN            130
 141 #define CLK_TOP_UNIVPLL_48M_EN          131
 142 #define CLK_TOP_LVDSTX_CLKDIG_EN        132
 143 #define CLK_TOP_VPLL_DPIX_EN            133
 144 #define CLK_TOP_SSUSB_TOP_CK_EN         134
 145 #define CLK_TOP_SSUSB_PHY_CK_EN         135
 146 #define CLK_TOP_CONN_32K                136
 147 #define CLK_TOP_CONN_26M                137
 148 #define CLK_TOP_DSP_32K                 138
 149 #define CLK_TOP_DSP_26M                 139
 150 #define CLK_TOP_NR_CLK                  140
 151
 152 /* INFRACFG */
 153 #define CLK_IFR_PMIC_TMR                0
 154 #define CLK_IFR_PMIC_AP                 1
 155 #define CLK_IFR_PMIC_MD                 2
 156 #define CLK_IFR_PMIC_CONN               3
 157 #define CLK_IFR_ICUSB                   4
 158 #define CLK_IFR_GCE                     5
 159 #define CLK_IFR_THERM                   6
 160 #define CLK_IFR_PWM_HCLK                7
 161 #define CLK_IFR_PWM1                    8
 162 #define CLK_IFR_PWM2                    9
 163 #define CLK_IFR_PWM3                    10
 164 #define CLK_IFR_PWM4                    11
 165 #define CLK_IFR_PWM5                    12
 166 #define CLK_IFR_PWM                     13
 167 #define CLK_IFR_UART0                   14
 168 #define CLK_IFR_UART1                   15
 169 #define CLK_IFR_UART2                   16
 170 #define CLK_IFR_DSP_UART                17
 171 #define CLK_IFR_GCE_26M                 18
 172 #define CLK_IFR_CQ_DMA_FPC              19
 173 #define CLK_IFR_BTIF                    20
 174 #define CLK_IFR_SPI0                    21
 175 #define CLK_IFR_MSDC0_HCLK              22
 176 #define CLK_IFR_MSDC2_HCLK              23
 177 #define CLK_IFR_MSDC1_HCLK              24
 178 #define CLK_IFR_DVFSRC                  25
 179 #define CLK_IFR_GCPU                    26
 180 #define CLK_IFR_TRNG                    27
 181 #define CLK_IFR_AUXADC                  28
 182 #define CLK_IFR_CPUM                    29
 183 #define CLK_IFR_AUXADC_MD               30
 184 #define CLK_IFR_AP_DMA                  31
 185 #define CLK_IFR_DEBUGSYS                32
 186 #define CLK_IFR_AUDIO                   33
 187 #define CLK_IFR_PWM_FBCLK6              34
 188 #define CLK_IFR_DISP_PWM                35
 189 #define CLK_IFR_AUD_26M_BK              36
 190 #define CLK_IFR_CQ_DMA                  37
 191 #define CLK_IFR_MSDC0_SF                38
 192 #define CLK_IFR_MSDC1_SF                39
 193 #define CLK_IFR_MSDC2_SF                40
 194 #define CLK_IFR_AP_MSDC0                41
 195 #define CLK_IFR_MD_MSDC0                42
 196 #define CLK_IFR_MSDC0_SRC               43
 197 #define CLK_IFR_MSDC1_SRC               44
 198 #define CLK_IFR_MSDC2_SRC               45
 199 #define CLK_IFR_PWRAP_TMR               46
 200 #define CLK_IFR_PWRAP_SPI               47
 201 #define CLK_IFR_PWRAP_SYS               48
 202 #define CLK_IFR_MCU_PM_BK               49
 203 #define CLK_IFR_IRRX_26M                50
 204 #define CLK_IFR_IRRX_32K                51
 205 #define CLK_IFR_I2C0_AXI                52
 206 #define CLK_IFR_I2C1_AXI                53
 207 #define CLK_IFR_I2C2_AXI                54
 208 #define CLK_IFR_I2C3_AXI                55
 209 #define CLK_IFR_NIC_AXI                 56
 210 #define CLK_IFR_NIC_SLV_AXI             57
 211 #define CLK_IFR_APU_AXI                 58
 212 #define CLK_IFR_NFIECC                  59
 213 #define CLK_IFR_NFIECC_BK               60
 214 #define CLK_IFR_NFI1X_BK                61
 215 #define CLK_IFR_NFI_BK                  62
 216 #define CLK_IFR_MSDC2_AP_BK             63
 217 #define CLK_IFR_MSDC2_MD_BK             64
 218 #define CLK_IFR_MSDC2_BK                65
 219 #define CLK_IFR_SUSB_133_BK             66
 220 #define CLK_IFR_SUSB_66_BK              67
 221 #define CLK_IFR_SSUSB_SYS               68
 222 #define CLK_IFR_SSUSB_REF               69
 223 #define CLK_IFR_SSUSB_XHCI              70
 224 #define CLK_IFR_NR_CLK                  71
 225
 226 /* PERICFG */
 227 #define CLK_PERIAXI                     0
 228 #define CLK_PERI_NR_CLK                 1
 229
 230 /* APMIXEDSYS */
 231 #define CLK_APMIXED_ARMPLL              0
 232 #define CLK_APMIXED_MAINPLL             1
 233 #define CLK_APMIXED_UNIVPLL             2
 234 #define CLK_APMIXED_MFGPLL              3
 235 #define CLK_APMIXED_MSDCPLL             4
 236 #define CLK_APMIXED_MMPLL               5
 237 #define CLK_APMIXED_APLL1               6
 238 #define CLK_APMIXED_APLL2               7
 239 #define CLK_APMIXED_LVDSPLL             8
 240 #define CLK_APMIXED_DSPPLL              9
 241 #define CLK_APMIXED_APUPLL              10
 242 #define CLK_APMIXED_UNIV_EN             11
 243 #define CLK_APMIXED_USB20_EN            12
 244 #define CLK_APMIXED_NR_CLK              13
 245
 246 /* GCE */
 247 #define CLK_GCE_FAXI                    0
 248 #define CLK_GCE_NR_CLK                  1
 249
 250 /* AUDIOTOP */
 251 #define CLK_AUD_AFE                     0
 252 #define CLK_AUD_I2S                     1
 253 #define CLK_AUD_22M                     2
 254 #define CLK_AUD_24M                     3
 255 #define CLK_AUD_INTDIR                  4
 256 #define CLK_AUD_APLL2_TUNER             5
 257 #define CLK_AUD_APLL_TUNER              6
 258 #define CLK_AUD_SPDF                    7
 259 #define CLK_AUD_HDMI                    8
 260 #define CLK_AUD_HDMI_IN                 9
 261 #define CLK_AUD_ADC                     10
 262 #define CLK_AUD_DAC                     11
 263 #define CLK_AUD_DAC_PREDIS              12
 264 #define CLK_AUD_TML                     13
 265 #define CLK_AUD_I2S1_BK                 14
 266 #define CLK_AUD_I2S2_BK                 15
 267 #define CLK_AUD_I2S3_BK                 16
 268 #define CLK_AUD_I2S4_BK                 17
 269 #define CLK_AUD_NR_CLK                  18
 270
 271 /* MIPI_CSI0A */
 272 #define CLK_MIPI0A_CSR_CSI_EN_0A        0
 273 #define CLK_MIPI_RX_ANA_CSI0A_NR_CLK    1
 274
 275 /* MIPI_CSI0B */
 276 #define CLK_MIPI0B_CSR_CSI_EN_0B        0
 277 #define CLK_MIPI_RX_ANA_CSI0B_NR_CLK    1
 278
 279 /* MIPI_CSI1A */
 280 #define CLK_MIPI1A_CSR_CSI_EN_1A        0
 281 #define CLK_MIPI_RX_ANA_CSI1A_NR_CLK    1
 282
 283 /* MIPI_CSI1B */
 284 #define CLK_MIPI1B_CSR_CSI_EN_1B        0
 285 #define CLK_MIPI_RX_ANA_CSI1B_NR_CLK    1
 286
 287 /* MIPI_CSI2A */
 288 #define CLK_MIPI2A_CSR_CSI_EN_2A        0
 289 #define CLK_MIPI_RX_ANA_CSI2A_NR_CLK    1
 290
 291 /* MIPI_CSI2B */
 292 #define CLK_MIPI2B_CSR_CSI_EN_2B        0
 293 #define CLK_MIPI_RX_ANA_CSI2B_NR_CLK    1
 294
 295 /* MCUCFG */
 296 #define CLK_MCU_BUS_SEL                 0
 297 #define CLK_MCU_NR_CLK                  1
 298
 299 /* MFGCFG */
 300 #define CLK_MFG_BG3D                    0
 301 #define CLK_MFG_MBIST_DIAG              1
 302 #define CLK_MFG_NR_CLK                  2
 303
 304 /* MMSYS */
 305 #define CLK_MM_MM_MDP_RDMA0             0
 306 #define CLK_MM_MM_MDP_CCORR0            1
 307 #define CLK_MM_MM_MDP_RSZ0              2
 308 #define CLK_MM_MM_MDP_RSZ1              3
 309 #define CLK_MM_MM_MDP_TDSHP0            4
 310 #define CLK_MM_MM_MDP_WROT0             5
 311 #define CLK_MM_MM_MDP_WDMA0             6
 312 #define CLK_MM_MM_DISP_OVL0             7
 313 #define CLK_MM_MM_DISP_OVL0_2L          8
 314 #define CLK_MM_MM_DISP_RSZ0             9
 315 #define CLK_MM_MM_DISP_RDMA0            10
 316 #define CLK_MM_MM_DISP_WDMA0            11
 317 #define CLK_MM_MM_DISP_COLOR0           12
 318 #define CLK_MM_MM_DISP_CCORR0           13
 319 #define CLK_MM_MM_DISP_AAL0             14
 320 #define CLK_MM_MM_DISP_GAMMA0           15
 321 #define CLK_MM_MM_DISP_DITHER0          16
 322 #define CLK_MM_MM_DSI0                  17
 323 #define CLK_MM_MM_DISP_RDMA1            18
 324 #define CLK_MM_MM_MDP_RDMA1             19
 325 #define CLK_MM_DPI0_DPI0                20
 326 #define CLK_MM_MM_FAKE                  21
 327 #define CLK_MM_MM_SMI_COMMON            22
 328 #define CLK_MM_MM_SMI_LARB0             23
 329 #define CLK_MM_MM_SMI_COMM0             24
 330 #define CLK_MM_MM_SMI_COMM1             25
 331 #define CLK_MM_MM_CAM_MDP               26
 332 #define CLK_MM_MM_SMI_IMG               27
 333 #define CLK_MM_MM_SMI_CAM               28
 334 #define CLK_MM_IMG_IMG_DL_RELAY         29
 335 #define CLK_MM_IMG_IMG_DL_ASYNC_TOP     30
 336 #define CLK_MM_DSI0_DIG_DSI             31
 337 #define CLK_MM_26M_HRTWT                32
 338 #define CLK_MM_MM_DPI0                  33
 339 #define CLK_MM_LVDSTX_PXL               34
 340 #define CLK_MM_LVDSTX_CTS               35
 341 #define CLK_MM_NR_CLK                   36
 342
 343 /* IMGSYS */
 344 #define CLK_CAM_LARB2                   0
 345 #define CLK_CAM                         1
 346 #define CLK_CAMTG                       2
 347 #define CLK_CAM_SENIF                   3
 348 #define CLK_CAMSV0                      4
 349 #define CLK_CAMSV1                      5
 350 #define CLK_CAM_FDVT                    6
 351 #define CLK_CAM_WPE                     7
 352 #define CLK_CAM_NR_CLK                  8
 353
 354 /* VDECSYS */
 355 #define CLK_VDEC_VDEC                   0
 356 #define CLK_VDEC_LARB1                  1
 357 #define CLK_VDEC_NR_CLK                 2
 358
 359 /* VENCSYS */
 360 #define CLK_VENC                        0
 361 #define CLK_VENC_JPGENC                 1
 362 #define CLK_VENC_NR_CLK                 2
 363
 364 /* APUSYS */
 365 #define CLK_APU_IPU_CK                  0
 366 #define CLK_APU_AXI                     1
 367 #define CLK_APU_JTAG                    2
 368 #define CLK_APU_IF_CK                   3
 369 #define CLK_APU_EDMA                    4
 370 #define CLK_APU_AHB                     5
 371 #define CLK_APU_NR_CLK                  6
 372
 373 #endif /* _DT_BINDINGS_CLK_MT8365_H */