include/dt-bindings/clock/qcom,sm4450-gcc.h

   1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
   2 /*
   3  * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
   4  */
   5
   6 #ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM4450_H
   7 #define _DT_BINDINGS_CLK_QCOM_GCC_SM4450_H
   8
   9 /* GCC clocks */
  10 #define GCC_AGGRE_NOC_PCIE_0_AXI_CLK                            0
  11 #define GCC_AGGRE_UFS_PHY_AXI_CLK                               1
  12 #define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK                        2
  13 #define GCC_AGGRE_USB3_PRIM_AXI_CLK                             3
  14 #define GCC_BOOT_ROM_AHB_CLK                                    4
  15 #define GCC_CAMERA_AHB_CLK                                      5
  16 #define GCC_CAMERA_HF_AXI_CLK                                   6
  17 #define GCC_CAMERA_SF_AXI_CLK                                   7
  18 #define GCC_CAMERA_SLEEP_CLK                                    8
  19 #define GCC_CAMERA_XO_CLK                                       9
  20 #define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK                           10
  21 #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK                           11
  22 #define GCC_DDRSS_GPU_AXI_CLK                                   12
  23 #define GCC_DDRSS_PCIE_SF_TBU_CLK                               13
  24 #define GCC_DISP_AHB_CLK                                        14
  25 #define GCC_DISP_HF_AXI_CLK                                     15
  26 #define GCC_DISP_XO_CLK                                         16
  27 #define GCC_EUSB3_0_CLKREF_EN                                   17
  28 #define GCC_GP1_CLK                                             18
  29 #define GCC_GP1_CLK_SRC                                         19
  30 #define GCC_GP2_CLK                                             20
  31 #define GCC_GP2_CLK_SRC                                         21
  32 #define GCC_GP3_CLK                                             22
  33 #define GCC_GP3_CLK_SRC                                         23
  34 #define GCC_GPLL0                                               24
  35 #define GCC_GPLL0_OUT_EVEN                                      25
  36 #define GCC_GPLL0_OUT_ODD                                       26
  37 #define GCC_GPLL1                                               27
  38 #define GCC_GPLL3                                               28
  39 #define GCC_GPLL4                                               29
  40 #define GCC_GPLL9                                               30
  41 #define GCC_GPLL10                                              31
  42 #define GCC_GPU_CFG_AHB_CLK                                     32
  43 #define GCC_GPU_GPLL0_CLK_SRC                                   33
  44 #define GCC_GPU_GPLL0_DIV_CLK_SRC                               34
  45 #define GCC_GPU_MEMNOC_GFX_CLK                                  35
  46 #define GCC_GPU_SNOC_DVM_GFX_CLK                                36
  47 #define GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK              37
  48 #define GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK               38
  49 #define GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK                   39
  50 #define GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK                   40
  51 #define GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_CLK                    41
  52 #define GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_CLK                    42
  53 #define GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_CLK                    43
  54 #define GCC_HLOS1_VOTE_MMU_TCU_CLK                              44
  55 #define GCC_PCIE_0_AUX_CLK                                      45
  56 #define GCC_PCIE_0_AUX_CLK_SRC                                  46
  57 #define GCC_PCIE_0_CFG_AHB_CLK                                  47
  58 #define GCC_PCIE_0_CLKREF_EN                                    48
  59 #define GCC_PCIE_0_MSTR_AXI_CLK                                 49
  60 #define GCC_PCIE_0_PHY_RCHNG_CLK                                50
  61 #define GCC_PCIE_0_PHY_RCHNG_CLK_SRC                            51
  62 #define GCC_PCIE_0_PIPE_CLK                                     52
  63 #define GCC_PCIE_0_PIPE_CLK_SRC                                 53
  64 #define GCC_PCIE_0_PIPE_DIV2_CLK                                54
  65 #define GCC_PCIE_0_PIPE_DIV2_CLK_SRC                            55
  66 #define GCC_PCIE_0_SLV_AXI_CLK                                  56
  67 #define GCC_PCIE_0_SLV_Q2A_AXI_CLK                              57
  68 #define GCC_PDM2_CLK                                            58
  69 #define GCC_PDM2_CLK_SRC                                        59
  70 #define GCC_PDM_AHB_CLK                                         60
  71 #define GCC_PDM_XO4_CLK                                         61
  72 #define GCC_QMIP_CAMERA_NRT_AHB_CLK                             62
  73 #define GCC_QMIP_CAMERA_RT_AHB_CLK                              63
  74 #define GCC_QMIP_DISP_AHB_CLK                                   64
  75 #define GCC_QMIP_GPU_AHB_CLK                                    65
  76 #define GCC_QMIP_PCIE_AHB_CLK                                   66
  77 #define GCC_QMIP_VIDEO_VCODEC_AHB_CLK                           67
  78 #define GCC_QUPV3_WRAP0_CORE_2X_CLK                             68
  79 #define GCC_QUPV3_WRAP0_CORE_CLK                                69
  80 #define GCC_QUPV3_WRAP0_S0_CLK                                  70
  81 #define GCC_QUPV3_WRAP0_S0_CLK_SRC                              71
  82 #define GCC_QUPV3_WRAP0_S1_CLK                                  72
  83 #define GCC_QUPV3_WRAP0_S1_CLK_SRC                              73
  84 #define GCC_QUPV3_WRAP0_S2_CLK                                  74
  85 #define GCC_QUPV3_WRAP0_S2_CLK_SRC                              75
  86 #define GCC_QUPV3_WRAP0_S3_CLK                                  76
  87 #define GCC_QUPV3_WRAP0_S3_CLK_SRC                              77
  88 #define GCC_QUPV3_WRAP0_S4_CLK                                  78
  89 #define GCC_QUPV3_WRAP0_S4_CLK_SRC                              79
  90 #define GCC_QUPV3_WRAP1_CORE_2X_CLK                             80
  91 #define GCC_QUPV3_WRAP1_CORE_CLK                                81
  92 #define GCC_QUPV3_WRAP1_S0_CLK                                  82
  93 #define GCC_QUPV3_WRAP1_S0_CLK_SRC                              83
  94 #define GCC_QUPV3_WRAP1_S1_CLK                                  84
  95 #define GCC_QUPV3_WRAP1_S1_CLK_SRC                              85
  96 #define GCC_QUPV3_WRAP1_S2_CLK                                  86
  97 #define GCC_QUPV3_WRAP1_S2_CLK_SRC                              87
  98 #define GCC_QUPV3_WRAP1_S3_CLK                                  88
  99 #define GCC_QUPV3_WRAP1_S3_CLK_SRC                              89
 100 #define GCC_QUPV3_WRAP1_S4_CLK                                  90
 101 #define GCC_QUPV3_WRAP1_S4_CLK_SRC                              91
 102 #define GCC_QUPV3_WRAP_0_M_AHB_CLK                              92
 103 #define GCC_QUPV3_WRAP_0_S_AHB_CLK                              93
 104 #define GCC_QUPV3_WRAP_1_M_AHB_CLK                              94
 105 #define GCC_QUPV3_WRAP_1_S_AHB_CLK                              95
 106 #define GCC_SDCC1_AHB_CLK                                       96
 107 #define GCC_SDCC1_APPS_CLK                                      97
 108 #define GCC_SDCC1_APPS_CLK_SRC                                  98
 109 #define GCC_SDCC1_ICE_CORE_CLK                                  99
 110 #define GCC_SDCC1_ICE_CORE_CLK_SRC                              100
 111 #define GCC_SDCC2_AHB_CLK                                       101
 112 #define GCC_SDCC2_APPS_CLK                                      102
 113 #define GCC_SDCC2_APPS_CLK_SRC                                  103
 114 #define GCC_UFS_0_CLKREF_EN                                     104
 115 #define GCC_UFS_PAD_CLKREF_EN                                   105
 116 #define GCC_UFS_PHY_AHB_CLK                                     106
 117 #define GCC_UFS_PHY_AXI_CLK                                     107
 118 #define GCC_UFS_PHY_AXI_CLK_SRC                                 108
 119 #define GCC_UFS_PHY_AXI_HW_CTL_CLK                              109
 120 #define GCC_UFS_PHY_ICE_CORE_CLK                                110
 121 #define GCC_UFS_PHY_ICE_CORE_CLK_SRC                            111
 122 #define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK                         112
 123 #define GCC_UFS_PHY_PHY_AUX_CLK                                 113
 124 #define GCC_UFS_PHY_PHY_AUX_CLK_SRC                             114
 125 #define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK                          115
 126 #define GCC_UFS_PHY_RX_SYMBOL_0_CLK                             116
 127 #define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC                         117
 128 #define GCC_UFS_PHY_RX_SYMBOL_1_CLK                             118
 129 #define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC                         119
 130 #define GCC_UFS_PHY_TX_SYMBOL_0_CLK                             120
 131 #define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC                         121
 132 #define GCC_UFS_PHY_UNIPRO_CORE_CLK                             122
 133 #define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC                         123
 134 #define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK                      124
 135 #define GCC_USB30_PRIM_MASTER_CLK                               125
 136 #define GCC_USB30_PRIM_MASTER_CLK_SRC                           126
 137 #define GCC_USB30_PRIM_MOCK_UTMI_CLK                            127
 138 #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC                        128
 139 #define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC                129
 140 #define GCC_USB30_PRIM_SLEEP_CLK                                130
 141 #define GCC_USB3_0_CLKREF_EN                                    131
 142 #define GCC_USB3_PRIM_PHY_AUX_CLK                               132
 143 #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC                           133
 144 #define GCC_USB3_PRIM_PHY_COM_AUX_CLK                           134
 145 #define GCC_USB3_PRIM_PHY_PIPE_CLK                              135
 146 #define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC                          136
 147 #define GCC_VCODEC0_AXI_CLK                                     137
 148 #define GCC_VENUS_CTL_AXI_CLK                                   138
 149 #define GCC_VIDEO_AHB_CLK                                       139
 150 #define GCC_VIDEO_THROTTLE_CORE_CLK                             140
 151 #define GCC_VIDEO_VCODEC0_SYS_CLK                               141
 152 #define GCC_VIDEO_VENUS_CLK_SRC                                 142
 153 #define GCC_VIDEO_VENUS_CTL_CLK                                 143
 154 #define GCC_VIDEO_XO_CLK                                        144
 155
 156 /* GCC power domains */
 157 #define GCC_PCIE_0_GDSC                                         0
 158 #define GCC_UFS_PHY_GDSC                                        1
 159 #define GCC_USB30_PRIM_GDSC                                     2
 160 #define GCC_VCODEC0_GDSC                                        3
 161 #define GCC_VENUS_GDSC                                          4
 162
 163 /* GCC resets */
 164 #define GCC_CAMERA_BCR                                          0
 165 #define GCC_DISPLAY_BCR                                         1
 166 #define GCC_GPU_BCR                                             2
 167 #define GCC_PCIE_0_BCR                                          3
 168 #define GCC_PCIE_0_LINK_DOWN_BCR                                4
 169 #define GCC_PCIE_0_NOCSR_COM_PHY_BCR                            5
 170 #define GCC_PCIE_0_PHY_BCR                                      6
 171 #define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR                        7
 172 #define GCC_PCIE_PHY_BCR                                        8
 173 #define GCC_PCIE_PHY_CFG_AHB_BCR                                9
 174 #define GCC_PCIE_PHY_COM_BCR                                    10
 175 #define GCC_PDM_BCR                                             11
 176 #define GCC_QUPV3_WRAPPER_0_BCR                                 12
 177 #define GCC_QUPV3_WRAPPER_1_BCR                                 13
 178 #define GCC_QUSB2PHY_PRIM_BCR                                   14
 179 #define GCC_QUSB2PHY_SEC_BCR                                    15
 180 #define GCC_SDCC1_BCR                                           16
 181 #define GCC_SDCC2_BCR                                           17
 182 #define GCC_UFS_PHY_BCR                                         18
 183 #define GCC_USB30_PRIM_BCR                                      19
 184 #define GCC_USB3_DP_PHY_PRIM_BCR                                20
 185 #define GCC_USB3_DP_PHY_SEC_BCR                                 21
 186 #define GCC_USB3_PHY_PRIM_BCR                                   22
 187 #define GCC_USB3_PHY_SEC_BCR                                    23
 188 #define GCC_USB3PHY_PHY_PRIM_BCR                                24
 189 #define GCC_USB3PHY_PHY_SEC_BCR                                 25
 190 #define GCC_VCODEC0_BCR                                         26
 191 #define GCC_VENUS_BCR                                           27
 192 #define GCC_VIDEO_BCR                                           28
 193 #define GCC_VIDEO_VENUS_BCR                                     29
 194 #define GCC_VENUS_CTL_AXI_CLK_ARES                              30
 195 #define GCC_VIDEO_VENUS_CTL_CLK_ARES                            31
 196
 197 #endif