include/dt-bindings/clock/sun50i-h616-ccu.h

   1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
   2 /*
   3  * Copyright (C) 2020 Arm Ltd.
   4  */
   5
   6 #ifndef _DT_BINDINGS_CLK_SUN50I_H616_H_
   7 #define _DT_BINDINGS_CLK_SUN50I_H616_H_
   8
   9 #define CLK_PLL_PERIPH0         4
  10
  11 #define CLK_CPUX                21
  12
  13 #define CLK_APB1                26
  14
  15 #define CLK_DE                  29
  16 #define CLK_BUS_DE              30
  17 #define CLK_DEINTERLACE         31
  18 #define CLK_BUS_DEINTERLACE     32
  19 #define CLK_G2D                 33
  20 #define CLK_BUS_G2D             34
  21 #define CLK_GPU0                35
  22 #define CLK_BUS_GPU             36
  23 #define CLK_GPU1                37
  24 #define CLK_CE                  38
  25 #define CLK_BUS_CE              39
  26 #define CLK_VE                  40
  27 #define CLK_BUS_VE              41
  28 #define CLK_BUS_DMA             42
  29 #define CLK_BUS_HSTIMER         43
  30 #define CLK_AVS                 44
  31 #define CLK_BUS_DBG             45
  32 #define CLK_BUS_PSI             46
  33 #define CLK_BUS_PWM             47
  34 #define CLK_BUS_IOMMU           48
  35
  36 #define CLK_MBUS_DMA            50
  37 #define CLK_MBUS_VE             51
  38 #define CLK_MBUS_CE             52
  39 #define CLK_MBUS_TS             53
  40 #define CLK_MBUS_NAND           54
  41 #define CLK_MBUS_G2D            55
  42
  43 #define CLK_NAND0               57
  44 #define CLK_NAND1               58
  45 #define CLK_BUS_NAND            59
  46 #define CLK_MMC0                60
  47 #define CLK_MMC1                61
  48 #define CLK_MMC2                62
  49 #define CLK_BUS_MMC0            63
  50 #define CLK_BUS_MMC1            64
  51 #define CLK_BUS_MMC2            65
  52 #define CLK_BUS_UART0           66
  53 #define CLK_BUS_UART1           67
  54 #define CLK_BUS_UART2           68
  55 #define CLK_BUS_UART3           69
  56 #define CLK_BUS_UART4           70
  57 #define CLK_BUS_UART5           71
  58 #define CLK_BUS_I2C0            72
  59 #define CLK_BUS_I2C1            73
  60 #define CLK_BUS_I2C2            74
  61 #define CLK_BUS_I2C3            75
  62 #define CLK_BUS_I2C4            76
  63 #define CLK_SPI0                77
  64 #define CLK_SPI1                78
  65 #define CLK_BUS_SPI0            79
  66 #define CLK_BUS_SPI1            80
  67 #define CLK_EMAC_25M            81
  68 #define CLK_BUS_EMAC0           82
  69 #define CLK_BUS_EMAC1           83
  70 #define CLK_TS                  84
  71 #define CLK_BUS_TS              85
  72 #define CLK_BUS_THS             86
  73 #define CLK_SPDIF               87
  74 #define CLK_BUS_SPDIF           88
  75 #define CLK_DMIC                89
  76 #define CLK_BUS_DMIC            90
  77 #define CLK_AUDIO_CODEC_1X      91
  78 #define CLK_AUDIO_CODEC_4X      92
  79 #define CLK_BUS_AUDIO_CODEC     93
  80 #define CLK_AUDIO_HUB           94
  81 #define CLK_BUS_AUDIO_HUB       95
  82 #define CLK_USB_OHCI0           96
  83 #define CLK_USB_PHY0            97
  84 #define CLK_USB_OHCI1           98
  85 #define CLK_USB_PHY1            99
  86 #define CLK_USB_OHCI2           100
  87 #define CLK_USB_PHY2            101
  88 #define CLK_USB_OHCI3           102
  89 #define CLK_USB_PHY3            103
  90 #define CLK_BUS_OHCI0           104
  91 #define CLK_BUS_OHCI1           105
  92 #define CLK_BUS_OHCI2           106
  93 #define CLK_BUS_OHCI3           107
  94 #define CLK_BUS_EHCI0           108
  95 #define CLK_BUS_EHCI1           109
  96 #define CLK_BUS_EHCI2           110
  97 #define CLK_BUS_EHCI3           111
  98 #define CLK_BUS_OTG             112
  99 #define CLK_BUS_KEYADC          113
 100 #define CLK_HDMI                114
 101 #define CLK_HDMI_SLOW           115
 102 #define CLK_HDMI_CEC            116
 103 #define CLK_BUS_HDMI            117
 104 #define CLK_BUS_TCON_TOP        118
 105 #define CLK_TCON_TV0            119
 106 #define CLK_TCON_TV1            120
 107 #define CLK_BUS_TCON_TV0        121
 108 #define CLK_BUS_TCON_TV1        122
 109 #define CLK_TVE0                123
 110 #define CLK_BUS_TVE_TOP         124
 111 #define CLK_BUS_TVE0            125
 112 #define CLK_HDCP                126
 113 #define CLK_BUS_HDCP            127
 114 #define CLK_PLL_SYSTEM_32K      128
 115
 116 #endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */