include/dt-bindings/memory/mediatek,mt8365-larb-port.h

   1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
   2 /*
   3  * Copyright (c) 2022 MediaTek Inc.
   4  * Author: Yong Wu <yong.wu@mediatek.com>
   5  */
   6 #ifndef _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_
   7 #define _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_
   8
   9 #include <dt-bindings/memory/mtk-memory-port.h>
  10
  11 #define M4U_LARB0_ID                    0
  12 #define M4U_LARB1_ID                    1
  13 #define M4U_LARB2_ID                    2
  14 #define M4U_LARB3_ID                    3
  15
  16 /* larb0 */
  17 #define M4U_PORT_DISP_OVL0              MTK_M4U_ID(M4U_LARB0_ID, 0)
  18 #define M4U_PORT_DISP_OVL0_2L           MTK_M4U_ID(M4U_LARB0_ID, 1)
  19 #define M4U_PORT_DISP_RDMA0             MTK_M4U_ID(M4U_LARB0_ID, 2)
  20 #define M4U_PORT_DISP_WDMA0             MTK_M4U_ID(M4U_LARB0_ID, 3)
  21 #define M4U_PORT_DISP_RDMA1             MTK_M4U_ID(M4U_LARB0_ID, 4)
  22 #define M4U_PORT_MDP_RDMA0              MTK_M4U_ID(M4U_LARB0_ID, 5)
  23 #define M4U_PORT_MDP_WROT1              MTK_M4U_ID(M4U_LARB0_ID, 6)
  24 #define M4U_PORT_MDP_WROT0              MTK_M4U_ID(M4U_LARB0_ID, 7)
  25 #define M4U_PORT_MDP_RDMA1              MTK_M4U_ID(M4U_LARB0_ID, 8)
  26 #define M4U_PORT_DISP_FAKE0             MTK_M4U_ID(M4U_LARB0_ID, 9)
  27 #define M4U_PORT_APU_READ               MTK_M4U_ID(M4U_LARB0_ID, 10)
  28 #define M4U_PORT_APU_WRITE              MTK_M4U_ID(M4U_LARB0_ID, 11)
  29
  30 /* larb1 */
  31 #define M4U_PORT_VENC_RCPU              MTK_M4U_ID(M4U_LARB1_ID, 0)
  32 #define M4U_PORT_VENC_REC               MTK_M4U_ID(M4U_LARB1_ID, 1)
  33 #define M4U_PORT_VENC_BSDMA             MTK_M4U_ID(M4U_LARB1_ID, 2)
  34 #define M4U_PORT_VENC_SV_COMV           MTK_M4U_ID(M4U_LARB1_ID, 3)
  35 #define M4U_PORT_VENC_RD_COMV           MTK_M4U_ID(M4U_LARB1_ID, 4)
  36 #define M4U_PORT_VENC_NBM_RDMA          MTK_M4U_ID(M4U_LARB1_ID, 5)
  37 #define M4U_PORT_VENC_NBM_RDMA_LITE     MTK_M4U_ID(M4U_LARB1_ID, 6)
  38 #define M4U_PORT_JPGENC_Y_RDMA          MTK_M4U_ID(M4U_LARB1_ID, 7)
  39 #define M4U_PORT_JPGENC_C_RDMA          MTK_M4U_ID(M4U_LARB1_ID, 8)
  40 #define M4U_PORT_JPGENC_Q_TABLE         MTK_M4U_ID(M4U_LARB1_ID, 9)
  41 #define M4U_PORT_JPGENC_BSDMA           MTK_M4U_ID(M4U_LARB1_ID, 10)
  42 #define M4U_PORT_JPGDEC_WDMA            MTK_M4U_ID(M4U_LARB1_ID, 11)
  43 #define M4U_PORT_JPGDEC_BSDMA           MTK_M4U_ID(M4U_LARB1_ID, 12)
  44 #define M4U_PORT_VENC_NBM_WDMA          MTK_M4U_ID(M4U_LARB1_ID, 13)
  45 #define M4U_PORT_VENC_NBM_WDMA_LITE     MTK_M4U_ID(M4U_LARB1_ID, 14)
  46 #define M4U_PORT_VENC_CUR_LUMA          MTK_M4U_ID(M4U_LARB1_ID, 15)
  47 #define M4U_PORT_VENC_CUR_CHROMA        MTK_M4U_ID(M4U_LARB1_ID, 16)
  48 #define M4U_PORT_VENC_REF_LUMA          MTK_M4U_ID(M4U_LARB1_ID, 17)
  49 #define M4U_PORT_VENC_REF_CHROMA        MTK_M4U_ID(M4U_LARB1_ID, 18)
  50
  51 /* larb2 */
  52 #define M4U_PORT_CAM_IMGO               MTK_M4U_ID(M4U_LARB2_ID, 0)
  53 #define M4U_PORT_CAM_RRZO               MTK_M4U_ID(M4U_LARB2_ID, 1)
  54 #define M4U_PORT_CAM_AAO                MTK_M4U_ID(M4U_LARB2_ID, 2)
  55 #define M4U_PORT_CAM_LCS                MTK_M4U_ID(M4U_LARB2_ID, 3)
  56 #define M4U_PORT_CAM_ESFKO              MTK_M4U_ID(M4U_LARB2_ID, 4)
  57 #define M4U_PORT_CAM_CAM_SV0            MTK_M4U_ID(M4U_LARB2_ID, 5)
  58 #define M4U_PORT_CAM_CAM_SV1            MTK_M4U_ID(M4U_LARB2_ID, 6)
  59 #define M4U_PORT_CAM_LSCI               MTK_M4U_ID(M4U_LARB2_ID, 7)
  60 #define M4U_PORT_CAM_LSCI_D             MTK_M4U_ID(M4U_LARB2_ID, 8)
  61 #define M4U_PORT_CAM_AFO                MTK_M4U_ID(M4U_LARB2_ID, 9)
  62 #define M4U_PORT_CAM_SPARE              MTK_M4U_ID(M4U_LARB2_ID, 10)
  63 #define M4U_PORT_CAM_BPCI               MTK_M4U_ID(M4U_LARB2_ID, 11)
  64 #define M4U_PORT_CAM_BPCI_D             MTK_M4U_ID(M4U_LARB2_ID, 12)
  65 #define M4U_PORT_CAM_UFDI               MTK_M4U_ID(M4U_LARB2_ID, 13)
  66 #define M4U_PORT_CAM_IMGI               MTK_M4U_ID(M4U_LARB2_ID, 14)
  67 #define M4U_PORT_CAM_IMG2O              MTK_M4U_ID(M4U_LARB2_ID, 15)
  68 #define M4U_PORT_CAM_IMG3O              MTK_M4U_ID(M4U_LARB2_ID, 16)
  69 #define M4U_PORT_CAM_WPE0_I             MTK_M4U_ID(M4U_LARB2_ID, 17)
  70 #define M4U_PORT_CAM_WPE1_I             MTK_M4U_ID(M4U_LARB2_ID, 18)
  71 #define M4U_PORT_CAM_WPE_O              MTK_M4U_ID(M4U_LARB2_ID, 19)
  72 #define M4U_PORT_CAM_FD0_I              MTK_M4U_ID(M4U_LARB2_ID, 20)
  73 #define M4U_PORT_CAM_FD1_I              MTK_M4U_ID(M4U_LARB2_ID, 21)
  74 #define M4U_PORT_CAM_FD0_O              MTK_M4U_ID(M4U_LARB2_ID, 22)
  75 #define M4U_PORT_CAM_FD1_O              MTK_M4U_ID(M4U_LARB2_ID, 23)
  76
  77 /* larb3 */
  78 #define M4U_PORT_HW_VDEC_MC_EXT         MTK_M4U_ID(M4U_LARB3_ID, 0)
  79 #define M4U_PORT_HW_VDEC_UFO_EXT        MTK_M4U_ID(M4U_LARB3_ID, 1)
  80 #define M4U_PORT_HW_VDEC_PP_EXT         MTK_M4U_ID(M4U_LARB3_ID, 2)
  81 #define M4U_PORT_HW_VDEC_PRED_RD_EXT    MTK_M4U_ID(M4U_LARB3_ID, 3)
  82 #define M4U_PORT_HW_VDEC_PRED_WR_EXT    MTK_M4U_ID(M4U_LARB3_ID, 4)
  83 #define M4U_PORT_HW_VDEC_PPWRAP_EXT     MTK_M4U_ID(M4U_LARB3_ID, 5)
  84 #define M4U_PORT_HW_VDEC_TILE_EXT       MTK_M4U_ID(M4U_LARB3_ID, 6)
  85 #define M4U_PORT_HW_VDEC_VLD_EXT        MTK_M4U_ID(M4U_LARB3_ID, 7)
  86 #define M4U_PORT_HW_VDEC_VLD2_EXT       MTK_M4U_ID(M4U_LARB3_ID, 8)
  87 #define M4U_PORT_HW_VDEC_AVC_MV_EXT     MTK_M4U_ID(M4U_LARB3_ID, 9)
  88 #define M4U_PORT_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(M4U_LARB3_ID, 10)
  89
  90 #endif