1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (c) 2015 Google, Inc
4 * Copyright 2014 Rockchip Inc.
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
14 #define HDMI_EDID_BLOCK_SIZE 128
16 /* Identification Registers */
17 #define HDMI_DESIGN_ID 0x0000
18 #define HDMI_REVISION_ID 0x0001
19 #define HDMI_PRODUCT_ID0 0x0002
20 #define HDMI_PRODUCT_ID1 0x0003
21 #define HDMI_CONFIG0_ID 0x0004
22 #define HDMI_CONFIG1_ID 0x0005
23 #define HDMI_CONFIG2_ID 0x0006
24 #define HDMI_CONFIG3_ID 0x0007
26 /* Interrupt Registers */
27 #define HDMI_IH_FC_STAT0 0x0100
28 #define HDMI_IH_FC_STAT1 0x0101
29 #define HDMI_IH_FC_STAT2 0x0102
30 #define HDMI_IH_AS_STAT0 0x0103
31 #define HDMI_IH_PHY_STAT0 0x0104
32 #define HDMI_IH_I2CM_STAT0 0x0105
33 #define HDMI_IH_CEC_STAT0 0x0106
34 #define HDMI_IH_VP_STAT0 0x0107
35 #define HDMI_IH_I2CMPHY_STAT0 0x0108
36 #define HDMI_IH_AHBDMAAUD_STAT0 0x0109
38 #define HDMI_IH_MUTE_FC_STAT0 0x0180
39 #define HDMI_IH_MUTE_FC_STAT1 0x0181
40 #define HDMI_IH_MUTE_FC_STAT2 0x0182
41 #define HDMI_IH_MUTE_AS_STAT0 0x0183
42 #define HDMI_IH_MUTE_PHY_STAT0 0x0184
43 #define HDMI_IH_MUTE_I2CM_STAT0 0x0185
44 #define HDMI_IH_MUTE_CEC_STAT0 0x0186
45 #define HDMI_IH_MUTE_VP_STAT0 0x0187
46 #define HDMI_IH_MUTE_I2CMPHY_STAT0 0x0188
47 #define HDMI_IH_MUTE_AHBDMAAUD_STAT0 0x0189
48 #define HDMI_IH_MUTE 0x01FF
50 /* Video Sample Registers */
51 #define HDMI_TX_INVID0 0x0200
52 #define HDMI_TX_INSTUFFING 0x0201
53 #define HDMI_TX_GYDATA0 0x0202
54 #define HDMI_TX_GYDATA1 0x0203
55 #define HDMI_TX_RCRDATA0 0x0204
56 #define HDMI_TX_RCRDATA1 0x0205
57 #define HDMI_TX_BCBDATA0 0x0206
58 #define HDMI_TX_BCBDATA1 0x0207
60 /* Video Packetizer Registers */
61 #define HDMI_VP_STATUS 0x0800
62 #define HDMI_VP_PR_CD 0x0801
63 #define HDMI_VP_STUFF 0x0802
64 #define HDMI_VP_REMAP 0x0803
65 #define HDMI_VP_CONF 0x0804
66 #define HDMI_VP_STAT 0x0805
67 #define HDMI_VP_INT 0x0806
68 #define HDMI_VP_MASK 0x0807
69 #define HDMI_VP_POL 0x0808
71 /* Frame Composer Registers */
72 #define HDMI_FC_INVIDCONF 0x1000
73 #define HDMI_FC_INHACTV0 0x1001
74 #define HDMI_FC_INHACTV1 0x1002
75 #define HDMI_FC_INHBLANK0 0x1003
76 #define HDMI_FC_INHBLANK1 0x1004
77 #define HDMI_FC_INVACTV0 0x1005
78 #define HDMI_FC_INVACTV1 0x1006
79 #define HDMI_FC_INVBLANK 0x1007
80 #define HDMI_FC_HSYNCINDELAY0 0x1008
81 #define HDMI_FC_HSYNCINDELAY1 0x1009
82 #define HDMI_FC_HSYNCINWIDTH0 0x100A
83 #define HDMI_FC_HSYNCINWIDTH1 0x100B
84 #define HDMI_FC_VSYNCINDELAY 0x100C
85 #define HDMI_FC_VSYNCINWIDTH 0x100D
86 #define HDMI_FC_INFREQ0 0x100E
87 #define HDMI_FC_INFREQ1 0x100F
88 #define HDMI_FC_INFREQ2 0x1010
89 #define HDMI_FC_CTRLDUR 0x1011
90 #define HDMI_FC_EXCTRLDUR 0x1012
91 #define HDMI_FC_EXCTRLSPAC 0x1013
92 #define HDMI_FC_CH0PREAM 0x1014
93 #define HDMI_FC_CH1PREAM 0x1015
94 #define HDMI_FC_CH2PREAM 0x1016
95 #define HDMI_FC_AVICONF3 0x1017
96 #define HDMI_FC_GCP 0x1018
97 #define HDMI_FC_AVICONF0 0x1019
98 #define HDMI_FC_AVICONF1 0x101A
99 #define HDMI_FC_AVICONF2 0x101B
100 #define HDMI_FC_AVIVID 0x101C
101 #define HDMI_FC_AVIETB0 0x101D
102 #define HDMI_FC_AVIETB1 0x101E
103 #define HDMI_FC_AVISBB0 0x101F
104 #define HDMI_FC_AVISBB1 0x1020
105 #define HDMI_FC_AVIELB0 0x1021
106 #define HDMI_FC_AVIELB1 0x1022
107 #define HDMI_FC_AVISRB0 0x1023
108 #define HDMI_FC_AVISRB1 0x1024
109 #define HDMI_FC_AUDICONF0 0x1025
110 #define HDMI_FC_AUDICONF1 0x1026
111 #define HDMI_FC_AUDICONF2 0x1027
112 #define HDMI_FC_AUDICONF3 0x1028
113 #define HDMI_FC_VSDIEEEID0 0x1029
114 #define HDMI_FC_VSDSIZE 0x102A
116 /* HDMI Source PHY Registers */
117 #define HDMI_PHY_CONF0 0x3000
118 #define HDMI_PHY_TST0 0x3001
119 #define HDMI_PHY_TST1 0x3002
120 #define HDMI_PHY_TST2 0x3003
121 #define HDMI_PHY_STAT0 0x3004
122 #define HDMI_PHY_INT0 0x3005
123 #define HDMI_PHY_MASK0 0x3006
124 #define HDMI_PHY_POL0 0x3007
126 /* HDMI Master PHY Registers */
127 #define HDMI_PHY_I2CM_SLAVE_ADDR 0x3020
128 #define HDMI_PHY_I2CM_ADDRESS_ADDR 0x3021
129 #define HDMI_PHY_I2CM_DATAO_1_ADDR 0x3022
130 #define HDMI_PHY_I2CM_DATAO_0_ADDR 0x3023
131 #define HDMI_PHY_I2CM_DATAI_1_ADDR 0x3024
132 #define HDMI_PHY_I2CM_DATAI_0_ADDR 0x3025
133 #define HDMI_PHY_I2CM_OPERATION_ADDR 0x3026
134 #define HDMI_PHY_I2CM_INT_ADDR 0x3027
135 #define HDMI_PHY_I2CM_CTLINT_ADDR 0x3028
136 #define HDMI_PHY_I2CM_DIV_ADDR 0x3029
137 #define HDMI_PHY_I2CM_SOFTRSTZ_ADDR 0x302a
138 #define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR 0x302b
139 #define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR 0x302c
140 #define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR 0x302d
141 #define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR 0x302e
142 #define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR 0x302f
143 #define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR 0x3030
144 #define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR 0x3031
145 #define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR 0x3032
147 /* Audio Sampler Registers */
148 #define HDMI_AUD_CONF0 0x3100
149 #define HDMI_AUD_CONF1 0x3101
150 #define HDMI_AUD_INT 0x3102
151 #define HDMI_AUD_CONF2 0x3103
152 #define HDMI_AUD_INT1 0x3104
153 #define HDMI_AUD_N1 0x3200
154 #define HDMI_AUD_N2 0x3201
155 #define HDMI_AUD_N3 0x3202
156 #define HDMI_AUD_CTS1 0x3203
157 #define HDMI_AUD_CTS2 0x3204
158 #define HDMI_AUD_CTS3 0x3205
159 #define HDMI_AUD_INPUTCLKFS 0x3206
160 #define HDMI_AUD_SPDIFINT 0x3302
161 #define HDMI_AUD_CONF0_HBR 0x3400
162 #define HDMI_AUD_HBR_STATUS 0x3401
163 #define HDMI_AUD_HBR_INT 0x3402
164 #define HDMI_AUD_HBR_POL 0x3403
165 #define HDMI_AUD_HBR_MASK 0x3404
167 /* Main Controller Registers */
168 #define HDMI_MC_SFRDIV 0x4000
169 #define HDMI_MC_CLKDIS 0x4001
170 #define HDMI_MC_SWRSTZ 0x4002
171 #define HDMI_MC_OPCTRL 0x4003
172 #define HDMI_MC_FLOWCTRL 0x4004
173 #define HDMI_MC_PHYRSTZ 0x4005
174 #define HDMI_MC_LOCKONCLOCK 0x4006
175 #define HDMI_MC_HEACPHY_RST 0x4007
177 /* I2C Master Registers (E-DDC) */
178 #define HDMI_I2CM_SLAVE 0x7E00
179 #define HDMI_I2CM_ADDRESS 0x7E01
180 #define HDMI_I2CM_DATAO 0x7E02
181 #define HDMI_I2CM_DATAI 0x7E03
182 #define HDMI_I2CM_OPERATION 0x7E04
183 #define HDMI_I2CM_INT 0x7E05
184 #define HDMI_I2CM_CTLINT 0x7E06
185 #define HDMI_I2CM_DIV 0x7E07
186 #define HDMI_I2CM_SEGADDR 0x7E08
187 #define HDMI_I2CM_SOFTRSTZ 0x7E09
188 #define HDMI_I2CM_SEGPTR 0x7E0A
189 #define HDMI_I2CM_SS_SCL_HCNT_1_ADDR 0x7E0B
190 #define HDMI_I2CM_SS_SCL_HCNT_0_ADDR 0x7E0C
191 #define HDMI_I2CM_SS_SCL_LCNT_1_ADDR 0x7E0D
192 #define HDMI_I2CM_SS_SCL_LCNT_0_ADDR 0x7E0E
193 #define HDMI_I2CM_FS_SCL_HCNT_1_ADDR 0x7E0F
194 #define HDMI_I2CM_FS_SCL_HCNT_0_ADDR 0x7E10
195 #define HDMI_I2CM_FS_SCL_LCNT_1_ADDR 0x7E11
196 #define HDMI_I2CM_FS_SCL_LCNT_0_ADDR 0x7E12
197 #define HDMI_I2CM_BUF0 0x7E20
200 /* HDMI PHY registers define */
201 PHY_OPMODE_PLLCFG
= 0x06,
202 PHY_CKCALCTRL
= 0x05,
203 PHY_CKSYMTXCTRL
= 0x09,
205 PHY_PLLCURRCTRL
= 0x10,
206 PHY_PLLPHBYCTRL
= 0x13,
207 PHY_PLLGMPCTRL
= 0x15,
208 PHY_PLLCLKBISTPHASE
= 0x17,
211 /* ih_phy_stat0 field values */
212 HDMI_IH_PHY_STAT0_HPD
= 0x1,
214 /* ih_mute field values */
215 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT
= 0x2,
216 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT
= 0x1,
218 /* tx_invid0 field values */
219 HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE
= 0x00,
220 HDMI_TX_INVID0_VIDEO_MAPPING_MASK
= 0x1f,
221 HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET
= 0,
223 /* tx_instuffing field values */
224 HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE
= 0x4,
225 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE
= 0x2,
226 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE
= 0x1,
228 /* vp_pr_cd field values */
229 HDMI_VP_PR_CD_COLOR_DEPTH_MASK
= 0xf0,
230 HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET
= 4,
231 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK
= 0x0f,
232 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET
= 0,
234 /* vp_stuff field values */
235 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK
= 0x20,
236 HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET
= 5,
237 HDMI_VP_STUFF_YCC422_STUFFING_MASK
= 0x4,
238 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE
= 0x4,
239 HDMI_VP_STUFF_PP_STUFFING_MASK
= 0x2,
240 HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE
= 0x2,
241 HDMI_VP_STUFF_PR_STUFFING_MASK
= 0x1,
242 HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE
= 0x1,
244 /* vp_conf field values */
245 HDMI_VP_CONF_BYPASS_EN_MASK
= 0x40,
246 HDMI_VP_CONF_BYPASS_EN_ENABLE
= 0x40,
247 HDMI_VP_CONF_PP_EN_ENMASK
= 0x20,
248 HDMI_VP_CONF_PP_EN_DISABLE
= 0x00,
249 HDMI_VP_CONF_PR_EN_MASK
= 0x10,
250 HDMI_VP_CONF_PR_EN_DISABLE
= 0x00,
251 HDMI_VP_CONF_YCC422_EN_MASK
= 0x8,
252 HDMI_VP_CONF_YCC422_EN_DISABLE
= 0x0,
253 HDMI_VP_CONF_BYPASS_SELECT_MASK
= 0x4,
254 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER
= 0x4,
255 HDMI_VP_CONF_OUTPUT_SELECTOR_MASK
= 0x3,
256 HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS
= 0x3,
258 /* vp_remap field values */
259 HDMI_VP_REMAP_YCC422_16BIT
= 0x0,
261 /* fc_invidconf field values */
262 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK
= 0x80,
263 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE
= 0x80,
264 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE
= 0x00,
265 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK
= 0x40,
266 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH
= 0x40,
267 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW
= 0x00,
268 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK
= 0x20,
269 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH
= 0x20,
270 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW
= 0x00,
271 HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK
= 0x10,
272 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH
= 0x10,
273 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW
= 0x00,
274 HDMI_FC_INVIDCONF_DVI_MODEZ_MASK
= 0x8,
275 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE
= 0x8,
276 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE
= 0x0,
277 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK
= 0x2,
278 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH
= 0x2,
279 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW
= 0x0,
280 HDMI_FC_INVIDCONF_IN_I_P_MASK
= 0x1,
281 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED
= 0x1,
282 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE
= 0x0,
285 /* fc_aviconf0-fc_aviconf3 field values */
286 HDMI_FC_AVICONF0_PIX_FMT_MASK
= 0x03,
287 HDMI_FC_AVICONF0_PIX_FMT_RGB
= 0x00,
288 HDMI_FC_AVICONF0_PIX_FMT_YCBCR422
= 0x01,
289 HDMI_FC_AVICONF0_PIX_FMT_YCBCR444
= 0x02,
290 HDMI_FC_AVICONF0_ACTIVE_FMT_MASK
= 0x40,
291 HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT
= 0x40,
292 HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO
= 0x00,
293 HDMI_FC_AVICONF0_BAR_DATA_MASK
= 0x0c,
294 HDMI_FC_AVICONF0_BAR_DATA_NO_DATA
= 0x00,
295 HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR
= 0x04,
296 HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR
= 0x08,
297 HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR
= 0x0c,
298 HDMI_FC_AVICONF0_SCAN_INFO_MASK
= 0x30,
299 HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN
= 0x10,
300 HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN
= 0x20,
301 HDMI_FC_AVICONF0_SCAN_INFO_NODATA
= 0x00,
303 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK
= 0x0f,
304 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED
= 0x08,
305 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3
= 0x09,
306 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9
= 0x0a,
307 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9
= 0x0b,
308 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK
= 0x30,
309 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA
= 0x00,
310 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3
= 0x10,
311 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9
= 0x20,
312 HDMI_FC_AVICONF1_COLORIMETRY_MASK
= 0xc0,
313 HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA
= 0x00,
314 HDMI_FC_AVICONF1_COLORIMETRY_SMPTE
= 0x40,
315 HDMI_FC_AVICONF1_COLORIMETRY_ITUR
= 0x80,
316 HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO
= 0xc0,
318 HDMI_FC_AVICONF2_SCALING_MASK
= 0x03,
319 HDMI_FC_AVICONF2_SCALING_NONE
= 0x00,
320 HDMI_FC_AVICONF2_SCALING_HORIZ
= 0x01,
321 HDMI_FC_AVICONF2_SCALING_VERT
= 0x02,
322 HDMI_FC_AVICONF2_SCALING_HORIZ_vert
= 0x03,
323 HDMI_FC_AVICONF2_RGB_QUANT_MASK
= 0x0c,
324 HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT
= 0x00,
325 HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE
= 0x04,
326 HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE
= 0x08,
327 HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK
= 0x70,
328 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601
= 0x00,
329 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709
= 0x10,
330 HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601
= 0x20,
331 HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601
= 0x30,
332 HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB
= 0x40,
333 HDMI_FC_AVICONF2_IT_CONTENT_MASK
= 0x80,
334 HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA
= 0x00,
335 HDMI_FC_AVICONF2_IT_CONTENT_VALID
= 0x80,
337 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK
= 0x03,
338 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS
= 0x00,
339 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO
= 0x01,
340 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA
= 0x02,
341 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME
= 0x03,
342 HDMI_FC_AVICONF3_QUANT_RANGE_MASK
= 0x0c,
343 HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED
= 0x00,
344 HDMI_FC_AVICONF3_QUANT_RANGE_FULL
= 0x04,
346 /* fc_gcp field values*/
347 HDMI_FC_GCP_SET_AVMUTE
= 0x02,
348 HDMI_FC_GCP_CLEAR_AVMUTE
= 0x01,
350 /* phy_conf0 field values */
351 HDMI_PHY_CONF0_PDZ_MASK
= 0x80,
352 HDMI_PHY_CONF0_PDZ_OFFSET
= 7,
353 HDMI_PHY_CONF0_ENTMDS_MASK
= 0x40,
354 HDMI_PHY_CONF0_ENTMDS_OFFSET
= 6,
355 HDMI_PHY_CONF0_SPARECTRL_MASK
= 0x20,
356 HDMI_PHY_CONF0_SPARECTRL_OFFSET
= 5,
357 HDMI_PHY_CONF0_GEN2_PDDQ_MASK
= 0x10,
358 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET
= 4,
359 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK
= 0x8,
360 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET
= 3,
361 HDMI_PHY_CONF0_SELDATAENPOL_MASK
= 0x2,
362 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET
= 1,
363 HDMI_PHY_CONF0_SELDIPIF_MASK
= 0x1,
364 HDMI_PHY_CONF0_SELDIPIF_OFFSET
= 0,
366 /* phy_tst0 field values */
367 HDMI_PHY_TST0_TSTCLR_MASK
= 0x20,
368 HDMI_PHY_TST0_TSTCLR_OFFSET
= 5,
370 /* phy_stat0 field values */
372 HDMI_PHY_TX_PHY_LOCK
= 0x01,
374 /* phy_i2cm_slave_addr field values */
375 HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2
= 0x69,
377 /* phy_i2cm_operation_addr field values */
378 HDMI_PHY_I2CM_OPERATION_ADDR_WRITE
= 0x10,
380 /* hdmi_phy_i2cm_int_addr */
381 HDMI_PHY_I2CM_INT_ADDR_DONE_POL
= 0x08,
383 /* hdmi_phy_i2cm_ctlint_addr */
384 HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL
= 0x80,
385 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL
= 0x08,
387 /* aud_conf0 field values */
388 HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST
= 0x80,
389 HDMI_AUD_CONF0_I2S_SELECT
= 0x20,
390 HDMI_AUD_CONF0_I2S_IN_EN_0
= 0x01,
391 HDMI_AUD_CONF0_I2S_IN_EN_1
= 0x02,
392 HDMI_AUD_CONF0_I2S_IN_EN_2
= 0x04,
393 HDMI_AUD_CONF0_I2S_IN_EN_3
= 0x08,
395 /* aud_conf0 field values */
396 HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE
= 0x0,
397 HDMI_AUD_CONF1_I2S_WIDTH_16BIT
= 0x10,
399 /* aud_n3 field values */
400 HDMI_AUD_N3_NCTS_ATOMIC_WRITE
= 0x80,
401 HDMI_AUD_N3_AUDN19_16_MASK
= 0x0f,
403 /* aud_cts3 field values */
404 HDMI_AUD_CTS3_N_SHIFT_OFFSET
= 5,
405 HDMI_AUD_CTS3_N_SHIFT_MASK
= 0xe0,
406 HDMI_AUD_CTS3_N_SHIFT_1
= 0,
407 HDMI_AUD_CTS3_N_SHIFT_16
= 0x20,
408 HDMI_AUD_CTS3_N_SHIFT_32
= 0x40,
409 HDMI_AUD_CTS3_N_SHIFT_64
= 0x60,
410 HDMI_AUD_CTS3_N_SHIFT_128
= 0x80,
411 HDMI_AUD_CTS3_N_SHIFT_256
= 0xa0,
412 HDMI_AUD_CTS3_CTS_MANUAL
= 0x10,
413 HDMI_AUD_CTS3_AUDCTS19_16_MASK
= 0x0f,
415 /* aud_inputclkfs filed values */
416 HDMI_AUD_INPUTCLKFS_128
= 0x0,
418 /* mc_clkdis field values */
419 HDMI_MC_CLKDIS_AUDCLK_DISABLE
= 0x8,
420 HDMI_MC_CLKDIS_TMDSCLK_DISABLE
= 0x2,
421 HDMI_MC_CLKDIS_PIXELCLK_DISABLE
= 0x1,
423 /* mc_swrstz field values */
424 HDMI_MC_SWRSTZ_II2SSWRST_REQ
= 0x08,
425 HDMI_MC_SWRSTZ_TMDSSWRST_REQ
= 0x02,
427 /* mc_flowctrl field values */
428 HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH
= 0x1,
429 HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS
= 0x0,
431 /* mc_phyrstz field values */
432 HDMI_MC_PHYRSTZ_ASSERT
= 0x0,
433 HDMI_MC_PHYRSTZ_DEASSERT
= 0x1,
435 /* mc_heacphy_rst field values */
436 HDMI_MC_HEACPHY_RST_ASSERT
= 0x1,
438 /* i2cm filed values */
439 HDMI_I2CM_SLAVE_DDC_ADDR
= 0x50,
440 HDMI_I2CM_SEGADDR_DDC
= 0x30,
441 HDMI_I2CM_OP_RD8_EXT
= 0x2,
442 HDMI_I2CM_OP_RD8
= 0x1,
443 HDMI_I2CM_DIV_FAST_STD_MODE
= 0x8,
444 HDMI_I2CM_DIV_FAST_MODE
= 0x8,
445 HDMI_I2CM_DIV_STD_MODE
= 0x0,
446 HDMI_I2CM_SOFTRSTZ_MASK
= 0x1,
449 struct hdmi_mpll_config
{
451 /* Mode of Operation and PLL Dividers Control Register */
453 /* PLL Gmp Control Register */
455 /* PLL Current Control Register */
459 struct hdmi_phy_config
{
461 u32 sym_ctr
; /* clock symbol and transmitter control */
462 u32 term
; /* transmission termination value */
463 u32 vlev_ctr
; /* voltage level control */
468 const struct hdmi_mpll_config
*mpll_cfg
;
469 const struct hdmi_phy_config
*phy_cfg
;
474 int (*phy_set
)(struct dw_hdmi
*hdmi
, uint mpixelclock
);
477 int dw_hdmi_phy_cfg(struct dw_hdmi
*hdmi
, uint mpixelclock
);
478 int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi
*hdmi
);
479 void dw_hdmi_phy_init(struct dw_hdmi
*hdmi
);
481 int dw_hdmi_enable(struct dw_hdmi
*hdmi
, const struct display_timing
*edid
);
482 int dw_hdmi_read_edid(struct dw_hdmi
*hdmi
, u8
*buf
, int buf_size
);
483 void dw_hdmi_init(struct dw_hdmi
*hdmi
);