include/e500.h

   1 /*
   2  * Copyright 2003 Motorola,Inc.
   3  * Xianghua Xiao(x.xiao@motorola.com)
   4  */
   5
   6 #ifndef __E500_H__
   7 #define __E500_H__
   8
   9 #ifndef __ASSEMBLY__
  10
  11 typedef struct
  12 {
  13   unsigned long freqProcessor;
  14   unsigned long freqSystemBus;
  15   unsigned long freqDDRBus;
  16 } MPC85xx_SYS_INFO;
  17
  18 #endif  /* _ASMLANGUAGE */
  19
  20 /* Motorola E500 core provides 16 TLB1 entries; they can be used for
  21  * initial memory mapping like legacy BAT registers do. Usually we
  22  * use four MAS registers(MAS0-3) to operate on TLB1 entries.
  23  *
  24  * While there are 16 Entries with variable Page Sizes in TLB1,
  25  * there are also 256 Entries with fixed 4K pages in TLB0.
  26  *
  27  * We also need LAWs(Local Access Window) to associate a range of
  28  * the local 32-bit address space with a particular target interface
  29  * such as PCI/PCI-X, RapidIO, Local Bus and DDR SDRAM.
  30  *
  31  * We put TLB1/LAW code here because memory mapping is board-specific
  32  * instead of cpu-specific.
  33  *
  34  * While these macros are all nominally for TLB1 by name, they can
  35  * also be used for TLB0 as well.
  36  */
  37
  38
  39 /*
  40  * Convert addresses to Effective and Real Page Numbers.
  41  * Grab the high 20-bits and shift 'em down, dropping the "byte offset".
  42  */
  43 #define E500_TLB_EPN(addr)      (((addr) >> 12) & 0xfffff)
  44 #define E500_TLB_RPN(addr)      (((addr) >> 12) & 0xfffff)
  45
  46
  47 /* MAS0
  48  * tlbsel(TLB Select):0,1
  49  * esel(Entry Select): 0,1,2,...,15 for TLB1
  50  * nv(Next victim):0,1
  51  */
  52 #define TLB1_MAS0(tlbsel,esel,nv) \
  53                         (MAS0_TLBSEL(tlbsel) | MAS0_ESEL(esel) | MAS0_NV(nv))
  54
  55 /* MAS1
  56  * v(TLB valid bit):0,1
  57  * iprot(invalidate protect):0,1
  58  * tid(translation identity):8bit to match process IDs
  59  * ts(translation space,comparing with MSR[IS,DS]): 0,1
  60  * tsize(translation size):1,2,...,9(4K,16K,64K,256K,1M,4M,16M,64M,256M)
  61  */
  62 #define TLB1_MAS1(v,iprot,tid,ts,tsize) \
  63                         ((((v) << 31) & MAS1_VALID)             |\
  64                         (((iprot) << 30) & MAS1_IPROT)          |\
  65                         (MAS1_TID(tid))                         |\
  66                         (((ts) << 12) & MAS1_TS)                |\
  67                         (MAS1_TSIZE(tsize)))
  68
  69 /* MAS2
  70  * epn(effective page number):20bits
  71  * sharen(Shared cache state):0,1
  72  * x0,x1(implementation specific page attribute):0,1
  73  * w,i,m,g,e(write-through,cache-inhibited,memory coherency,guarded,
  74  *      endianness):0,1
  75  */
  76 #define TLB1_MAS2(epn,sharen,x0,x1,w,i,m,g,e) \
  77                         ((((epn) << 12) & MAS2_EPN)             |\
  78                         (((x0) << 6) & MAS2_X0)                 |\
  79                         (((x1) << 5) & MAS2_X1)                 |\
  80                         (((w) << 4) & MAS2_W)                   |\
  81                         (((i) << 3) & MAS2_I)                   |\
  82                         (((m) << 2) & MAS2_M)                   |\
  83                         (((g) << 1) & MAS2_G)                   |\
  84                         (e) )
  85
  86 /* MAS3
  87  * rpn(real page number):20bits
  88  * u0-u3(user bits, useful for page table management in OS):0,1
  89  * ux,sx,uw,sw,ur,sr(permission bits, user and supervisor read,
  90  *      write,execute permission).
  91  */
  92 #define TLB1_MAS3(rpn,u0,u1,u2,u3,ux,sx,uw,sw,ur,sr) \
  93                         ((((rpn) << 12) & MAS3_RPN)             |\
  94                         (((u0) << 9) & MAS3_U0)                 |\
  95                         (((u1) << 8) & MAS3_U1)                 |\
  96                         (((u2) << 7) & MAS3_U2)                 |\
  97                         (((u3) << 6) & MAS3_U3)                 |\
  98                         (((ux) << 5) & MAS3_UX)                 |\
  99                         (((sx) << 4) & MAS3_SX)                 |\
 100                         (((uw) << 3) & MAS3_UW)                 |\
 101                         (((sw) << 2) & MAS3_SW)                 |\
 102                         (((ur) << 1) & MAS3_UR)                 |\
 103                         (sr) )
 104
 105
 106 #define RESET_VECTOR    0xfffffffc
 107 #define CACHELINE_MASK  (CFG_CACHELINE_SIZE - 1) /* Address mask for cache
 108                                                      line aligned data. */
 109
 110 #endif  /* __E500_H__ */