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git.ipfire.org Git - thirdparty/qemu.git/blob - include/exec/cpu-defs.h
2 * common defines for all CPUs
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 #error cpu.h included from common code
29 #include "qemu/osdep.h"
30 #include "qemu/queue.h"
31 #include "exec/hwaddr.h"
33 #ifndef TARGET_LONG_BITS
34 #error TARGET_LONG_BITS must be defined before including this header
37 #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
39 typedef int16_t target_short
__attribute__ ((aligned(TARGET_SHORT_ALIGNMENT
)));
40 typedef uint16_t target_ushort
__attribute__((aligned(TARGET_SHORT_ALIGNMENT
)));
41 typedef int32_t target_int
__attribute__((aligned(TARGET_INT_ALIGNMENT
)));
42 typedef uint32_t target_uint
__attribute__((aligned(TARGET_INT_ALIGNMENT
)));
43 typedef int64_t target_llong
__attribute__((aligned(TARGET_LLONG_ALIGNMENT
)));
44 typedef uint64_t target_ullong
__attribute__((aligned(TARGET_LLONG_ALIGNMENT
)));
45 /* target_ulong is the type of a virtual address */
46 #if TARGET_LONG_SIZE == 4
47 typedef int32_t target_long
__attribute__((aligned(TARGET_LONG_ALIGNMENT
)));
48 typedef uint32_t target_ulong
__attribute__((aligned(TARGET_LONG_ALIGNMENT
)));
49 #define TARGET_FMT_lx "%08x"
50 #define TARGET_FMT_ld "%d"
51 #define TARGET_FMT_lu "%u"
52 #elif TARGET_LONG_SIZE == 8
53 typedef int64_t target_long
__attribute__((aligned(TARGET_LONG_ALIGNMENT
)));
54 typedef uint64_t target_ulong
__attribute__((aligned(TARGET_LONG_ALIGNMENT
)));
55 #define TARGET_FMT_lx "%016" PRIx64
56 #define TARGET_FMT_ld "%" PRId64
57 #define TARGET_FMT_lu "%" PRIu64
59 #error TARGET_LONG_SIZE undefined
62 #define EXCP_INTERRUPT 0x10000 /* async interruption */
63 #define EXCP_HLT 0x10001 /* hlt instruction reached */
64 #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
65 #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
67 #define TB_JMP_CACHE_BITS 12
68 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
70 /* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
71 addresses on the same page. The top bits are the same. This allows
72 TLB invalidation to quickly clear a subset of the hash table. */
73 #define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2)
74 #define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS)
75 #define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1)
76 #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
78 #if !defined(CONFIG_USER_ONLY)
79 #define CPU_TLB_BITS 8
80 #define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
82 #if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32
83 #define CPU_TLB_ENTRY_BITS 4
85 #define CPU_TLB_ENTRY_BITS 5
88 typedef struct CPUTLBEntry
{
89 /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
90 bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not
92 bit 3 : indicates that the entry is invalid
95 target_ulong addr_read
;
96 target_ulong addr_write
;
97 target_ulong addr_code
;
98 /* Addend to virtual address to get host address. IO accesses
99 use the corresponding iotlb value. */
101 /* padding to get a power of two size */
102 uint8_t dummy
[(1 << CPU_TLB_ENTRY_BITS
) -
103 (sizeof(target_ulong
) * 3 +
104 ((-sizeof(target_ulong
) * 3) & (sizeof(uintptr_t) - 1)) +
108 extern int CPUTLBEntry_wrong_size
[sizeof(CPUTLBEntry
) == (1 << CPU_TLB_ENTRY_BITS
) ? 1 : -1];
110 #define CPU_COMMON_TLB \
111 /* The meaning of the MMU modes is defined in the target code. */ \
112 CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
113 hwaddr iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
114 target_ulong tlb_flush_addr; \
115 target_ulong tlb_flush_mask;
119 #define CPU_COMMON_TLB
124 #ifdef HOST_WORDS_BIGENDIAN
125 typedef struct icount_decr_u16
{
130 typedef struct icount_decr_u16
{
136 typedef struct CPUBreakpoint
{
138 int flags
; /* BP_* */
139 QTAILQ_ENTRY(CPUBreakpoint
) entry
;
142 typedef struct CPUWatchpoint
{
144 target_ulong len_mask
;
145 int flags
; /* BP_* */
146 QTAILQ_ENTRY(CPUWatchpoint
) entry
;
149 #define CPU_TEMP_BUF_NLONGS 128
151 /* soft mmu support */ \
152 /* in order to avoid passing too many arguments to the MMIO \
153 helpers, we store some rarely used information in the CPU \
155 uintptr_t mem_io_pc; /* host pc at which the memory was \
157 target_ulong mem_io_vaddr; /* target virtual addr at which the \
158 memory was accessed */ \
160 struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \
161 /* buffer for temporaries in the code generator */ \
162 long temp_buf[CPU_TEMP_BUF_NLONGS]; \
164 int64_t icount_extra; /* Instructions until next timer event. */ \
165 /* Number of cycles left, with interrupt flag in high bit. \
166 This allows a single read-compare-cbranch-write sequence to test \
167 for both decrementer underflow and exceptions. */ \
170 icount_decr_u16 u16; \
172 uint32_t can_do_io; /* nonzero if memory mapped IO is safe. */ \
174 /* from this point: preserved by CPU reset */ \
175 /* ice debug support */ \
176 QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \
177 int singlestep_enabled; \
179 QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \
180 CPUWatchpoint *watchpoint_hit; \
182 struct GDBRegisterState *gdb_regs; \
184 /* Core interrupt code */ \
185 sigjmp_buf jmp_env; \
186 int exception_index; \
188 CPUArchState *next_cpu; /* next CPU sharing TB cache */ \
192 const char *cpu_model_str;