include/faraday/ftsdmc021.h

   1 /*
   2  * (C) Copyright 2009 Faraday Technology
   3  * Po-Yu Chuang <ratbert@faraday-tech.com>
   4  *
   5  * (C) Copyright 2011 Andes Technology Corp
   6  * Macpaul Lin <macpaul@andestech.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * FTSDMC021 - SDRAM Controller
  25  */
  26 #ifndef __FTSDMC021_H
  27 #define __FTSDMC021_H
  28
  29 #ifndef __ASSEMBLY__
  30 struct ftsdmc021 {
  31         unsigned int    tp1;            /* 0x00 - SDRAM Timing Parameter 1 */
  32         unsigned int    tp2;            /* 0x04 - SDRAM Timing Parameter 2 */
  33         unsigned int    cr1;            /* 0x08 - SDRAM Configuration Reg 1 */
  34         unsigned int    cr2;            /* 0x0c - SDRAM Configuration Reg 2 */
  35         unsigned int    bank0_bsr;      /* 0x10 - Ext. Bank Base/Size Reg 0 */
  36         unsigned int    bank1_bsr;      /* 0x14 - Ext. Bank Base/Size Reg 1 */
  37         unsigned int    bank2_bsr;      /* 0x18 - Ext. Bank Base/Size Reg 2 */
  38         unsigned int    bank3_bsr;      /* 0x1c - Ext. Bank Base/Size Reg 3 */
  39         unsigned int    bank4_bsr;      /* 0x20 - Ext. Bank Base/Size Reg 4 */
  40         unsigned int    bank5_bsr;      /* 0x24 - Ext. Bank Base/Size Reg 5 */
  41         unsigned int    bank6_bsr;      /* 0x28 - Ext. Bank Base/Size Reg 6 */
  42         unsigned int    bank7_bsr;      /* 0x2c - Ext. Bank Base/Size Reg 7 */
  43         unsigned int    ragr;           /* 0x30 - Read Arbitration Group Reg */
  44         unsigned int    frr;            /* 0x34 - Flush Request Register */
  45         unsigned int    ebisr;          /* 0x38 - EBI Support Register  */
  46         unsigned int    rsved[25];      /* 0x3c-0x9c - Reserved         */
  47         unsigned int    crr;            /* 0x100 - Controller Revision Reg */
  48         unsigned int    cfr;            /* 0x104 - Controller Feature Reg */
  49 };
  50 #endif /* __ASSEMBLY__ */
  51
  52 /*
  53  * Timing Parameter 1 Register
  54  */
  55 #define FTSDMC021_TP1_TCL(x)    ((x) & 0x3)             /* CAS Latency */
  56 #define FTSDMC021_TP1_TWR(x)    (((x) & 0x3) << 4)      /* W-Recovery Time */
  57 #define FTSDMC021_TP1_TRF(x)    (((x) & 0xf) << 8)      /* Auto-Refresh Cycle */
  58 #define FTSDMC021_TP1_TRCD(x)   (((x) & 0x7) << 12)     /* RAS-to-CAS Delay */
  59 #define FTSDMC021_TP1_TRP(x)    (((x) & 0xf) << 16)     /* Precharge Cycle */
  60 #define FTSDMC021_TP1_TRAS(x)   (((x) & 0xf) << 20)
  61
  62 /*
  63  * Timing Parameter 2 Register
  64  */
  65 #define FTSDMC021_TP2_REF_INTV(x)       ((x) & 0xffff)  /* Refresh interval */
  66 /* b(16:19) - Initial Refresh Times */
  67 #define FTSDMC021_TP2_INI_REFT(x)       (((x) & 0xf) << 16)
  68 /* b(20:23) - Initial Pre-Charge Times */
  69 #define FTSDMC021_TP2_INI_PREC(x)       (((x) & 0xf) << 20)
  70
  71 /*
  72  * SDRAM Configuration Register 1
  73  */
  74 #define FTSDMC021_CR1_BNKSIZE(x)        ((x) & 0xf)             /* Bank Size  */
  75 #define FTSDMC021_CR1_MBW(x)            (((x) & 0x3) << 4)      /* Bus Width  */
  76 #define FTSDMC021_CR1_DSZ(x)            (((x) & 0x7) << 8)      /* SDRAM Size */
  77 #define FTSDMC021_CR1_DDW(x)            (((x) & 0x3) << 12)     /* Data Width */
  78 /* b(16) MA2T: Double Memory Address Cycle Enable */
  79 #define FTSDMC021_CR1_MA2T(x)           (1 << 16)
  80 /* The value of b(0:3)CR1: 1M-512M, must be power of 2 */
  81 #define FTSDMC021_BANK_SIZE(x)          (ffs(x) - 1)
  82
  83 /*
  84  * Configuration Register 2
  85  */
  86 #define FTSDMC021_CR2_SREF      (1 << 0)        /* Self-Refresh Mode */
  87 #define FTSDMC021_CR2_PWDN      (1 << 1)        /* Power Down Operation Mode */
  88 #define FTSDMC021_CR2_ISMR      (1 << 2)        /* Start Set-Mode-Register */
  89 #define FTSDMC021_CR2_IREF      (1 << 3)        /* Init Refresh Start Flag */
  90 #define FTSDMC021_CR2_IPREC     (1 << 4)        /* Init Pre-Charge Start Flag */
  91 #define FTSDMC021_CR2_REFTYPE   (1 << 5)
  92
  93 /*
  94  * SDRAM External Bank Base/Size Register
  95  */
  96 #define FTSDMC021_BANK_ENABLE           (1 << 12)
  97
  98 /* 12-bit base address of external bank.
  99  * Default value is 0x800.
 100  * The 12-bit equals to the haddr[31:20] of AHB address bus. */
 101 #define FTSDMC021_BANK_BASE(x)          ((x) & 0xfff)
 102
 103 /*
 104  * Read Arbitration Grant Window Register
 105  */
 106 #define FTSDMC021_RAGR_CH1GW(x)         (((x) & 0xff) << 0)
 107 #define FTSDMC021_RAGR_CH2GW(x)         (((x) & 0xff) << 4)
 108 #define FTSDMC021_RAGR_CH3GW(x)         (((x) & 0xff) << 8)
 109 #define FTSDMC021_RAGR_CH4GW(x)         (((x) & 0xff) << 12)
 110 #define FTSDMC021_RAGR_CH5GW(x)         (((x) & 0xff) << 16)
 111 #define FTSDMC021_RAGR_CH6GW(x)         (((x) & 0xff) << 20)
 112 #define FTSDMC021_RAGR_CH7GW(x)         (((x) & 0xff) << 24)
 113 #define FTSDMC021_RAGR_CH8GW(x)         (((x) & 0xff) << 28)
 114
 115 /*
 116  * Flush Request Register
 117  */
 118 #define FTSDMC021_FRR_FLUSHCHN(x)       (((x) & 0x7) << 0)
 119 #define FTSDMC021_FRR_FLUSHCMPLT        (1 << 3)        /* Flush Req Flag */
 120
 121 /*
 122  * External Bus Interface Support Register (EBISR)
 123  */
 124 #define FTSDMC021_EBISR_MR(x)           ((x) & 0xfff)   /* Far-end mode */
 125 #define FTSDMC021_EBISR_PRSMR           (1 << 12)       /* Pre-SMR      */
 126 #define FTSDMC021_EBISR_POPREC          (1 << 13)
 127 #define FTSDMC021_EBISR_POSMR           (1 << 14)       /* Post-SMR     */
 128
 129 /*
 130  * Controller Revision Register (CRR, Read Only)
 131  */
 132 #define FTSDMC021_CRR_REV_VER           (((x) >> 0) & 0xff)
 133 #define FTSDMC021_CRR_MINOR_VER         (((x) >> 8) & 0xff)
 134 #define FTSDMC021_CRR_MAJOR_VER         (((x) >> 16) & 0xff)
 135
 136 /*
 137  * Controller Feature Register (CFR, Read Only)
 138  */
 139 #define FTSDMC021_CFR_EBNK              (((x) >> 0) & 0xf)
 140 #define FTSDMC021_CFR_CHN               (((x) >> 8) & 0xf)
 141 #define FTSDMC021_CFR_EBI               (((x) >> 16) & 0x1)
 142 #define FTSDMC021_CFR_CH1_FDEPTH        (((x) >> 24) & 0x1)
 143 #define FTSDMC021_CFR_CH2_FDEPTH        (((x) >> 25) & 0x1)
 144 #define FTSDMC021_CFR_CH3_FDEPTH        (((x) >> 26) & 0x1)
 145 #define FTSDMC021_CFR_CH4_FDEPTH        (((x) >> 27) & 0x1)
 146 #define FTSDMC021_CFR_CH5_FDEPTH        (((x) >> 28) & 0x1)
 147 #define FTSDMC021_CFR_CH6_FDEPTH        (((x) >> 29) & 0x1)
 148 #define FTSDMC021_CFR_CH7_FDEPTH        (((x) >> 30) & 0x1)
 149 #define FTSDMC021_CFR_CH8_FDEPTH        (((x) >> 31) & 0x1)
 150
 151 #endif  /* __FTSDMC021_H */