1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2008-2014 Freescale Semiconductor, Inc.
9 #include <fsl_ddrc_version.h>
10 #include <fsl_ddr_sdram.h>
11 #include <fsl_ddr_dimm_params.h>
13 #include <common_timing_params.h>
15 #ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
16 /* All controllers are for main memory */
17 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_SYS_NUM_DDR_CTLRS
20 #ifdef CONFIG_SYS_FSL_DDR_LE
21 #define ddr_in32(a) in_le32(a)
22 #define ddr_out32(a, v) out_le32(a, v)
23 #define ddr_setbits32(a, v) setbits_le32(a, v)
24 #define ddr_clrbits32(a, v) clrbits_le32(a, v)
25 #define ddr_clrsetbits32(a, clear, set) clrsetbits_le32(a, clear, set)
27 #define ddr_in32(a) in_be32(a)
28 #define ddr_out32(a, v) out_be32(a, v)
29 #define ddr_setbits32(a, v) setbits_be32(a, v)
30 #define ddr_clrbits32(a, v) clrbits_be32(a, v)
31 #define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set)
34 u32
fsl_ddr_get_version(unsigned int ctrl_num
);
36 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
38 * Bind the main DDR setup driver's generic names
39 * to this specific DDR technology.
42 compute_dimm_parameters(const unsigned int ctrl_num
,
43 const generic_spd_eeprom_t
*spd
,
45 unsigned int dimm_number
)
47 return ddr_compute_dimm_parameters(ctrl_num
, spd
, pdimm
, dimm_number
);
54 * All data structures have to be on the stack
56 #define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR
60 spd_installed_dimms
[CONFIG_SYS_NUM_DDR_CTLRS
][CONFIG_SYS_DIMM_SLOTS_PER_CTLR
];
62 dimm_params
[CONFIG_SYS_NUM_DDR_CTLRS
][CONFIG_SYS_DIMM_SLOTS_PER_CTLR
];
63 memctl_options_t memctl_opts
[CONFIG_SYS_NUM_DDR_CTLRS
];
64 common_timing_params_t common_timing_params
[CONFIG_SYS_NUM_DDR_CTLRS
];
65 fsl_ddr_cfg_regs_t fsl_ddr_config_reg
[CONFIG_SYS_NUM_DDR_CTLRS
];
66 unsigned int first_ctrl
;
67 unsigned int num_ctrls
;
68 unsigned long long mem_base
;
69 unsigned int dimm_slots_per_ctrl
;
70 int (*board_need_mem_reset
)(void);
71 void (*board_mem_reset
)(void);
72 void (*board_mem_de_reset
)(void);
76 #define STEP_GET_SPD (1 << 0)
77 #define STEP_COMPUTE_DIMM_PARMS (1 << 1)
78 #define STEP_COMPUTE_COMMON_PARMS (1 << 2)
79 #define STEP_GATHER_OPTS (1 << 3)
80 #define STEP_ASSIGN_ADDRESSES (1 << 4)
81 #define STEP_COMPUTE_REGS (1 << 5)
82 #define STEP_PROGRAM_REGS (1 << 6)
83 #define STEP_ALL 0xFFF
86 fsl_ddr_compute(fsl_ddr_info_t
*pinfo
, unsigned int start_step
,
87 unsigned int size_only
);
88 const char *step_to_string(unsigned int step
);
90 unsigned int compute_fsl_memctl_config_regs(const unsigned int ctrl_num
,
91 const memctl_options_t
*popts
,
92 fsl_ddr_cfg_regs_t
*ddr
,
93 const common_timing_params_t
*common_dimm
,
94 const dimm_params_t
*dimm_parameters
,
95 unsigned int dbw_capacity_adjust
,
96 unsigned int size_only
);
97 unsigned int compute_lowest_common_dimm_parameters(
98 const unsigned int ctrl_num
,
99 const dimm_params_t
*dimm_params
,
100 common_timing_params_t
*outpdimm
,
101 unsigned int number_of_dimms
);
102 unsigned int populate_memctl_options(const common_timing_params_t
*common_dimm
,
103 memctl_options_t
*popts
,
104 dimm_params_t
*pdimm
,
105 unsigned int ctrl_num
);
106 void check_interleaving_options(fsl_ddr_info_t
*pinfo
);
108 unsigned int mclk_to_picos(const unsigned int ctrl_num
, unsigned int mclk
);
109 unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num
);
110 unsigned int picos_to_mclk(const unsigned int ctrl_num
, unsigned int picos
);
111 void fsl_ddr_set_lawbar(
112 const common_timing_params_t
*memctl_common_params
,
113 unsigned int memctl_interleaved
,
114 unsigned int ctrl_num
);
115 void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl
,
116 unsigned int last_ctrl
);
118 int fsl_ddr_interactive_env_var_exists(void);
119 unsigned long long fsl_ddr_interactive(fsl_ddr_info_t
*pinfo
, int var_is_set
);
120 void fsl_ddr_get_spd(generic_spd_eeprom_t
*ctrl_dimms_spd
,
121 unsigned int ctrl_num
, unsigned int dimm_slots_per_ctrl
);
123 int do_reset(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[]);
124 unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t
*ddr
);
125 void board_add_ram_info(int use_default
);
127 /* processor specific function */
128 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t
*regs
,
129 unsigned int ctrl_num
, int step
);
130 void remove_unused_controllers(fsl_ddr_info_t
*info
);
132 /* board specific function */
133 int fsl_ddr_get_dimm_params(dimm_params_t
*pdimm
,
134 unsigned int controller_number
,
135 unsigned int dimm_number
);
136 void update_spd_address(unsigned int ctrl_num
,
140 void erratum_a009942_check_cpo(void);