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git.ipfire.org Git - people/ms/u-boot.git/blob - include/fsl_ddr_dimm_params.h
2 * Copyright 2008-2014 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
9 #ifndef DDR2_DIMM_PARAMS_H
10 #define DDR2_DIMM_PARAMS_H
12 #define EDC_DATA_PARITY 1
14 #define EDC_AC_PARITY 4
16 /* Parameters for a DDR dimm computed from the SPD */
17 typedef struct dimm_params_s
{
19 /* DIMM organization parameters */
20 char mpart
[19]; /* guaranteed null terminated */
23 unsigned long long rank_density
;
24 unsigned long long capacity
;
25 unsigned int data_width
;
26 unsigned int primary_sdram_width
;
27 unsigned int ec_sdram_width
;
28 unsigned int registered_dimm
;
29 unsigned int device_width
; /* x4, x8, x16 components */
31 /* SDRAM device parameters */
32 unsigned int n_row_addr
;
33 unsigned int n_col_addr
;
34 unsigned int edc_config
; /* 0 = none, 1 = parity, 2 = ECC */
35 #ifdef CONFIG_SYS_FSL_DDR4
36 unsigned int bank_addr_bits
;
37 unsigned int bank_group_bits
;
39 unsigned int n_banks_per_sdram_device
;
41 unsigned int burst_lengths_bitmask
; /* BL=4 bit 2, BL=8 = bit 3 */
42 unsigned int row_density
;
44 /* used in computing base address of DIMMs */
45 unsigned long long base_address
;
47 unsigned int mirrored_dimm
; /* only for ddr3 */
49 /* DIMM timing parameters */
51 int mtb_ps
; /* medium timebase ps */
52 int ftb_10th_ps
; /* fine timebase, in 1/10 ps */
53 int taa_ps
; /* minimum CAS latency time */
54 int tfaw_ps
; /* four active window delay */
58 * The range for these are 1000-10000 so a short should be sufficient
61 int tckmin_x_minus_1_ps
;
62 int tckmin_x_minus_2_ps
;
65 /* SPD-defined CAS latencies */
66 unsigned int caslat_x
;
67 unsigned int caslat_x_minus_1
;
68 unsigned int caslat_x_minus_2
;
70 unsigned int caslat_lowest_derated
; /* Derated CAS latency */
72 /* basic timing parameters */
77 #ifdef CONFIG_SYS_FSL_DDR4
85 int twr_ps
; /* maximum = 63750 ps */
86 int trfc_ps
; /* max = 255 ns + 256 ns + .75 ns
88 int trrd_ps
; /* maximum = 63750 ps */
89 int twtr_ps
; /* maximum = 63750 ps */
90 int trtp_ps
; /* byte 38, spd->trtp */
93 int trc_ps
; /* maximum = 254 ns + .75 ns = 254750 ps */
98 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
99 int tis_ps
; /* byte 32, spd->ca_setup */
100 int tih_ps
; /* byte 33, spd->ca_hold */
101 int tds_ps
; /* byte 34, spd->data_setup */
102 int tdh_ps
; /* byte 35, spd->data_hold */
103 int tdqsq_max_ps
; /* byte 44, spd->tdqsq */
104 int tqhs_ps
; /* byte 45, spd->tqhs */
108 unsigned char rcw
[16]; /* Register Control Word 0-15 */
109 #ifdef CONFIG_SYS_FSL_DDR4
110 unsigned int dq_mapping
[18];
111 unsigned int dq_mapping_ors
;
115 extern unsigned int ddr_compute_dimm_parameters(
116 const generic_spd_eeprom_t
*spd
,
117 dimm_params_t
*pdimm
,
118 unsigned int dimm_number
);