2 * Copyright 2008-2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0
7 #ifndef FSL_DDR_MEMCTL_H
8 #define FSL_DDR_MEMCTL_H
11 * Pick a basic DDR Technology.
14 #include <fsl_ddrc_version.h>
16 #define SDRAM_TYPE_DDR1 2
17 #define SDRAM_TYPE_DDR2 3
18 #define SDRAM_TYPE_LPDDR1 6
19 #define SDRAM_TYPE_DDR3 7
20 #define SDRAM_TYPE_DDR4 5
22 #define DDR_BL4 4 /* burst length 4 */
23 #define DDR_BC4 DDR_BL4 /* burst chop for ddr3 */
24 #define DDR_OTF 6 /* on-the-fly BC4 and BL8 */
25 #define DDR_BL8 8 /* burst length 8 */
27 #define DDR3_RTT_OFF 0
28 #define DDR3_RTT_60_OHM 1 /* RTT_Nom = RZQ/4 */
29 #define DDR3_RTT_120_OHM 2 /* RTT_Nom = RZQ/2 */
30 #define DDR3_RTT_40_OHM 3 /* RTT_Nom = RZQ/6 */
31 #define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */
32 #define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */
34 #define DDR4_RTT_OFF 0
35 #define DDR4_RTT_60_OHM 1 /* RZQ/4 */
36 #define DDR4_RTT_120_OHM 2 /* RZQ/2 */
37 #define DDR4_RTT_40_OHM 3 /* RZQ/6 */
38 #define DDR4_RTT_240_OHM 4 /* RZQ/1 */
39 #define DDR4_RTT_48_OHM 5 /* RZQ/5 */
40 #define DDR4_RTT_80_OHM 6 /* RZQ/3 */
41 #define DDR4_RTT_34_OHM 7 /* RZQ/7 */
43 #define DDR2_RTT_OFF 0
44 #define DDR2_RTT_75_OHM 1
45 #define DDR2_RTT_150_OHM 2
46 #define DDR2_RTT_50_OHM 3
48 #if defined(CONFIG_SYS_FSL_DDR1)
49 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1)
50 typedef ddr1_spd_eeprom_t generic_spd_eeprom_t
;
51 #ifndef CONFIG_FSL_SDRAM_TYPE
52 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1
54 #elif defined(CONFIG_SYS_FSL_DDR2)
55 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3)
56 typedef ddr2_spd_eeprom_t generic_spd_eeprom_t
;
57 #ifndef CONFIG_FSL_SDRAM_TYPE
58 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2
60 #elif defined(CONFIG_SYS_FSL_DDR3)
61 typedef ddr3_spd_eeprom_t generic_spd_eeprom_t
;
62 #ifndef CONFIG_FSL_SDRAM_TYPE
63 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3
65 #elif defined(CONFIG_SYS_FSL_DDR4)
66 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */
67 typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t
;
68 #ifndef CONFIG_FSL_SDRAM_TYPE
69 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR4
71 #endif /* #if defined(CONFIG_SYS_FSL_DDR1) */
73 #define FSL_DDR_ODT_NEVER 0x0
74 #define FSL_DDR_ODT_CS 0x1
75 #define FSL_DDR_ODT_ALL_OTHER_CS 0x2
76 #define FSL_DDR_ODT_OTHER_DIMM 0x3
77 #define FSL_DDR_ODT_ALL 0x4
78 #define FSL_DDR_ODT_SAME_DIMM 0x5
79 #define FSL_DDR_ODT_CS_AND_OTHER_DIMM 0x6
80 #define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7
82 /* define bank(chip select) interleaving mode */
83 #define FSL_DDR_CS0_CS1 0x40
84 #define FSL_DDR_CS2_CS3 0x20
85 #define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3)
86 #define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04)
88 /* define memory controller interleaving mode */
89 #define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0
90 #define FSL_DDR_PAGE_INTERLEAVING 0x1
91 #define FSL_DDR_BANK_INTERLEAVING 0x2
92 #define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
93 #define FSL_DDR_256B_INTERLEAVING 0x8
94 #define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA
95 #define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC
96 #define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD
97 /* placeholder for 4-way interleaving */
98 #define FSL_DDR_4WAY_1KB_INTERLEAVING 0x1A
99 #define FSL_DDR_4WAY_4KB_INTERLEAVING 0x1C
100 #define FSL_DDR_4WAY_8KB_INTERLEAVING 0x1D
102 #define SDRAM_CS_CONFIG_EN 0x80000000
104 /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
106 #define SDRAM_CFG_MEM_EN 0x80000000
107 #define SDRAM_CFG_SREN 0x40000000
108 #define SDRAM_CFG_ECC_EN 0x20000000
109 #define SDRAM_CFG_RD_EN 0x10000000
110 #define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
111 #define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
112 #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
113 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
114 #define SDRAM_CFG_DYN_PWR 0x00200000
115 #define SDRAM_CFG_DBW_MASK 0x00180000
116 #define SDRAM_CFG_DBW_SHIFT 19
117 #define SDRAM_CFG_32_BE 0x00080000
118 #define SDRAM_CFG_16_BE 0x00100000
119 #define SDRAM_CFG_8_BE 0x00040000
120 #define SDRAM_CFG_NCAP 0x00020000
121 #define SDRAM_CFG_2T_EN 0x00008000
122 #define SDRAM_CFG_BI 0x00000001
124 #define SDRAM_CFG2_FRC_SR 0x80000000
125 #define SDRAM_CFG2_D_INIT 0x00000010
126 #define SDRAM_CFG2_ODT_CFG_MASK 0x00600000
127 #define SDRAM_CFG2_ODT_NEVER 0
128 #define SDRAM_CFG2_ODT_ONLY_WRITE 1
129 #define SDRAM_CFG2_ODT_ONLY_READ 2
130 #define SDRAM_CFG2_ODT_ALWAYS 3
132 #define TIMING_CFG_2_CPO_MASK 0x0F800000
134 #if defined(CONFIG_SYS_FSL_DDR_VER) && \
135 (CONFIG_SYS_FSL_DDR_VER > FSL_DDR_VER_4_4)
136 #define RD_TO_PRE_MASK 0xf
137 #define RD_TO_PRE_SHIFT 13
138 #define WR_DATA_DELAY_MASK 0xf
139 #define WR_DATA_DELAY_SHIFT 9
141 #define RD_TO_PRE_MASK 0x7
142 #define RD_TO_PRE_SHIFT 13
143 #define WR_DATA_DELAY_MASK 0x7
144 #define WR_DATA_DELAY_SHIFT 10
148 #define MD_CNTL_MD_EN 0x80000000
149 #define MD_CNTL_CS_SEL_CS0 0x00000000
150 #define MD_CNTL_CS_SEL_CS1 0x10000000
151 #define MD_CNTL_CS_SEL_CS2 0x20000000
152 #define MD_CNTL_CS_SEL_CS3 0x30000000
153 #define MD_CNTL_CS_SEL_CS0_CS1 0x40000000
154 #define MD_CNTL_CS_SEL_CS2_CS3 0x50000000
155 #define MD_CNTL_MD_SEL_MR 0x00000000
156 #define MD_CNTL_MD_SEL_EMR 0x01000000
157 #define MD_CNTL_MD_SEL_EMR2 0x02000000
158 #define MD_CNTL_MD_SEL_EMR3 0x03000000
159 #define MD_CNTL_SET_REF 0x00800000
160 #define MD_CNTL_SET_PRE 0x00400000
161 #define MD_CNTL_CKE_CNTL_LOW 0x00100000
162 #define MD_CNTL_CKE_CNTL_HIGH 0x00200000
163 #define MD_CNTL_WRCW 0x00080000
164 #define MD_CNTL_MD_VALUE(x) (x & 0x0000FFFF)
165 #define MD_CNTL_CS_SEL(x) (((x) & 0x7) << 28)
166 #define MD_CNTL_MD_SEL(x) (((x) & 0xf) << 24)
169 #define DDR_CDR1_DHC_EN 0x80000000
170 #define DDR_CDR1_ODT_SHIFT 17
171 #define DDR_CDR1_ODT_MASK 0x6
172 #define DDR_CDR2_ODT_MASK 0x1
173 #define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
174 #define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
175 #define DDR_CDR2_VREF_OVRD(x) (0x00008080 | ((((x) - 37) & 0x3F) << 8))
176 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
177 #define DDR_CDR2_VREF_RANGE_2 0x00000040
179 #if (defined(CONFIG_SYS_FSL_DDR_VER) && \
180 (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
181 #ifdef CONFIG_SYS_FSL_DDR3L
182 #define DDR_CDR_ODT_OFF 0x0
183 #define DDR_CDR_ODT_120ohm 0x1
184 #define DDR_CDR_ODT_200ohm 0x2
185 #define DDR_CDR_ODT_75ohm 0x3
186 #define DDR_CDR_ODT_60ohm 0x5
187 #define DDR_CDR_ODT_46ohm 0x7
188 #elif defined(CONFIG_SYS_FSL_DDR4)
189 #define DDR_CDR_ODT_OFF 0x0
190 #define DDR_CDR_ODT_100ohm 0x1
191 #define DDR_CDR_ODT_120OHM 0x2
192 #define DDR_CDR_ODT_80ohm 0x3
193 #define DDR_CDR_ODT_60ohm 0x4
194 #define DDR_CDR_ODT_40ohm 0x5
195 #define DDR_CDR_ODT_50ohm 0x6
196 #define DDR_CDR_ODT_30ohm 0x7
198 #define DDR_CDR_ODT_OFF 0x0
199 #define DDR_CDR_ODT_120ohm 0x1
200 #define DDR_CDR_ODT_180ohm 0x2
201 #define DDR_CDR_ODT_75ohm 0x3
202 #define DDR_CDR_ODT_110ohm 0x4
203 #define DDR_CDR_ODT_60hm 0x5
204 #define DDR_CDR_ODT_70ohm 0x6
205 #define DDR_CDR_ODT_47ohm 0x7
208 #define DDR_CDR_ODT_75ohm 0x0
209 #define DDR_CDR_ODT_55ohm 0x1
210 #define DDR_CDR_ODT_60ohm 0x2
211 #define DDR_CDR_ODT_50ohm 0x3
212 #define DDR_CDR_ODT_150ohm 0x4
213 #define DDR_CDR_ODT_43ohm 0x5
214 #define DDR_CDR_ODT_120ohm 0x6
217 #define DDR_INIT_ADDR_EXT_UIA (1 << 31)
219 /* Record of register values computed */
220 typedef struct fsl_ddr_cfg_regs_s
{
224 unsigned int config_2
;
225 } cs
[CONFIG_CHIP_SELECTS_PER_CTRL
];
226 unsigned int timing_cfg_3
;
227 unsigned int timing_cfg_0
;
228 unsigned int timing_cfg_1
;
229 unsigned int timing_cfg_2
;
230 unsigned int ddr_sdram_cfg
;
231 unsigned int ddr_sdram_cfg_2
;
232 unsigned int ddr_sdram_cfg_3
;
233 unsigned int ddr_sdram_mode
;
234 unsigned int ddr_sdram_mode_2
;
235 unsigned int ddr_sdram_mode_3
;
236 unsigned int ddr_sdram_mode_4
;
237 unsigned int ddr_sdram_mode_5
;
238 unsigned int ddr_sdram_mode_6
;
239 unsigned int ddr_sdram_mode_7
;
240 unsigned int ddr_sdram_mode_8
;
241 unsigned int ddr_sdram_mode_9
;
242 unsigned int ddr_sdram_mode_10
;
243 unsigned int ddr_sdram_mode_11
;
244 unsigned int ddr_sdram_mode_12
;
245 unsigned int ddr_sdram_mode_13
;
246 unsigned int ddr_sdram_mode_14
;
247 unsigned int ddr_sdram_mode_15
;
248 unsigned int ddr_sdram_mode_16
;
249 unsigned int ddr_sdram_md_cntl
;
250 unsigned int ddr_sdram_interval
;
251 unsigned int ddr_data_init
;
252 unsigned int ddr_sdram_clk_cntl
;
253 unsigned int ddr_init_addr
;
254 unsigned int ddr_init_ext_addr
;
255 unsigned int timing_cfg_4
;
256 unsigned int timing_cfg_5
;
257 unsigned int timing_cfg_6
;
258 unsigned int timing_cfg_7
;
259 unsigned int timing_cfg_8
;
260 unsigned int timing_cfg_9
;
261 unsigned int ddr_zq_cntl
;
262 unsigned int ddr_wrlvl_cntl
;
263 unsigned int ddr_wrlvl_cntl_2
;
264 unsigned int ddr_wrlvl_cntl_3
;
265 unsigned int ddr_sr_cntr
;
266 unsigned int ddr_sdram_rcw_1
;
267 unsigned int ddr_sdram_rcw_2
;
268 unsigned int ddr_sdram_rcw_3
;
269 unsigned int ddr_sdram_rcw_4
;
270 unsigned int ddr_sdram_rcw_5
;
271 unsigned int ddr_sdram_rcw_6
;
272 unsigned int dq_map_0
;
273 unsigned int dq_map_1
;
274 unsigned int dq_map_2
;
275 unsigned int dq_map_3
;
276 unsigned int ddr_eor
;
277 unsigned int ddr_cdr1
;
278 unsigned int ddr_cdr2
;
279 unsigned int err_disable
;
280 unsigned int err_int_en
;
281 unsigned int debug
[32];
282 } fsl_ddr_cfg_regs_t
;
284 typedef struct memctl_options_partial_s
{
285 unsigned int all_dimms_ecc_capable
;
286 unsigned int all_dimms_tckmax_ps
;
287 unsigned int all_dimms_burst_lengths_bitmask
;
288 unsigned int all_dimms_registered
;
289 unsigned int all_dimms_unbuffered
;
290 /* unsigned int lowest_common_spd_caslat; */
291 unsigned int all_dimms_minimum_trcd_ps
;
292 } memctl_options_partial_t
;
294 #define DDR_DATA_BUS_WIDTH_64 0
295 #define DDR_DATA_BUS_WIDTH_32 1
296 #define DDR_DATA_BUS_WIDTH_16 2
297 #define DDR_CSWL_CS0 0x04000001
299 * Generalized parameters for memory controller configuration,
300 * might be a little specific to the FSL memory controller
302 typedef struct memctl_options_s
{
304 * Memory organization parameters
306 * if DIMM is present in the system
307 * where DIMMs are with respect to chip select
308 * where chip selects are with respect to memory boundaries
310 unsigned int registered_dimm_en
; /* use registered DIMM support */
312 /* Options local to a Chip Select */
313 struct cs_local_opts_s
{
314 unsigned int auto_precharge
;
315 unsigned int odt_rd_cfg
;
316 unsigned int odt_wr_cfg
;
317 unsigned int odt_rtt_norm
;
318 unsigned int odt_rtt_wr
;
319 } cs_local_opts
[CONFIG_CHIP_SELECTS_PER_CTRL
];
321 /* Special configurations for chip select */
322 unsigned int memctl_interleaving
;
323 unsigned int memctl_interleaving_mode
;
324 unsigned int ba_intlv_ctl
;
325 unsigned int addr_hash
;
327 /* Operational mode parameters */
328 unsigned int ecc_mode
; /* Use ECC? */
329 /* Initialize ECC using memory controller? */
330 unsigned int ecc_init_using_memctl
;
331 unsigned int dqs_config
; /* Use DQS? maybe only with DDR2? */
332 /* SREN - self-refresh during sleep */
333 unsigned int self_refresh_in_sleep
;
334 /* SR_IE - Self-refresh interrupt enable */
335 unsigned int self_refresh_interrupt_en
;
336 unsigned int dynamic_power
; /* DYN_PWR */
337 /* memory data width to use (16-bit, 32-bit, 64-bit) */
338 unsigned int data_bus_width
;
339 unsigned int burst_length
; /* BL4, OTF and BL8 */
340 /* On-The-Fly Burst Chop enable */
341 unsigned int otf_burst_chop_en
;
342 /* mirrior DIMMs for DDR3 */
343 unsigned int mirrored_dimm
;
344 unsigned int quad_rank_present
;
345 unsigned int ap_en
; /* address parity enable for RDIMM */
346 unsigned int x4_en
; /* enable x4 devices */
348 /* Global Timing Parameters */
349 unsigned int cas_latency_override
;
350 unsigned int cas_latency_override_value
;
351 unsigned int use_derated_caslat
;
352 unsigned int additive_latency_override
;
353 unsigned int additive_latency_override_value
;
355 unsigned int clk_adjust
; /* */
356 unsigned int cpo_override
;
357 unsigned int write_data_delay
; /* DQS adjust */
359 unsigned int cswl_override
;
360 unsigned int wrlvl_override
;
361 unsigned int wrlvl_sample
; /* Write leveling */
362 unsigned int wrlvl_start
;
363 unsigned int wrlvl_ctl_2
;
364 unsigned int wrlvl_ctl_3
;
366 unsigned int half_strength_driver_enable
;
367 unsigned int twot_en
;
368 unsigned int threet_en
;
369 unsigned int bstopre
;
370 unsigned int tfaw_window_four_activates_ps
; /* tFAW -- FOUR_ACT */
373 unsigned int rtt_override
; /* rtt_override enable */
374 unsigned int rtt_override_value
; /* that is Rtt_Nom for DDR3 */
375 unsigned int rtt_wr_override_value
; /* this is Rtt_WR for DDR3 */
377 /* Automatic self refresh */
378 unsigned int auto_self_refresh_en
;
383 unsigned int wrlvl_en
;
384 /* RCW override for RDIMM */
385 unsigned int rcw_override
;
388 /* control register 1 */
389 unsigned int ddr_cdr1
;
390 unsigned int ddr_cdr2
;
392 unsigned int trwt_override
;
393 unsigned int trwt
; /* read-to-write turnaround */
396 phys_size_t
fsl_ddr_sdram(void);
397 phys_size_t
fsl_ddr_sdram_size(void);
398 phys_size_t
fsl_other_ddr_sdram(unsigned long long base
,
399 unsigned int first_ctrl
,
400 unsigned int num_ctrls
,
401 unsigned int dimm_slots_per_ctrl
,
402 int (*board_need_reset
)(void),
403 void (*board_reset
)(void),
404 void (*board_de_reset
)(void));
405 extern int fsl_use_spd(void);
406 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t
*regs
,
407 unsigned int ctrl_num
, int step
);
408 u32
fsl_ddr_get_intl3r(void);
409 void print_ddr_info(unsigned int start_ctrl
);
411 static void __board_assert_mem_reset(void)
415 static void __board_deassert_mem_reset(void)
419 void board_assert_mem_reset(void)
420 __attribute__((weak
, alias("__board_assert_mem_reset")));
422 void board_deassert_mem_reset(void)
423 __attribute__((weak
, alias("__board_deassert_mem_reset")));
425 static int __board_need_mem_reset(void)
430 int board_need_mem_reset(void)
431 __attribute__((weak
, alias("__board_need_mem_reset")));
433 #if defined(CONFIG_DEEP_SLEEP)
434 void board_mem_sleep_setup(void);
435 bool is_warm_boot(void);
436 int fsl_dp_resume(void);
440 * The 85xx boards have a common prototype for fixed_sdram so put the
443 #ifdef CONFIG_MPC85xx
444 extern phys_size_t
fixed_sdram(void);
447 #if defined(CONFIG_DDR_ECC)
448 extern void ddr_enable_ecc(unsigned int dram_size
);
452 typedef struct fixed_ddr_parm
{
455 fsl_ddr_cfg_regs_t
*ddr_settings
;