1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * MPC85xx Internal Memory Map
5 * Copyright 2010-2011 Freescale Semiconductor, Inc.
11 #include <asm/types.h>
13 typedef struct fm_bmi_common
{
14 u32 fmbm_init
; /* BMI initialization */
15 u32 fmbm_cfg1
; /* BMI configuration1 */
16 u32 fmbm_cfg2
; /* BMI configuration2 */
18 u32 fmbm_ievr
; /* interrupt event register */
19 u32 fmbm_ier
; /* interrupt enable register */
20 u32 fmbm_ifr
; /* interrupt force register */
22 u32 fmbm_arb
[0x8]; /* BMI arbitration */
24 u32 fmbm_gde
; /* global debug enable */
25 u32 fmbm_pp
[0x3f]; /* BMI port parameters */
27 u32 fmbm_pfs
[0x3f]; /* BMI port FIFO size */
29 u32 fmbm_ppid
[0x3f];/* port partition ID */
32 typedef struct fm_qmi_common
{
33 u32 fmqm_gc
; /* general configuration register */
35 u32 fmqm_eie
; /* error interrupt event register */
36 u32 fmqm_eien
; /* error interrupt enable register */
37 u32 fmqm_eif
; /* error interrupt force register */
38 u32 fmqm_ie
; /* interrupt event register */
39 u32 fmqm_ien
; /* interrupt enable register */
40 u32 fmqm_if
; /* interrupt force register */
41 u32 fmqm_gs
; /* global status register */
42 u32 fmqm_ts
; /* task status register */
43 u32 fmqm_etfc
; /* enqueue total frame counter */
44 u32 fmqm_dtfc
; /* dequeue total frame counter */
45 u32 fmqm_dc0
; /* dequeue counter 0 */
46 u32 fmqm_dc1
; /* dequeue counter 1 */
47 u32 fmqm_dc2
; /* dequeue counter 2 */
48 u32 fmqm_dc3
; /* dequeue counter 3 */
49 u32 fmqm_dfnoc
; /* dequeue FQID not override counter */
50 u32 fmqm_dfcc
; /* dequeue FQID from context counter */
51 u32 fmqm_dffc
; /* dequeue FQID from FD counter */
52 u32 fmqm_dcc
; /* dequeue confirm counter */
54 u32 fmqm_dtrc
; /* debug trap configuration register */
55 u32 fmqm_efddd
; /* enqueue frame descriptor dynamic debug */
57 u32 res4
[0xdc]; /* missing debug regs */
60 typedef struct fm_bmi
{
64 typedef struct fm_qmi
{
68 struct fm_bmi_rx_port
{
69 u32 fmbm_rcfg
; /* Rx configuration */
70 u32 fmbm_rst
; /* Rx status */
71 u32 fmbm_rda
; /* Rx DMA attributes */
72 u32 fmbm_rfp
; /* Rx FIFO parameters */
73 u32 fmbm_rfed
; /* Rx frame end data */
74 u32 fmbm_ricp
; /* Rx internal context parameters */
75 u32 fmbm_rim
; /* Rx internal margins */
76 u32 fmbm_rebm
; /* Rx external buffer margins */
77 u32 fmbm_rfne
; /* Rx frame next engine */
78 u32 fmbm_rfca
; /* Rx frame command attributes */
79 u32 fmbm_rfpne
; /* Rx frame parser next engine */
80 u32 fmbm_rpso
; /* Rx parse start offset */
81 u32 fmbm_rpp
; /* Rx policer profile */
82 u32 fmbm_rccb
; /* Rx coarse classification base */
84 u32 fmbm_rprai
[0x8]; /* Rx parse results array Initialization */
85 u32 fmbm_rfqid
; /* Rx frame queue ID */
86 u32 fmbm_refqid
; /* Rx error frame queue ID */
87 u32 fmbm_rfsdm
; /* Rx frame status discard mask */
88 u32 fmbm_rfsem
; /* Rx frame status error mask */
89 u32 fmbm_rfene
; /* Rx frame enqueue next engine */
91 u32 fmbm_ebmpi
[0x8]; /* buffer manager pool information */
92 u32 fmbm_acnt
[0x8]; /* allocate counter */
94 u32 fmbm_cgm
[0x8]; /* congestion group map */
95 u32 fmbm_mpd
; /* BMan pool depletion */
97 u32 fmbm_rstc
; /* Rx statistics counters */
98 u32 fmbm_rfrc
; /* Rx frame counters */
99 u32 fmbm_rfbc
; /* Rx bad frames counter */
100 u32 fmbm_rlfc
; /* Rx large frames counter */
101 u32 fmbm_rffc
; /* Rx filter frames counter */
102 u32 fmbm_rfdc
; /* Rx frame discard counter */
103 u32 fmbm_rfldec
; /* Rx frames list DMA error counter */
104 u32 fmbm_rodc
; /* Rx out of buffers discard counter */
105 u32 fmbm_rbdc
; /* Rx buffers deallocate counter */
107 u32 fmbm_rpc
; /* Rx performance counters */
108 u32 fmbm_rpcp
; /* Rx performance count parameters */
109 u32 fmbm_rccn
; /* Rx cycle counter */
110 u32 fmbm_rtuc
; /* Rx tasks utilization counter */
111 u32 fmbm_rrquc
; /* Rx receive queue utilization counter */
112 u32 fmbm_rduc
; /* Rx DMA utilization counter */
113 u32 fmbm_rfuc
; /* Rx FIFO utilization counter */
114 u32 fmbm_rpac
; /* Rx pause activation counter */
116 u32 fmbm_rdbg
; /* Rx debug configuration */
119 /* FMBM_RCFG - Rx configuration */
120 #define FMBM_RCFG_EN 0x80000000 /* port is enabled to receive data */
121 #define FMBM_RCFG_FDOVR 0x02000000 /* frame discard override */
122 #define FMBM_RCFG_IM 0x01000000 /* independent mode */
124 /* FMBM_RST - Rx status */
125 #define FMBM_RST_BSY 0x80000000 /* Rx port is busy */
127 /* FMBM_RFCA - Rx frame command attributes */
128 #define FMBM_RFCA_ORDER 0x80000000
129 #define FMBM_RFCA_MR_MASK 0x003f0000
130 #define FMBM_RFCA_MR(x) ((x << 16) & FMBM_RFCA_MR_MASK)
132 /* FMBM_RSTC - Rx statistics */
133 #define FMBM_RSTC_EN 0x80000000 /* statistics counters enable */
135 struct fm_bmi_tx_port
{
136 u32 fmbm_tcfg
; /* Tx configuration */
137 u32 fmbm_tst
; /* Tx status */
138 u32 fmbm_tda
; /* Tx DMA attributes */
139 u32 fmbm_tfp
; /* Tx FIFO parameters */
140 u32 fmbm_tfed
; /* Tx frame end data */
141 u32 fmbm_ticp
; /* Tx internal context parameters */
142 u32 fmbm_tfne
; /* Tx frame next engine */
143 u32 fmbm_tfca
; /* Tx frame command attributes */
144 u32 fmbm_tcfqid
;/* Tx confirmation frame queue ID */
145 u32 fmbm_tfeqid
;/* Tx error frame queue ID */
146 u32 fmbm_tfene
; /* Tx frame enqueue next engine */
147 u32 fmbm_trlmts
;/* Tx rate limiter scale */
148 u32 fmbm_trlmt
; /* Tx rate limiter */
150 u32 fmbm_tstc
; /* Tx statistics counters */
151 u32 fmbm_tfrc
; /* Tx frame counter */
152 u32 fmbm_tfdc
; /* Tx frames discard counter */
153 u32 fmbm_tfledc
;/* Tx frame length error discard counter */
154 u32 fmbm_tfufdc
;/* Tx frame unsupported format discard counter */
155 u32 fmbm_tbdc
; /* Tx buffers deallocate counter */
157 u32 fmbm_tpc
; /* Tx performance counters */
158 u32 fmbm_tpcp
; /* Tx performance count parameters */
159 u32 fmbm_tccn
; /* Tx cycle counter */
160 u32 fmbm_ttuc
; /* Tx tasks utilization counter */
161 u32 fmbm_ttcquc
;/* Tx transmit confirm queue utilization counter */
162 u32 fmbm_tduc
; /* Tx DMA utilization counter */
163 u32 fmbm_tfuc
; /* Tx FIFO utilization counter */
165 u32 fmbm_tdcfg
; /* Tx debug configuration */
168 /* FMBM_TCFG - Tx configuration */
169 #define FMBM_TCFG_EN 0x80000000 /* port is enabled to transmit data */
170 #define FMBM_TCFG_IM 0x01000000 /* independent mode enable */
172 /* FMBM_TST - Tx status */
173 #define FMBM_TST_BSY 0x80000000 /* Tx port is busy */
175 /* FMBM_TFCA - Tx frame command attributes */
176 #define FMBM_TFCA_ORDER 0x80000000
177 #define FMBM_TFCA_MR_MASK 0x003f0000
178 #define FMBM_TFCA_MR(x) ((x << 16) & FMBM_TFCA_MR_MASK)
180 /* FMBM_TSTC - Tx statistics counters */
181 #define FMBM_TSTC_EN 0x80000000
183 /* FMBM_INIT - BMI initialization register */
184 #define FMBM_INIT_START 0x80000000 /* init internal buffers */
186 /* FMBM_CFG1 - BMI configuration 1 */
187 #define FMBM_CFG1_FBPS_MASK 0x03ff0000 /* Free buffer pool size */
188 #define FMBM_CFG1_FBPS_SHIFT 16
189 #define FMBM_CFG1_FBPO_MASK 0x000003ff /* Free buffer pool offset */
191 /* FMBM_IEVR - interrupt event */
192 #define FMBM_IEVR_PEC 0x80000000 /* pipeline table ECC err detected */
193 #define FMBM_IEVR_LEC 0x40000000 /* linked list RAM ECC error */
194 #define FMBM_IEVR_SEC 0x20000000 /* statistics count RAM ECC error */
195 #define FMBM_IEVR_CLEAR_ALL (FMBM_IEVR_PEC | FMBM_IEVR_LEC | FMBM_IEVR_SEC)
197 /* FMBM_IER - interrupt enable */
198 #define FMBM_IER_PECE 0x80000000 /* PEC interrupt enable */
199 #define FMBM_IER_LECE 0x40000000 /* LEC interrupt enable */
200 #define FMBM_IER_SECE 0x20000000 /* SEC interrupt enable */
202 #define FMBM_IER_DISABLE_ALL 0x00000000
204 /* FMBM_PP - BMI Port Parameters */
205 #define FMBM_PP_MXT_MASK 0x3f000000 /* Max # tasks */
206 #define FMBM_PP_MXT(x) (((x-1) << 24) & FMBM_PP_MXT_MASK)
207 #define FMBM_PP_MXD_MASK 0x00000f00 /* Max DMA */
208 #define FMBM_PP_MXD(x) (((x-1) << 8) & FMBM_PP_MXD_MASK)
210 /* FMBM_PFS - BMI Port FIFO Size */
211 #define FMBM_PFS_IFSZ_MASK 0x000003ff /* Internal Fifo Size */
212 #define FMBM_PFS_IFSZ(x) (x & FMBM_PFS_IFSZ_MASK)
214 /* FMQM_GC - global configuration */
215 #define FMQM_GC_ENQ_EN 0x80000000 /* enqueue enable */
216 #define FMQM_GC_DEQ_EN 0x40000000 /* dequeue enable */
217 #define FMQM_GC_STEN 0x10000000 /* enable global stat counters */
218 #define FMQM_GC_ENQ_THR_MASK 0x00003f00 /* max number of enqueue Tnum */
219 #define FMQM_GC_ENQ(x) ((x << 8) & FMQM_GC_ENQ_THR_MAS)
220 #define FMQM_GC_DEQ_THR_MASK 0x0000003f /* max number of dequeue Tnum */
221 #define FMQM_GC_DEQ(x) (x & FMQM_GC_DEQ_THR_MASK)
223 /* FMQM_EIE - error interrupt event register */
224 #define FMQM_EIE_DEE 0x80000000 /* double-bit ECC error */
225 #define FMQM_EIE_DFUPE 0x40000000 /* dequeue from unknown PortID */
226 #define FMQM_EIE_CLEAR_ALL (FMQM_EIE_DEE | FMQM_EIE_DFUPE)
228 /* FMQM_EIEN - error interrupt enable register */
229 #define FMQM_EIEN_DEEN 0x80000000 /* double-bit ECC error */
230 #define FMQM_EIEN_DFUPEN 0x40000000 /* dequeue from unknown PortID */
231 #define FMQM_EIEN_DISABLE_ALL 0x00000000
233 /* FMQM_IE - interrupt event register */
234 #define FMQM_IE_SEE 0x80000000 /* single-bit ECC error detected */
235 #define FMQM_IE_CLEAR_ALL FMQM_IE_SEE
237 /* FMQM_IEN - interrupt enable register */
238 #define FMQM_IEN_SEE 0x80000000 /* single-bit ECC err IRQ enable */
239 #define FMQM_IEN_DISABLE_ALL 0x00000000
241 /* NIA - next invoked action */
242 #define NIA_ENG_RISC 0x00000000
243 #define NIA_ENG_MASK 0x007c0000
246 #define NIA_RISC_AC_CC 0x00000006
247 #define NIA_RISC_AC_IM_TX 0x00000008 /* independent mode Tx */
248 #define NIA_RISC_AC_IM_RX 0x0000000a /* independent mode Rx */
249 #define NIA_RISC_AC_HC 0x0000000c
251 typedef struct fm_parser
{
255 typedef struct fm_policer
{
259 typedef struct fm_keygen
{
263 typedef struct fm_dma
{
264 u32 fmdmsr
; /* status register */
265 u32 fmdmmr
; /* mode register */
266 u32 fmdmtr
; /* bus threshold register */
267 u32 fmdmhy
; /* bus hysteresis register */
268 u32 fmdmsetr
; /* SOS emergency threshold register */
269 u32 fmdmtah
; /* transfer bus address high register */
270 u32 fmdmtal
; /* transfer bus address low register */
271 u32 fmdmtcid
; /* transfer bus communication ID register */
272 u32 fmdmra
; /* DMA bus internal ram address register */
273 u32 fmdmrd
; /* DMA bus internal ram data register */
275 u32 fmdmdcr
; /* debug counter */
276 u32 fmdmemsr
; /* emrgency smoother register */
278 u32 fmdmplr
[32]; /* FM DMA PID-LIODN # register */
282 /* FMDMSR - Fman DMA status register */
283 #define FMDMSR_CMDQNE 0x10000000 /* command queue not empty */
284 #define FMDMSR_BER 0x08000000 /* bus err event occurred on bus */
285 #define FMDMSR_RDB_ECC 0x04000000 /* read buffer ECC error */
286 #define FMDMSR_WRB_SECC 0x02000000 /* write buf ECC err sys side */
287 #define FMDMSR_WRB_FECC 0x01000000 /* write buf ECC err Fman side */
288 #define FMDMSR_DPEXT_SECC 0x00800000 /* DP external ECC err sys side */
289 #define FMDMSR_DPEXT_FECC 0x00400000 /* DP external ECC err Fman side */
290 #define FMDMSR_DPDAT_SECC 0x00200000 /* DP data ECC err on sys side */
291 #define FMDMSR_DPDAT_FECC 0x00100000 /* DP data ECC err on Fman side */
292 #define FMDMSR_SPDAT_FECC 0x00080000 /* SP data ECC error Fman side */
294 #define FMDMSR_CLEAR_ALL (FMDMSR_BER | FMDMSR_RDB_ECC \
295 | FMDMSR_WRB_SECC | FMDMSR_WRB_FECC \
296 | FMDMSR_DPEXT_SECC | FMDMSR_DPEXT_FECC \
297 | FMDMSR_DPDAT_SECC | FMDMSR_DPDAT_FECC \
300 /* FMDMMR - FMan DMA mode register */
301 #define FMDMMR_SBER 0x10000000 /* stop the DMA if a bus error */
303 typedef struct fm_fpm
{
304 u32 fpmtnc
; /* TNUM control */
305 u32 fpmprc
; /* Port_ID control */
307 u32 fpmflc
; /* flush control */
308 u32 fpmdis1
; /* dispatch thresholds1 */
309 u32 fpmdis2
; /* dispatch thresholds2 */
310 u32 fmepi
; /* error pending interrupts */
311 u32 fmrie
; /* rams interrupt enable */
312 u32 fpmfcevent
[0x4];/* FMan controller event 0-3 */
314 u32 fpmfcmask
[0x4]; /* FMan controller mask 0-3 */
316 u32 fpmtsc1
; /* timestamp control1 */
317 u32 fpmtsc2
; /* timestamp control2 */
318 u32 fpmtsp
; /* time stamp */
319 u32 fpmtsf
; /* time stamp fraction */
320 u32 fpmrcr
; /* rams control and event */
322 u32 fpmdrd
[0x4]; /* data_ram data 0-3 */
324 u32 fpmdra
; /* data ram access */
325 u32 fm_ip_rev_1
; /* IP block revision 1 */
326 u32 fm_ip_rev_2
; /* IP block revision 2 */
327 u32 fmrstc
; /* reset command */
328 u32 fmcld
; /* classifier debug control */
329 u32 fmnpi
; /* normal pending interrupts */
331 u32 fmfpee
; /* event and enable */
332 u32 fpmcev
[0x4]; /* CPU event 0-3 */
334 u32 fmfp_ps
[0x40]; /* port status */
336 u32 fpmts
[0x80]; /* task status */
340 /* FMFP_PRC - FPM Port_ID Control Register */
341 #define FMFPPRC_PORTID_MASK 0x3f000000
342 #define FMFPPRC_PORTID_SHIFT 24
343 #define FMFPPRC_ORA_SHIFT 16
344 #define FMFPPRC_RISC1 0x00000001
345 #define FMFPPRC_RISC2 0x00000002
346 #define FMFPPRC_RISC_ALL (FMFPPRC_RISC1 | FMFPPRC_RSIC2)
348 /* FPM Flush Control Register */
349 #define FMFP_FLC_DISP_LIM_NONE 0x00000000 /* no dispatch limitation */
351 /* FMFP_EE - FPM event and enable register */
352 #define FMFPEE_DECC 0x80000000 /* double ECC err on FPM ram */
353 #define FMFPEE_STL 0x40000000 /* stall of task ... */
354 #define FMFPEE_SECC 0x20000000 /* single ECC error */
355 #define FMFPEE_RFM 0x00010000 /* release FMan */
356 #define FMFPEE_DECC_EN 0x00008000 /* double ECC interrupt enable */
357 #define FMFPEE_STL_EN 0x00004000 /* stall of task interrupt enable */
358 #define FMFPEE_SECC_EN 0x00002000 /* single ECC err interrupt enable */
359 #define FMFPEE_EHM 0x00000008 /* external halt enable */
360 #define FMFPEE_UEC 0x00000004 /* FMan is not halted */
361 #define FMFPEE_CER 0x00000002 /* only errornous task stalled */
362 #define FMFPEE_DER 0x00000001 /* DMA error is just reported */
364 #define FMFPEE_CLEAR_EVENT (FMFPEE_DECC | FMFPEE_STL | FMFPEE_SECC | \
365 FMFPEE_EHM | FMFPEE_UEC | FMFPEE_CER | \
366 FMFPEE_DER | FMFPEE_RFM)
368 /* FMFP_RCR - FMan Rams Control and Event */
369 #define FMFP_RCR_MDEC 0x00008000 /* double ECC error in muram */
370 #define FMFP_RCR_IDEC 0x00004000 /* double ECC error in iram */
372 typedef struct fm_imem
{
373 u32 iadd
; /* instruction address register */
374 u32 idata
; /* instruction data register */
375 u32 itcfg
; /* timing config register */
376 u32 iready
; /* ready register */
379 #define IRAM_IADD_AIE 0x80000000 /* address auto increase enable */
380 #define IRAM_READY 0x80000000 /* ready to use */
382 typedef struct fm_soft_parser
{
386 typedef struct fm_dtesc
{
390 typedef struct fm_mdio
{
392 u32 miimcfg
; /* MII management configuration reg */
393 u32 miimcom
; /* MII management command reg */
394 u32 miimadd
; /* MII management address reg */
395 u32 miimcon
; /* MII management control reg */
396 u32 miimstat
; /* MII management status reg */
397 u32 miimind
; /* MII management indication reg */
398 u8 res1
[0x1000 - 0x138];
401 typedef struct fm_10gec
{
405 typedef struct fm_10gec_mdio
{
409 typedef struct fm_memac
{
413 typedef struct fm_memac_mdio
{
417 typedef struct fm_1588
{
421 typedef struct ccsr_fman
{
423 fm_bmi_common_t fm_bmi_common
;
424 fm_qmi_common_t fm_qmi_common
;
429 fm_parser_t fm_parser
;
432 fm_policer_t fm_policer
;
433 fm_keygen_t fm_keygen
;
438 fm_soft_parser_t fm_soft_parser
;
440 #ifdef CONFIG_SYS_FMAN_V3
443 fm_memac_mdio_t fm_memac_mdio
;
446 fm_memac_mdio_t fm_dedicated_mdio
[2];
451 } mac_1g
[8]; /* support up to 8 1g controllers */
454 fm_10gec_mdio_t fm_10gec_mdio
;
462 void fdt_fixup_fman_firmware(void *blob
);
463 #endif /*__FSL_FMAN_H__*/