2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
3 * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
5 * SPDX-License-Identifier: GPL-2.0+
16 #ifdef CONFIG_SYS_FSL_IFC_LE
17 #define ifc_in32(a) in_le32(a)
18 #define ifc_out32(a, v) out_le32(a, v)
19 #define ifc_in16(a) in_le16(a)
20 #elif defined(CONFIG_SYS_FSL_IFC_BE)
21 #define ifc_in32(a) in_be32(a)
22 #define ifc_out32(a, v) out_be32(a, v)
23 #define ifc_in16(a) in_be16(a)
25 #error Neither CONFIG_SYS_FSL_IFC_LE nor CONFIG_SYS_FSL_IFC_BE is defined
30 * CSPR - Chip Select Property Register
32 #define CSPR_BA 0xFFFF0000
33 #define CSPR_BA_SHIFT 16
34 #define CSPR_PORT_SIZE 0x00000180
35 #define CSPR_PORT_SIZE_SHIFT 7
37 #define CSPR_PORT_SIZE_8 0x00000080
38 /* Port Size 16 bit */
39 #define CSPR_PORT_SIZE_16 0x00000100
40 /* Port Size 32 bit */
41 #define CSPR_PORT_SIZE_32 0x00000180
43 #define CSPR_WP 0x00000040
44 #define CSPR_WP_SHIFT 6
46 #define CSPR_MSEL 0x00000006
47 #define CSPR_MSEL_SHIFT 1
49 #define CSPR_MSEL_NOR 0x00000000
51 #define CSPR_MSEL_NAND 0x00000002
53 #define CSPR_MSEL_GPCM 0x00000004
55 #define CSPR_V 0x00000001
56 #define CSPR_V_SHIFT 0
58 /* Convert an address into the right format for the CSPR Registers */
59 #define CSPR_PHYS_ADDR(x) (((uint64_t)x) & 0xffff0000)
62 * Address Mask Register
64 #define IFC_AMASK_MASK 0xFFFF0000
65 #define IFC_AMASK_SHIFT 16
66 #define IFC_AMASK(n) (IFC_AMASK_MASK << \
67 (__ilog2(n) - IFC_AMASK_SHIFT))
70 * Chip Select Option Register IFC_NAND Machine
72 /* Enable ECC Encoder */
73 #define CSOR_NAND_ECC_ENC_EN 0x80000000
74 #define CSOR_NAND_ECC_MODE_MASK 0x30000000
75 /* 4 bit correction per 520 Byte sector */
76 #define CSOR_NAND_ECC_MODE_4 0x00000000
77 /* 8 bit correction per 528 Byte sector */
78 #define CSOR_NAND_ECC_MODE_8 0x10000000
79 /* Enable ECC Decoder */
80 #define CSOR_NAND_ECC_DEC_EN 0x04000000
81 /* Row Address Length */
82 #define CSOR_NAND_RAL_MASK 0x01800000
83 #define CSOR_NAND_RAL_SHIFT 20
84 #define CSOR_NAND_RAL_1 0x00000000
85 #define CSOR_NAND_RAL_2 0x00800000
86 #define CSOR_NAND_RAL_3 0x01000000
87 #define CSOR_NAND_RAL_4 0x01800000
88 /* Page Size 512b, 2k, 4k */
89 #define CSOR_NAND_PGS_MASK 0x00180000
90 #define CSOR_NAND_PGS_SHIFT 16
91 #define CSOR_NAND_PGS_512 0x00000000
92 #define CSOR_NAND_PGS_2K 0x00080000
93 #define CSOR_NAND_PGS_4K 0x00100000
94 #define CSOR_NAND_PGS_8K 0x00180000
95 /* Spare region Size */
96 #define CSOR_NAND_SPRZ_MASK 0x0000E000
97 #define CSOR_NAND_SPRZ_SHIFT 13
98 #define CSOR_NAND_SPRZ_16 0x00000000
99 #define CSOR_NAND_SPRZ_64 0x00002000
100 #define CSOR_NAND_SPRZ_128 0x00004000
101 #define CSOR_NAND_SPRZ_210 0x00006000
102 #define CSOR_NAND_SPRZ_218 0x00008000
103 #define CSOR_NAND_SPRZ_224 0x0000A000
104 #define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000
105 /* Pages Per Block */
106 #define CSOR_NAND_PB_MASK 0x00000700
107 #define CSOR_NAND_PB_SHIFT 8
108 #define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
109 /* Time for Read Enable High to Output High Impedance */
110 #define CSOR_NAND_TRHZ_MASK 0x0000001C
111 #define CSOR_NAND_TRHZ_SHIFT 2
112 #define CSOR_NAND_TRHZ_20 0x00000000
113 #define CSOR_NAND_TRHZ_40 0x00000004
114 #define CSOR_NAND_TRHZ_60 0x00000008
115 #define CSOR_NAND_TRHZ_80 0x0000000C
116 #define CSOR_NAND_TRHZ_100 0x00000010
117 /* Buffer control disable */
118 #define CSOR_NAND_BCTLD 0x00000001
121 * Chip Select Option Register - NOR Flash Mode
123 /* Enable Address shift Mode */
124 #define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000
125 /* Page Read Enable from NOR device */
126 #define CSOR_NOR_PGRD_EN 0x10000000
127 /* AVD Toggle Enable during Burst Program */
128 #define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000
129 /* Address Data Multiplexing Shift */
130 #define CSOR_NOR_ADM_MASK 0x0003E000
131 #define CSOR_NOR_ADM_SHIFT_SHIFT 13
132 #define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT)
133 /* Type of the NOR device hooked */
134 #define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000
135 #define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020
136 /* Time for Read Enable High to Output High Impedance */
137 #define CSOR_NOR_TRHZ_MASK 0x0000001C
138 #define CSOR_NOR_TRHZ_SHIFT 2
139 #define CSOR_NOR_TRHZ_20 0x00000000
140 #define CSOR_NOR_TRHZ_40 0x00000004
141 #define CSOR_NOR_TRHZ_60 0x00000008
142 #define CSOR_NOR_TRHZ_80 0x0000000C
143 #define CSOR_NOR_TRHZ_100 0x00000010
144 /* Buffer control disable */
145 #define CSOR_NOR_BCTLD 0x00000001
148 * Chip Select Option Register - GPCM Mode
150 /* GPCM Mode - Normal */
151 #define CSOR_GPCM_GPMODE_NORMAL 0x00000000
152 /* GPCM Mode - GenericASIC */
153 #define CSOR_GPCM_GPMODE_ASIC 0x80000000
154 /* Parity Mode odd/even */
155 #define CSOR_GPCM_PARITY_EVEN 0x40000000
156 /* Parity Checking enable/disable */
157 #define CSOR_GPCM_PAR_EN 0x20000000
158 /* GPCM Timeout Count */
159 #define CSOR_GPCM_GPTO_MASK 0x0F000000
160 #define CSOR_GPCM_GPTO_SHIFT 24
161 #define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
162 /* GPCM External Access Termination mode for read access */
163 #define CSOR_GPCM_RGETA_EXT 0x00080000
164 /* GPCM External Access Termination mode for write access */
165 #define CSOR_GPCM_WGETA_EXT 0x00040000
166 /* Address Data Multiplexing Shift */
167 #define CSOR_GPCM_ADM_MASK 0x0003E000
168 #define CSOR_GPCM_ADM_SHIFT_SHIFT 13
169 #define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT)
170 /* Generic ASIC Parity error indication delay */
171 #define CSOR_GPCM_GAPERRD_MASK 0x00000180
172 #define CSOR_GPCM_GAPERRD_SHIFT 7
173 #define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT)
174 /* Time for Read Enable High to Output High Impedance */
175 #define CSOR_GPCM_TRHZ_MASK 0x0000001C
176 #define CSOR_GPCM_TRHZ_20 0x00000000
177 #define CSOR_GPCM_TRHZ_40 0x00000004
178 #define CSOR_GPCM_TRHZ_60 0x00000008
179 #define CSOR_GPCM_TRHZ_80 0x0000000C
180 #define CSOR_GPCM_TRHZ_100 0x00000010
181 /* Buffer control disable */
182 #define CSOR_GPCM_BCTLD 0x00000001
185 * Flash Timing Registers (FTIM0 - FTIM2_CSn)
188 * FTIM0 - NAND Flash Mode
190 #define FTIM0_NAND 0x7EFF3F3F
191 #define FTIM0_NAND_TCCST_SHIFT 25
192 #define FTIM0_NAND_TCCST(n) ((n) << FTIM0_NAND_TCCST_SHIFT)
193 #define FTIM0_NAND_TWP_SHIFT 16
194 #define FTIM0_NAND_TWP(n) ((n) << FTIM0_NAND_TWP_SHIFT)
195 #define FTIM0_NAND_TWCHT_SHIFT 8
196 #define FTIM0_NAND_TWCHT(n) ((n) << FTIM0_NAND_TWCHT_SHIFT)
197 #define FTIM0_NAND_TWH_SHIFT 0
198 #define FTIM0_NAND_TWH(n) ((n) << FTIM0_NAND_TWH_SHIFT)
200 * FTIM1 - NAND Flash Mode
202 #define FTIM1_NAND 0xFFFF3FFF
203 #define FTIM1_NAND_TADLE_SHIFT 24
204 #define FTIM1_NAND_TADLE(n) ((n) << FTIM1_NAND_TADLE_SHIFT)
205 #define FTIM1_NAND_TWBE_SHIFT 16
206 #define FTIM1_NAND_TWBE(n) ((n) << FTIM1_NAND_TWBE_SHIFT)
207 #define FTIM1_NAND_TRR_SHIFT 8
208 #define FTIM1_NAND_TRR(n) ((n) << FTIM1_NAND_TRR_SHIFT)
209 #define FTIM1_NAND_TRP_SHIFT 0
210 #define FTIM1_NAND_TRP(n) ((n) << FTIM1_NAND_TRP_SHIFT)
212 * FTIM2 - NAND Flash Mode
214 #define FTIM2_NAND 0x1FE1F8FF
215 #define FTIM2_NAND_TRAD_SHIFT 21
216 #define FTIM2_NAND_TRAD(n) ((n) << FTIM2_NAND_TRAD_SHIFT)
217 #define FTIM2_NAND_TREH_SHIFT 11
218 #define FTIM2_NAND_TREH(n) ((n) << FTIM2_NAND_TREH_SHIFT)
219 #define FTIM2_NAND_TWHRE_SHIFT 0
220 #define FTIM2_NAND_TWHRE(n) ((n) << FTIM2_NAND_TWHRE_SHIFT)
222 * FTIM3 - NAND Flash Mode
224 #define FTIM3_NAND 0xFF000000
225 #define FTIM3_NAND_TWW_SHIFT 24
226 #define FTIM3_NAND_TWW(n) ((n) << FTIM3_NAND_TWW_SHIFT)
229 * FTIM0 - NOR Flash Mode
231 #define FTIM0_NOR 0xF03F3F3F
232 #define FTIM0_NOR_TACSE_SHIFT 28
233 #define FTIM0_NOR_TACSE(n) ((n) << FTIM0_NOR_TACSE_SHIFT)
234 #define FTIM0_NOR_TEADC_SHIFT 16
235 #define FTIM0_NOR_TEADC(n) ((n) << FTIM0_NOR_TEADC_SHIFT)
236 #define FTIM0_NOR_TAVDS_SHIFT 8
237 #define FTIM0_NOR_TAVDS(n) ((n) << FTIM0_NOR_TAVDS_SHIFT)
238 #define FTIM0_NOR_TEAHC_SHIFT 0
239 #define FTIM0_NOR_TEAHC(n) ((n) << FTIM0_NOR_TEAHC_SHIFT)
241 * FTIM1 - NOR Flash Mode
243 #define FTIM1_NOR 0xFF003F3F
244 #define FTIM1_NOR_TACO_SHIFT 24
245 #define FTIM1_NOR_TACO(n) ((n) << FTIM1_NOR_TACO_SHIFT)
246 #define FTIM1_NOR_TRAD_NOR_SHIFT 8
247 #define FTIM1_NOR_TRAD_NOR(n) ((n) << FTIM1_NOR_TRAD_NOR_SHIFT)
248 #define FTIM1_NOR_TSEQRAD_NOR_SHIFT 0
249 #define FTIM1_NOR_TSEQRAD_NOR(n) ((n) << FTIM1_NOR_TSEQRAD_NOR_SHIFT)
251 * FTIM2 - NOR Flash Mode
253 #define FTIM2_NOR 0x0F3CFCFF
254 #define FTIM2_NOR_TCS_SHIFT 24
255 #define FTIM2_NOR_TCS(n) ((n) << FTIM2_NOR_TCS_SHIFT)
256 #define FTIM2_NOR_TCH_SHIFT 18
257 #define FTIM2_NOR_TCH(n) ((n) << FTIM2_NOR_TCH_SHIFT)
258 #define FTIM2_NOR_TWPH_SHIFT 10
259 #define FTIM2_NOR_TWPH(n) ((n) << FTIM2_NOR_TWPH_SHIFT)
260 #define FTIM2_NOR_TWP_SHIFT 0
261 #define FTIM2_NOR_TWP(n) ((n) << FTIM2_NOR_TWP_SHIFT)
264 * FTIM0 - Normal GPCM Mode
266 #define FTIM0_GPCM 0xF03F3F3F
267 #define FTIM0_GPCM_TACSE_SHIFT 28
268 #define FTIM0_GPCM_TACSE(n) ((n) << FTIM0_GPCM_TACSE_SHIFT)
269 #define FTIM0_GPCM_TEADC_SHIFT 16
270 #define FTIM0_GPCM_TEADC(n) ((n) << FTIM0_GPCM_TEADC_SHIFT)
271 #define FTIM0_GPCM_TAVDS_SHIFT 8
272 #define FTIM0_GPCM_TAVDS(n) ((n) << FTIM0_GPCM_TAVDS_SHIFT)
273 #define FTIM0_GPCM_TEAHC_SHIFT 0
274 #define FTIM0_GPCM_TEAHC(n) ((n) << FTIM0_GPCM_TEAHC_SHIFT)
276 * FTIM1 - Normal GPCM Mode
278 #define FTIM1_GPCM 0xFF003F00
279 #define FTIM1_GPCM_TACO_SHIFT 24
280 #define FTIM1_GPCM_TACO(n) ((n) << FTIM1_GPCM_TACO_SHIFT)
281 #define FTIM1_GPCM_TRAD_SHIFT 8
282 #define FTIM1_GPCM_TRAD(n) ((n) << FTIM1_GPCM_TRAD_SHIFT)
284 * FTIM2 - Normal GPCM Mode
286 #define FTIM2_GPCM 0x0F3C00FF
287 #define FTIM2_GPCM_TCS_SHIFT 24
288 #define FTIM2_GPCM_TCS(n) ((n) << FTIM2_GPCM_TCS_SHIFT)
289 #define FTIM2_GPCM_TCH_SHIFT 18
290 #define FTIM2_GPCM_TCH(n) ((n) << FTIM2_GPCM_TCH_SHIFT)
291 #define FTIM2_GPCM_TWP_SHIFT 0
292 #define FTIM2_GPCM_TWP(n) ((n) << FTIM2_GPCM_TWP_SHIFT)
295 * Ready Busy Status Register (RB_STAT)
298 #define IFC_RB_STAT_READY_CS0 0x80000000
299 #define IFC_RB_STAT_READY_CS1 0x40000000
300 #define IFC_RB_STAT_READY_CS2 0x20000000
301 #define IFC_RB_STAT_READY_CS3 0x10000000
304 * General Control Register (GCR)
306 #define IFC_GCR_MASK 0x8000F800
307 /* reset all IFC hardware */
308 #define IFC_GCR_SOFT_RST_ALL 0x80000000
309 /* Turnaroud Time of external buffer */
310 #define IFC_GCR_TBCTL_TRN_TIME 0x0000F800
311 #define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11
314 * Common Event and Error Status Register (CM_EVTER_STAT)
316 /* Chip select error */
317 #define IFC_CM_EVTER_STAT_CSER 0x80000000
320 * Common Event and Error Enable Register (CM_EVTER_EN)
322 /* Chip select error checking enable */
323 #define IFC_CM_EVTER_EN_CSEREN 0x80000000
326 * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN)
328 /* Chip select error interrupt enable */
329 #define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000
332 * Common Transfer Error Attribute Register-0 (CM_ERATTR0)
334 /* transaction type of error Read/Write */
335 #define IFC_CM_ERATTR0_ERTYP_READ 0x80000000
336 #define IFC_CM_ERATTR0_ERAID 0x0FF00000
337 #define IFC_CM_ERATTR0_ESRCID 0x0000FF00
340 * Clock Control Register (CCR)
342 #define IFC_CCR_MASK 0x0F0F8800
343 /* Clock division ratio */
344 #define IFC_CCR_CLK_DIV_MASK 0x0F000000
345 #define IFC_CCR_CLK_DIV_SHIFT 24
346 #define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT)
347 /* IFC Clock Delay */
348 #define IFC_CCR_CLK_DLY_MASK 0x000F0000
349 #define IFC_CCR_CLK_DLY_SHIFT 16
350 #define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT)
351 /* Invert IFC clock before sending out */
352 #define IFC_CCR_INV_CLK_EN 0x00008000
353 /* Fedback IFC Clock */
354 #define IFC_CCR_FB_IFC_CLK_SEL 0x00000800
357 * Clock Status Register (CSR)
360 #define IFC_CSR_CLK_STAT_STABLE 0x80000000
363 * IFC_NAND Machine Specific Registers
366 * NAND Configuration Register (NCFGR)
369 #define IFC_NAND_NCFGR_BOOT 0x80000000
371 #define IFC_NAND_SRAM_INIT_EN 0x20000000
372 /* Addressing Mode-ROW0+n/COL0 */
373 #define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000
374 /* Addressing Mode-ROW0+n/COL0+n */
375 #define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000
376 /* Number of loop iterations of FIR sequences for multi page operations */
377 #define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000
378 #define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12
379 #define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT)
380 /* Number of wait cycles */
381 #define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF
382 #define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0
385 * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1)
387 /* General purpose FCM flash command bytes CMD0-CMD7 */
388 #define IFC_NAND_FCR0_CMD0 0xFF000000
389 #define IFC_NAND_FCR0_CMD0_SHIFT 24
390 #define IFC_NAND_FCR0_CMD1 0x00FF0000
391 #define IFC_NAND_FCR0_CMD1_SHIFT 16
392 #define IFC_NAND_FCR0_CMD2 0x0000FF00
393 #define IFC_NAND_FCR0_CMD2_SHIFT 8
394 #define IFC_NAND_FCR0_CMD3 0x000000FF
395 #define IFC_NAND_FCR0_CMD3_SHIFT 0
396 #define IFC_NAND_FCR1_CMD4 0xFF000000
397 #define IFC_NAND_FCR1_CMD4_SHIFT 24
398 #define IFC_NAND_FCR1_CMD5 0x00FF0000
399 #define IFC_NAND_FCR1_CMD5_SHIFT 16
400 #define IFC_NAND_FCR1_CMD6 0x0000FF00
401 #define IFC_NAND_FCR1_CMD6_SHIFT 8
402 #define IFC_NAND_FCR1_CMD7 0x000000FF
403 #define IFC_NAND_FCR1_CMD7_SHIFT 0
406 * Flash ROW and COL Address Register (ROWn, COLn)
408 /* Main/spare region locator */
409 #define IFC_NAND_COL_MS 0x80000000
411 #define IFC_NAND_COL_CA_MASK 0x00000FFF
414 * NAND Flash Byte Count Register (NAND_BC)
416 /* Byte Count for read/Write */
417 #define IFC_NAND_BC 0x000001FF
420 * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
422 /* NAND Machine specific opcodes OP0-OP14*/
423 #define IFC_NAND_FIR0_OP0 0xFC000000
424 #define IFC_NAND_FIR0_OP0_SHIFT 26
425 #define IFC_NAND_FIR0_OP1 0x03F00000
426 #define IFC_NAND_FIR0_OP1_SHIFT 20
427 #define IFC_NAND_FIR0_OP2 0x000FC000
428 #define IFC_NAND_FIR0_OP2_SHIFT 14
429 #define IFC_NAND_FIR0_OP3 0x00003F00
430 #define IFC_NAND_FIR0_OP3_SHIFT 8
431 #define IFC_NAND_FIR0_OP4 0x000000FC
432 #define IFC_NAND_FIR0_OP4_SHIFT 2
433 #define IFC_NAND_FIR1_OP5 0xFC000000
434 #define IFC_NAND_FIR1_OP5_SHIFT 26
435 #define IFC_NAND_FIR1_OP6 0x03F00000
436 #define IFC_NAND_FIR1_OP6_SHIFT 20
437 #define IFC_NAND_FIR1_OP7 0x000FC000
438 #define IFC_NAND_FIR1_OP7_SHIFT 14
439 #define IFC_NAND_FIR1_OP8 0x00003F00
440 #define IFC_NAND_FIR1_OP8_SHIFT 8
441 #define IFC_NAND_FIR1_OP9 0x000000FC
442 #define IFC_NAND_FIR1_OP9_SHIFT 2
443 #define IFC_NAND_FIR2_OP10 0xFC000000
444 #define IFC_NAND_FIR2_OP10_SHIFT 26
445 #define IFC_NAND_FIR2_OP11 0x03F00000
446 #define IFC_NAND_FIR2_OP11_SHIFT 20
447 #define IFC_NAND_FIR2_OP12 0x000FC000
448 #define IFC_NAND_FIR2_OP12_SHIFT 14
449 #define IFC_NAND_FIR2_OP13 0x00003F00
450 #define IFC_NAND_FIR2_OP13_SHIFT 8
451 #define IFC_NAND_FIR2_OP14 0x000000FC
452 #define IFC_NAND_FIR2_OP14_SHIFT 2
455 * Instruction opcodes to be programmed
456 * in FIR registers- 6bits
458 enum ifc_nand_fir_opcodes
{
496 * NAND Chip Select Register (NAND_CSEL)
498 #define IFC_NAND_CSEL 0x0C000000
499 #define IFC_NAND_CSEL_SHIFT 26
500 #define IFC_NAND_CSEL_CS0 0x00000000
501 #define IFC_NAND_CSEL_CS1 0x04000000
502 #define IFC_NAND_CSEL_CS2 0x08000000
503 #define IFC_NAND_CSEL_CS3 0x0C000000
506 * NAND Operation Sequence Start (NANDSEQ_STRT)
508 /* NAND Flash Operation Start */
509 #define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000
510 /* Automatic Erase */
511 #define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000
512 /* Automatic Program */
513 #define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000
514 /* Automatic Copyback */
515 #define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000
516 /* Automatic Read Operation */
517 #define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000
518 /* Automatic Status Read */
519 #define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800
522 * NAND Event and Error Status Register (NAND_EVTER_STAT)
524 /* Operation Complete */
525 #define IFC_NAND_EVTER_STAT_OPC 0x80000000
526 /* Flash Timeout Error */
527 #define IFC_NAND_EVTER_STAT_FTOER 0x08000000
528 /* Write Protect Error */
529 #define IFC_NAND_EVTER_STAT_WPER 0x04000000
531 #define IFC_NAND_EVTER_STAT_ECCER 0x02000000
533 #define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000
534 /* Boot Loadr Done */
535 #define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000
536 /* Bad Block Indicator search select */
537 #define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800
540 * NAND Flash Page Read Completion Event Status Register
541 * (PGRDCMPL_EVT_STAT)
543 #define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000
544 /* Small Page 0-15 Done */
545 #define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n)))
546 /* Large Page(2K) 0-3 Done */
547 #define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4))
548 /* Large Page(4K) 0-1 Done */
549 #define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8))
552 * NAND Event and Error Enable Register (NAND_EVTER_EN)
554 /* Operation complete event enable */
555 #define IFC_NAND_EVTER_EN_OPC_EN 0x80000000
556 /* Page read complete event enable */
557 #define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000
558 /* Flash Timeout error enable */
559 #define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000
560 /* Write Protect error enable */
561 #define IFC_NAND_EVTER_EN_WPER_EN 0x04000000
562 /* ECC error logging enable */
563 #define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000
566 * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN)
568 /* Enable interrupt for operation complete */
569 #define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000
570 /* Enable interrupt for Page read complete */
571 #define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000
572 /* Enable interrupt for Flash timeout error */
573 #define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000
574 /* Enable interrupt for Write protect error */
575 #define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000
576 /* Enable interrupt for ECC error*/
577 #define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000
580 * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0)
582 #define IFC_NAND_ERATTR0_MASK 0x0C080000
583 /* Error on CS0-3 for NAND */
584 #define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000
585 #define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000
586 #define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000
587 #define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000
588 /* Transaction type of error Read/Write */
589 #define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000
592 * NAND Flash Status Register (NAND_FSR)
594 /* First byte of data read from read status op */
595 #define IFC_NAND_NFSR_RS0 0xFF000000
596 /* Second byte of data read from read status op */
597 #define IFC_NAND_NFSR_RS1 0x00FF0000
600 * ECC Error Status Registers (ECCSTAT0-ECCSTAT3)
602 /* Number of ECC errors on sector n (n = 0-15) */
603 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000
604 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24
605 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000
606 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16
607 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00
608 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8
609 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F
610 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0
611 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000
612 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24
613 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000
614 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16
615 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00
616 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8
617 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F
618 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0
619 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000
620 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24
621 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000
622 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16
623 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00
624 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8
625 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F
626 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0
627 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000
628 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24
629 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000
630 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16
631 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00
632 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8
633 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F
634 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0
637 * NAND Control Register (NANDCR)
639 #define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000
640 #define IFC_NAND_NCR_FTOCNT_SHIFT 25
641 #define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT)
646 /* Trigger RCW load */
647 #define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000
648 /* Trigget Auto Boot */
649 #define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000
654 /* 1st read data byte when opcode SBRD */
655 #define IFC_NAND_MDR_RDATA0 0xFF000000
656 /* 2nd read data byte when opcode SBRD */
657 #define IFC_NAND_MDR_RDATA1 0x00FF0000
660 * NOR Machine Specific Registers
663 * NOR Event and Error Status Register (NOR_EVTER_STAT)
665 /* NOR Command Sequence Operation Complete */
666 #define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000
667 /* Write Protect Error */
668 #define IFC_NOR_EVTER_STAT_WPER 0x04000000
669 /* Command Sequence Timeout Error */
670 #define IFC_NOR_EVTER_STAT_STOER 0x01000000
673 * NOR Event and Error Enable Register (NOR_EVTER_EN)
675 /* NOR Command Seq complete event enable */
676 #define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000
677 /* Write Protect Error Checking Enable */
678 #define IFC_NOR_EVTER_EN_WPEREN 0x04000000
679 /* Timeout Error Enable */
680 #define IFC_NOR_EVTER_EN_STOEREN 0x01000000
683 * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN)
685 /* Enable interrupt for OPC complete */
686 #define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000
687 /* Enable interrupt for write protect error */
688 #define IFC_NOR_EVTER_INTR_WPEREN 0x04000000
689 /* Enable interrupt for timeout error */
690 #define IFC_NOR_EVTER_INTR_STOEREN 0x01000000
693 * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0)
695 /* Source ID for error transaction */
696 #define IFC_NOR_ERATTR0_ERSRCID 0xFF000000
697 /* AXI ID for error transation */
698 #define IFC_NOR_ERATTR0_ERAID 0x000FF000
699 /* Chip select corresponds to NOR error */
700 #define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000
701 #define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010
702 #define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020
703 #define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030
704 /* Type of transaction read/write */
705 #define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001
708 * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2)
710 #define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000
711 #define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00
714 * NOR Control Register (NORCR)
716 #define IFC_NORCR_MASK 0x0F0F0000
717 /* No. of Address/Data Phase */
718 #define IFC_NORCR_NUM_PHASE_MASK 0x0F000000
719 #define IFC_NORCR_NUM_PHASE_SHIFT 24
720 #define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT)
721 /* Sequence Timeout Count */
722 #define IFC_NORCR_STOCNT_MASK 0x000F0000
723 #define IFC_NORCR_STOCNT_SHIFT 16
724 #define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
727 * GPCM Machine specific registers
730 * GPCM Event and Error Status Register (GPCM_EVTER_STAT)
733 #define IFC_GPCM_EVTER_STAT_TOER 0x04000000
735 #define IFC_GPCM_EVTER_STAT_PER 0x01000000
738 * GPCM Event and Error Enable Register (GPCM_EVTER_EN)
740 /* Timeout error enable */
741 #define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000
742 /* Parity error enable */
743 #define IFC_GPCM_EVTER_EN_PER_EN 0x01000000
746 * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN)
748 /* Enable Interrupt for timeout error */
749 #define IFC_GPCM_EEIER_TOERIR_EN 0x04000000
750 /* Enable Interrupt for Parity error */
751 #define IFC_GPCM_EEIER_PERIR_EN 0x01000000
754 * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0)
756 /* Source ID for error transaction */
757 #define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000
758 /* AXI ID for error transaction */
759 #define IFC_GPCM_ERATTR0_ERAID 0x000FF000
760 /* Chip select corresponds to GPCM error */
761 #define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000
762 #define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040
763 #define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080
764 #define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0
765 /* Type of transaction read/Write */
766 #define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001
769 * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2)
771 /* On which beat of address/data parity error is observed */
772 #define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00
773 /* Parity Error on byte */
774 #define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0
775 /* Parity Error reported in addr or data phase */
776 #define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001
779 * GPCM Status Register (GPCM_STAT)
781 #define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */
787 extern void print_ifc_regs(void);
788 extern void init_early_memctl_regs(void);
789 void init_final_memctl_regs(void);
791 #define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR)
793 #define get_ifc_cspr_ext(i) (ifc_in32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext))
794 #define get_ifc_cspr(i) (ifc_in32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr))
795 #define get_ifc_csor_ext(i) (ifc_in32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext))
796 #define get_ifc_csor(i) (ifc_in32(&(IFC_BASE_ADDR)->csor_cs[i].csor))
797 #define get_ifc_amask(i) (ifc_in32(&(IFC_BASE_ADDR)->amask_cs[i].amask))
798 #define get_ifc_ftim(i, j) (ifc_in32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j]))
800 #define set_ifc_cspr_ext(i, v) \
801 (ifc_out32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v))
802 #define set_ifc_cspr(i, v) (ifc_out32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v))
803 #define set_ifc_csor_ext(i, v) \
804 (ifc_out32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v))
805 #define set_ifc_csor(i, v) (ifc_out32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v))
806 #define set_ifc_amask(i, v) (ifc_out32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v))
807 #define set_ifc_ftim(i, j, v) \
808 (ifc_out32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v))
829 * IFC Controller NAND Machine registers
831 struct fsl_ifc_nand
{
865 u32 pgrdcmpl_evt_stat
;
869 u32 nand_evter_intr_en
;
880 u32 nand_autoboot_trgr
;
887 * IFC controller NOR Machine registers
894 u32 nor_evter_intr_en
;
905 * IFC controller GPCM Machine registers
907 struct fsl_ifc_gpcm
{
912 u32 gpcm_evter_intr_en
;
921 #ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT
922 #if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8)
923 #define IFC_CSPR_REG_LEN 148
924 #define IFC_AMASK_REG_LEN 144
925 #define IFC_CSOR_REG_LEN 144
926 #define IFC_FTIM_REG_LEN 576
928 #define IFC_CSPR_USED_LEN sizeof(struct fsl_ifc_cspr) * \
929 CONFIG_SYS_FSL_IFC_BANK_COUNT
930 #define IFC_AMASK_USED_LEN sizeof(struct fsl_ifc_amask) * \
931 CONFIG_SYS_FSL_IFC_BANK_COUNT
932 #define IFC_CSOR_USED_LEN sizeof(struct fsl_ifc_csor) * \
933 CONFIG_SYS_FSL_IFC_BANK_COUNT
934 #define IFC_FTIM_USED_LEN sizeof(struct fsl_ifc_ftim) * \
935 CONFIG_SYS_FSL_IFC_BANK_COUNT
937 #error IFC BANK count not vaild
940 #error IFC BANK count not defined
943 struct fsl_ifc_cspr
{
949 struct fsl_ifc_amask
{
954 struct fsl_ifc_csor
{
960 struct fsl_ifc_ftim
{
966 * IFC Controller Registers
971 struct fsl_ifc_cspr cspr_cs
[CONFIG_SYS_FSL_IFC_BANK_COUNT
];
972 u8 res2
[IFC_CSPR_REG_LEN
- IFC_CSPR_USED_LEN
];
973 struct fsl_ifc_amask amask_cs
[CONFIG_SYS_FSL_IFC_BANK_COUNT
];
974 u8 res3
[IFC_AMASK_REG_LEN
- IFC_AMASK_USED_LEN
];
975 struct fsl_ifc_csor csor_cs
[CONFIG_SYS_FSL_IFC_BANK_COUNT
];
976 u8 res4
[IFC_CSOR_REG_LEN
- IFC_CSOR_USED_LEN
];
977 struct fsl_ifc_ftim ftim_cs
[CONFIG_SYS_FSL_IFC_BANK_COUNT
];
978 u8 res5
[IFC_FTIM_REG_LEN
- IFC_FTIM_USED_LEN
];
987 u32 cm_evter_intr_en
;
995 struct fsl_ifc_nand ifc_nand
;
996 struct fsl_ifc_nor ifc_nor
;
997 struct fsl_ifc_gpcm ifc_gpcm
;
1000 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
1001 #undef CSPR_MSEL_NOR
1002 #define CSPR_MSEL_NOR CSPR_MSEL_GPCM
1004 #endif /* CONFIG_FSL_IFC */
1006 #endif /* __ASSEMBLY__ */
1007 #endif /* __FSL_IFC_H */