include/fsl_tgec.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2009-2011 Freescale Semiconductor, Inc.
   4  *      Dave Liu <daveliu@freescale.com>
   5  */
   6
   7 #ifndef __TGEC_H__
   8 #define __TGEC_H__
   9
  10 #include <phy.h>
  11
  12 struct tgec {
  13         /* 10GEC general control and status registers */
  14         u32     tgec_id;        /* Controller ID register */
  15         u32     res0;
  16         u32     command_config; /* Control and configuration register */
  17         u32     mac_addr_0;     /* Lower 32 bits of 48-bit MAC address */
  18         u32     mac_addr_1;     /* Upper 16 bits of 48-bit MAC address */
  19         u32     maxfrm;         /* Maximum frame length register */
  20         u32     pause_quant;    /* Pause quanta register */
  21         u32     res1[4];
  22         u32     hashtable_ctrl; /* Hash table control register */
  23         u32     res2[4];
  24         u32     status;         /* MAC status register */
  25         u32     tx_ipg_length;  /* Transmitter inter-packet-gap register */
  26         u32     mac_addr_2;     /* Lower 32 bits of the 2nd 48-bit MAC addr */
  27         u32     mac_addr_3;     /* Upper 16 bits of the 2nd 48-bit MAC addr */
  28         u32     res3[4];
  29         u32     imask;          /* Interrupt mask register */
  30         u32     ievent;         /* Interrupt event register */
  31         u32     res4[6];
  32         /* 10GEC statistics counter registers */
  33         u32     tx_frame_u;     /* Tx frame counter upper */
  34         u32     tx_frame_l;     /* Tx frame counter lower */
  35         u32     rx_frame_u;     /* Rx frame counter upper */
  36         u32     rx_frame_l;     /* Rx frame counter lower */
  37         u32     rx_frame_crc_err_u; /* Rx frame check sequence error upper */
  38         u32     rx_frame_crc_err_l; /* Rx frame check sequence error lower */
  39         u32     rx_align_err_u; /* Rx alignment error upper */
  40         u32     rx_align_err_l; /* Rx alignment error lower */
  41         u32     tx_pause_frame_u; /* Tx valid pause frame upper */
  42         u32     tx_pause_frame_l; /* Tx valid pause frame lower */
  43         u32     rx_pause_frame_u; /* Rx valid pause frame upper */
  44         u32     rx_pause_frame_l; /* Rx valid pause frame upper */
  45         u32     rx_long_err_u;  /* Rx too long frame error upper */
  46         u32     rx_long_err_l;  /* Rx too long frame error lower */
  47         u32     rx_frame_err_u; /* Rx frame length error upper */
  48         u32     rx_frame_err_l; /* Rx frame length error lower */
  49         u32     tx_vlan_u;      /* Tx VLAN frame upper */
  50         u32     tx_vlan_l;      /* Tx VLAN frame lower */
  51         u32     rx_vlan_u;      /* Rx VLAN frame upper */
  52         u32     rx_vlan_l;      /* Rx VLAN frame lower */
  53         u32     tx_oct_u;       /* Tx octets upper */
  54         u32     tx_oct_l;       /* Tx octets lower */
  55         u32     rx_oct_u;       /* Rx octets upper */
  56         u32     rx_oct_l;       /* Rx octets lower */
  57         u32     rx_uni_u;       /* Rx unicast frame upper */
  58         u32     rx_uni_l;       /* Rx unicast frame lower */
  59         u32     rx_multi_u;     /* Rx multicast frame upper */
  60         u32     rx_multi_l;     /* Rx multicast frame lower */
  61         u32     rx_brd_u;       /* Rx broadcast frame upper */
  62         u32     rx_brd_l;       /* Rx broadcast frame lower */
  63         u32     tx_frame_err_u; /* Tx frame error upper */
  64         u32     tx_frame_err_l; /* Tx frame error lower */
  65         u32     tx_uni_u;       /* Tx unicast frame upper */
  66         u32     tx_uni_l;       /* Tx unicast frame lower */
  67         u32     tx_multi_u;     /* Tx multicast frame upper */
  68         u32     tx_multi_l;     /* Tx multicast frame lower */
  69         u32     tx_brd_u;       /* Tx broadcast frame upper */
  70         u32     tx_brd_l;       /* Tx broadcast frame lower */
  71         u32     rx_drop_u;      /* Rx dropped packets upper */
  72         u32     rx_drop_l;      /* Rx dropped packets lower */
  73         u32     rx_eoct_u;      /* Rx ethernet octets upper */
  74         u32     rx_eoct_l;      /* Rx ethernet octets lower */
  75         u32     rx_pkt_u;       /* Rx packets upper */
  76         u32     rx_pkt_l;       /* Rx packets lower */
  77         u32     tx_undsz_u;     /* Undersized packet upper */
  78         u32     tx_undsz_l;     /* Undersized packet lower */
  79         u32     rx_64_u;        /* Rx 64 oct packet upper */
  80         u32     rx_64_l;        /* Rx 64 oct packet lower */
  81         u32     rx_127_u;       /* Rx 65 to 127 oct packet upper */
  82         u32     rx_127_l;       /* Rx 65 to 127 oct packet lower */
  83         u32     rx_255_u;       /* Rx 128 to 255 oct packet upper */
  84         u32     rx_255_l;       /* Rx 128 to 255 oct packet lower */
  85         u32     rx_511_u;       /* Rx 256 to 511 oct packet upper */
  86         u32     rx_511_l;       /* Rx 256 to 511 oct packet lower */
  87         u32     rx_1023_u;      /* Rx 512 to 1023 oct packet upper */
  88         u32     rx_1023_l;      /* Rx 512 to 1023 oct packet lower */
  89         u32     rx_1518_u;      /* Rx 1024 to 1518 oct packet upper */
  90         u32     rx_1518_l;      /* Rx 1024 to 1518 oct packet lower */
  91         u32     rx_1519_u;      /* Rx 1519 to max oct packet upper */
  92         u32     rx_1519_l;      /* Rx 1519 to max oct packet lower */
  93         u32     tx_oversz_u;    /* oversized packet upper */
  94         u32     tx_oversz_l;    /* oversized packet lower */
  95         u32     tx_jabber_u;    /* Jabber packet upper */
  96         u32     tx_jabber_l;    /* Jabber packet lower */
  97         u32     tx_frag_u;      /* Fragment packet upper */
  98         u32     tx_frag_l;      /* Fragment packet lower */
  99         u32     rx_err_u;       /* Rx frame error upper */
 100         u32     rx_err_l;       /* Rx frame error lower */
 101         u32     res5[0x39a];
 102 };
 103
 104 /* EC10G_ID - 10-gigabit ethernet MAC controller ID */
 105 #define EC10G_ID_VER_MASK       0x0000ff00
 106 #define EC10G_ID_VER_SHIFT      8
 107 #define EC10G_ID_REV_MASK       0x000000ff
 108
 109 /* COMMAND_CONFIG - command and configuration register */
 110 #define TGEC_CMD_CFG_EN_TIMESTAMP       0x00100000 /* enable IEEE1588 */
 111 #define TGEC_CMD_CFG_TX_ADDR_INS_SEL    0x00080000 /* Tx mac addr w/ second */
 112 #define TGEC_CMD_CFG_NO_LEN_CHK         0x00020000 /* payload len chk disable */
 113 #define TGEC_CMD_CFG_SEND_IDLE          0x00010000 /* send XGMII idle seqs */
 114 #define TGEC_CMD_CFG_RX_ER_DISC         0x00004000 /* Rx err frm discard enb */
 115 #define TGEC_CMD_CFG_CMD_FRM_EN         0x00002000 /* CMD frame RX enable */
 116 #define TGEC_CMD_CFG_STAT_CLR           0x00001000 /* clear stats */
 117 #define TGEC_CMD_CFG_TX_ADDR_INS        0x00000200 /* overwrite src MAC addr */
 118 #define TGEC_CMD_CFG_PAUSE_IGNORE       0x00000100 /* ignore pause frames */
 119 #define TGEC_CMD_CFG_PAUSE_FWD          0x00000080 /* fwd pause frames */
 120 #define TGEC_CMD_CFG_CRC_FWD            0x00000040 /* fwd Rx CRC frames */
 121 #define TGEC_CMD_CFG_PAD_EN             0x00000020 /* MAC remove Rx padding */
 122 #define TGEC_CMD_CFG_PROM_EN            0x00000010 /* promiscuous mode enable */
 123 #define TGEC_CMD_CFG_WAN_MODE           0x00000008 /* WAN mode enable */
 124 #define TGEC_CMD_CFG_RX_EN              0x00000002 /* MAC Rx path enable */
 125 #define TGEC_CMD_CFG_TX_EN              0x00000001 /* MAC Tx path enable */
 126 #define TGEC_CMD_CFG_RXTX_EN    (TGEC_CMD_CFG_RX_EN | TGEC_CMD_CFG_TX_EN)
 127
 128 /* HASHTABLE_CTRL - Hashtable control register */
 129 #define HASHTABLE_CTRL_MCAST_EN 0x00000200 /* enable mulitcast Rx hash */
 130 #define HASHTABLE_CTRL_ADDR_MASK        0x000001ff
 131
 132 /* TX_IPG_LENGTH - Transmit inter-packet gap length register */
 133 #define TX_IPG_LENGTH_IPG_LEN_MASK      0x000003ff
 134
 135 /* IMASK - interrupt mask register */
 136 #define IMASK_MDIO_SCAN_EVENT   0x00010000 /* MDIO scan event mask */
 137 #define IMASK_MDIO_CMD_CMPL     0x00008000 /* MDIO cmd completion mask */
 138 #define IMASK_REM_FAULT         0x00004000 /* remote fault mask */
 139 #define IMASK_LOC_FAULT         0x00002000 /* local fault mask */
 140 #define IMASK_TX_ECC_ER         0x00001000 /* Tx frame ECC error mask */
 141 #define IMASK_TX_FIFO_UNFL      0x00000800 /* Tx FIFO underflow mask */
 142 #define IMASK_TX_ER             0x00000200 /* Tx frame error mask */
 143 #define IMASK_RX_FIFO_OVFL      0x00000100 /* Rx FIFO overflow mask */
 144 #define IMASK_RX_ECC_ER         0x00000080 /* Rx frame ECC error mask */
 145 #define IMASK_RX_JAB_FRM        0x00000040 /* Rx jabber frame mask */
 146 #define IMASK_RX_OVRSZ_FRM      0x00000020 /* Rx oversized frame mask */
 147 #define IMASK_RX_RUNT_FRM       0x00000010 /* Rx runt frame mask */
 148 #define IMASK_RX_FRAG_FRM       0x00000008 /* Rx fragment frame mask */
 149 #define IMASK_RX_LEN_ER         0x00000004 /* Rx payload length error mask */
 150 #define IMASK_RX_CRC_ER         0x00000002 /* Rx CRC error mask */
 151 #define IMASK_RX_ALIGN_ER       0x00000001 /* Rx alignment error mask */
 152
 153 #define IMASK_MASK_ALL          0x00000000
 154
 155 /* IEVENT - interrupt event register */
 156 #define IEVENT_MDIO_SCAN_EVENT  0x00010000 /* MDIO scan event */
 157 #define IEVENT_MDIO_CMD_CMPL    0x00008000 /* MDIO cmd completion */
 158 #define IEVENT_REM_FAULT        0x00004000 /* remote fault */
 159 #define IEVENT_LOC_FAULT        0x00002000 /* local fault */
 160 #define IEVENT_TX_ECC_ER        0x00001000 /* Tx frame ECC error */
 161 #define IEVENT_TX_FIFO_UNFL     0x00000800 /* Tx FIFO underflow */
 162 #define IEVENT_TX_ER            0x00000200 /* Tx frame error */
 163 #define IEVENT_RX_FIFO_OVFL     0x00000100 /* Rx FIFO overflow */
 164 #define IEVENT_RX_ECC_ER        0x00000080 /* Rx frame ECC error */
 165 #define IEVENT_RX_JAB_FRM       0x00000040 /* Rx jabber frame */
 166 #define IEVENT_RX_OVRSZ_FRM     0x00000020 /* Rx oversized frame */
 167 #define IEVENT_RX_RUNT_FRM      0x00000010 /* Rx runt frame */
 168 #define IEVENT_RX_FRAG_FRM      0x00000008 /* Rx fragment frame */
 169 #define IEVENT_RX_LEN_ER        0x00000004 /* Rx payload length error */
 170 #define IEVENT_RX_CRC_ER        0x00000002 /* Rx CRC error */
 171 #define IEVENT_RX_ALIGN_ER      0x00000001 /* Rx alignment error */
 172
 173 #define IEVENT_CLEAR_ALL        0xffffffff
 174
 175 struct tgec_mdio_controller {
 176         u32     res0[0xc];
 177         u32     mdio_stat;      /* MDIO configuration and status */
 178         u32     mdio_ctl;       /* MDIO control */
 179         u32     mdio_data;      /* MDIO data */
 180         u32     mdio_addr;      /* MDIO address */
 181 };
 182
 183 #define MDIO_STAT_CLKDIV(x)     (((x>>1) & 0xff) << 8)
 184 #define MDIO_STAT_BSY           (1 << 0)
 185 #define MDIO_STAT_RD_ER         (1 << 1)
 186 #define MDIO_CTL_DEV_ADDR(x)    (x & 0x1f)
 187 #define MDIO_CTL_PORT_ADDR(x)   ((x & 0x1f) << 5)
 188 #define MDIO_CTL_PRE_DIS        (1 << 10)
 189 #define MDIO_CTL_SCAN_EN        (1 << 11)
 190 #define MDIO_CTL_POST_INC       (1 << 14)
 191 #define MDIO_CTL_READ           (1 << 15)
 192
 193 #define MDIO_DATA(x)            (x & 0xffff)
 194 #define MDIO_DATA_BSY           (1 << 31)
 195
 196 struct fsl_enet_mac;
 197
 198 void init_tgec(struct fsl_enet_mac *mac, void *base, void *phyregs,
 199                 int max_rx_len);
 200
 201 #endif