include/gdsys_fpga.h

   1 /*
   2  * (C) Copyright 2010
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __GDSYS_FPGA_H
  25 #define __GDSYS_FPGA_H
  26
  27 int init_func_fpga(void);
  28
  29 enum {
  30         FPGA_STATE_DONE_FAILED = 1 << 0,
  31         FPGA_STATE_REFLECTION_FAILED = 1 << 1,
  32         FPGA_STATE_PLATFORM = 1 << 2,
  33 };
  34
  35 int get_fpga_state(unsigned dev);
  36 void print_fpga_state(unsigned dev);
  37
  38 struct ihs_gpio {
  39         u16 read;
  40         u16 clear;
  41         u16 set;
  42 };
  43
  44 struct ihs_i2c {
  45         u16 write_mailbox;
  46         u16 write_mailbox_ext;
  47         u16 read_mailbox;
  48         u16 read_mailbox_ext;
  49 };
  50
  51 struct ihs_osd {
  52         u16 version;
  53         u16 features;
  54         u16 control;
  55         u16 xy_size;
  56         u16 xy_scale;
  57         u16 x_pos;
  58         u16 y_pos;
  59 };
  60
  61 #ifdef CONFIG_NEO
  62 struct ihs_fpga {
  63         u16 reflection_low;     /* 0x0000 */
  64         u16 versions;           /* 0x0002 */
  65         u16 fpga_features;      /* 0x0004 */
  66         u16 fpga_version;       /* 0x0006 */
  67         u16 reserved_0[8187];   /* 0x0008 */
  68         u16 reflection_high;    /* 0x3ffe */
  69 };
  70 #endif
  71
  72 #ifdef CONFIG_IO
  73 struct ihs_fpga {
  74         u16 reflection_low;     /* 0x0000 */
  75         u16 versions;           /* 0x0002 */
  76         u16 fpga_features;      /* 0x0004 */
  77         u16 fpga_version;       /* 0x0006 */
  78         u16 reserved_0[5];      /* 0x0008 */
  79         u16 quad_serdes_reset;  /* 0x0012 */
  80         u16 reserved_1[8181];   /* 0x0014 */
  81         u16 reflection_high;    /* 0x3ffe */
  82 };
  83 #endif
  84
  85 #ifdef CONFIG_IO64
  86 struct ihs_fpga {
  87         u16 reflection_low;     /* 0x0000 */
  88         u16 versions;           /* 0x0002 */
  89         u16 fpga_features;      /* 0x0004 */
  90         u16 fpga_version;       /* 0x0006 */
  91         u16 reserved_0[5];      /* 0x0008 */
  92         u16 quad_serdes_reset;  /* 0x0012 */
  93         u16 reserved_1[502];    /* 0x0014 */
  94         u16 ch0_status_int;     /* 0x0400 */
  95         u16 ch0_config_int;     /* 0x0402 */
  96         u16 reserved_2[126];    /* 0x0404 */
  97         u16 ch0_hicb_status_int;/* 0x0500 */
  98         u16 ch0_hicb_config_int;/* 0x0502 */
  99         u16 reserved_3[7549];   /* 0x0504 */
 100         u16 reflection_high;    /* 0x3ffe */
 101 };
 102 #endif
 103
 104 #ifdef CONFIG_IOCON
 105 struct ihs_fpga {
 106         u16 reflection_low;     /* 0x0000 */
 107         u16 versions;           /* 0x0002 */
 108         u16 fpga_version;       /* 0x0004 */
 109         u16 fpga_features;      /* 0x0006 */
 110         u16 reserved_0[6];      /* 0x0008 */
 111         struct ihs_gpio gpio;   /* 0x0014 */
 112         u16 mpc3w_control;      /* 0x001a */
 113         u16 reserved_1[19];     /* 0x001c */
 114         u16 videocontrol;       /* 0x0042 */
 115         u16 reserved_2[93];     /* 0x0044 */
 116         u16 reflection_high;    /* 0x00fe */
 117         struct ihs_osd osd;     /* 0x0100 */
 118         u16 reserved_3[889];    /* 0x010e */
 119         u16 videomem;           /* 0x0800 */
 120 };
 121 #endif
 122
 123 #ifdef CONFIG_DLVISION_10G
 124 struct ihs_fpga {
 125         u16 reflection_low;     /* 0x0000 */
 126         u16 versions;           /* 0x0002 */
 127         u16 fpga_version;       /* 0x0004 */
 128         u16 fpga_features;      /* 0x0006 */
 129         u16 reserved_0[10];     /* 0x0008 */
 130         u16 extended_interrupt; /* 0x001c */
 131         u16 reserved_1[9];      /* 0x001e */
 132         struct ihs_i2c i2c;     /* 0x0030 */
 133         u16 reserved_2[16];     /* 0x0038 */
 134         u16 mpc3w_control;      /* 0x0058 */
 135         u16 reserved_3[34];     /* 0x005a */
 136         u16 videocontrol;       /* 0x009e */
 137         u16 reserved_4[176];    /* 0x00a0 */
 138         struct ihs_osd osd;     /* 0x0200 */
 139         u16 reserved_5[761];    /* 0x020e */
 140         u16 videomem;           /* 0x0800 */
 141 };
 142 #endif
 143
 144 #endif