3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * SPDX-License-Identifier: GPL-2.0+
11 int init_func_fpga(void);
14 FPGA_STATE_DONE_FAILED
= 1 << 0,
15 FPGA_STATE_REFLECTION_FAILED
= 1 << 1,
16 FPGA_STATE_PLATFORM
= 1 << 2,
19 int get_fpga_state(unsigned dev
);
20 void print_fpga_state(unsigned dev
);
22 int fpga_set_reg(u32 fpga
, u16
*reg
, off_t regoff
, u16 data
);
23 int fpga_get_reg(u32 fpga
, u16
*reg
, off_t regoff
, u16
*data
);
25 extern struct ihs_fpga
*fpga_ptr
[];
27 #define FPGA_SET_REG(ix, fld, val) \
30 offsetof(struct ihs_fpga, fld), \
33 #define FPGA_GET_REG(ix, fld, val) \
36 offsetof(struct ihs_fpga, fld), \
47 u16 write_mailbox_ext
;
64 u16 reflection_low
; /* 0x0000 */
65 u16 versions
; /* 0x0002 */
66 u16 fpga_features
; /* 0x0004 */
67 u16 fpga_version
; /* 0x0006 */
68 u16 reserved_0
[8187]; /* 0x0008 */
69 u16 reflection_high
; /* 0x3ffe */
75 u16 reflection_low
; /* 0x0000 */
76 u16 versions
; /* 0x0002 */
77 u16 fpga_features
; /* 0x0004 */
78 u16 fpga_version
; /* 0x0006 */
79 u16 reserved_0
[5]; /* 0x0008 */
80 u16 quad_serdes_reset
; /* 0x0012 */
81 u16 reserved_1
[8181]; /* 0x0014 */
82 u16 reflection_high
; /* 0x3ffe */
88 struct ihs_fpga_channel
{
91 u16 switch_connect_config
;
95 struct ihs_fpga_hicb
{
101 u16 reflection_low
; /* 0x0000 */
102 u16 versions
; /* 0x0002 */
103 u16 fpga_features
; /* 0x0004 */
104 u16 fpga_version
; /* 0x0006 */
105 u16 reserved_0
[5]; /* 0x0008 */
106 u16 quad_serdes_reset
; /* 0x0012 */
107 u16 reserved_1
[502]; /* 0x0014 */
108 struct ihs_fpga_channel ch
[32]; /* 0x0400 */
109 struct ihs_fpga_channel hicb_ch
[32]; /* 0x0500 */
110 u16 reserved_2
[7487]; /* 0x0580 */
111 u16 reflection_high
; /* 0x3ffe */
117 u16 reflection_low
; /* 0x0000 */
118 u16 versions
; /* 0x0002 */
119 u16 fpga_version
; /* 0x0004 */
120 u16 fpga_features
; /* 0x0006 */
121 u16 reserved_0
[6]; /* 0x0008 */
122 struct ihs_gpio gpio
; /* 0x0014 */
123 u16 mpc3w_control
; /* 0x001a */
124 u16 reserved_1
[19]; /* 0x001c */
125 u16 videocontrol
; /* 0x0042 */
126 u16 reserved_2
[14]; /* 0x0044 */
127 u16 mc_int
; /* 0x0060 */
128 u16 mc_int_en
; /* 0x0062 */
129 u16 mc_status
; /* 0x0064 */
130 u16 mc_control
; /* 0x0066 */
131 u16 mc_tx_data
; /* 0x0068 */
132 u16 mc_tx_address
; /* 0x006a */
133 u16 mc_tx_cmd
; /* 0x006c */
134 u16 mc_res
; /* 0x006e */
135 u16 mc_rx_cmd_status
; /* 0x0070 */
136 u16 mc_rx_data
; /* 0x0072 */
137 u16 reserved_3
[69]; /* 0x0074 */
138 u16 reflection_high
; /* 0x00fe */
139 struct ihs_osd osd
; /* 0x0100 */
140 u16 reserved_4
[889]; /* 0x010e */
141 u16 videomem
[31736]; /* 0x0800 */
145 #ifdef CONFIG_DLVISION_10G
147 u16 reflection_low
; /* 0x0000 */
148 u16 versions
; /* 0x0002 */
149 u16 fpga_version
; /* 0x0004 */
150 u16 fpga_features
; /* 0x0006 */
151 u16 reserved_0
[10]; /* 0x0008 */
152 u16 extended_interrupt
; /* 0x001c */
153 u16 reserved_1
[9]; /* 0x001e */
154 struct ihs_i2c i2c
; /* 0x0030 */
155 u16 reserved_2
[16]; /* 0x0038 */
156 u16 mpc3w_control
; /* 0x0058 */
157 u16 reserved_3
[34]; /* 0x005a */
158 u16 videocontrol
; /* 0x009e */
159 u16 reserved_4
[176]; /* 0x00a0 */
160 struct ihs_osd osd
; /* 0x0200 */
161 u16 reserved_5
[761]; /* 0x020e */
162 u16 videomem
[31736]; /* 0x0800 */