4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
23 #include "hw/qdev-core.h"
24 #include "disas/dis-asm.h"
25 #include "exec/hwaddr.h"
26 #include "exec/memattrs.h"
27 #include "qapi/qapi-types-run-state.h"
28 #include "qemu/bitmap.h"
29 #include "qemu/rcu_queue.h"
30 #include "qemu/queue.h"
31 #include "qemu/thread.h"
33 typedef int (*WriteCoreDumpFunction
)(const void *buf
, size_t size
,
38 * Type wide enough to contain any #target_ulong virtual address.
40 typedef uint64_t vaddr
;
41 #define VADDR_PRId PRId64
42 #define VADDR_PRIu PRIu64
43 #define VADDR_PRIo PRIo64
44 #define VADDR_PRIx PRIx64
45 #define VADDR_PRIX PRIX64
46 #define VADDR_MAX UINT64_MAX
50 * @section_id: QEMU-cpu
52 * @short_description: Base class for all CPUs
55 #define TYPE_CPU "cpu"
57 /* Since this macro is used a lot in hot code paths and in conjunction with
58 * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using
61 #define CPU(obj) ((CPUState *)(obj))
63 #define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU)
64 #define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU)
66 typedef enum MMUAccessType
{
72 typedef struct CPUWatchpoint CPUWatchpoint
;
74 typedef void (*CPUUnassignedAccess
)(CPUState
*cpu
, hwaddr addr
,
75 bool is_write
, bool is_exec
, int opaque
,
78 struct TranslationBlock
;
82 * @class_by_name: Callback to map -cpu command line model name to an
83 * instantiatable CPU type.
84 * @parse_features: Callback to parse command line arguments.
85 * @reset: Callback to reset the #CPUState to its initial state.
86 * @reset_dump_flags: #CPUDumpFlags to use for reset logging.
87 * @has_work: Callback for checking if there is work to do.
88 * @do_interrupt: Callback for interrupt handling.
89 * @do_unassigned_access: Callback for unassigned access handling.
90 * (this is deprecated: new targets should use do_transaction_failed instead)
91 * @do_unaligned_access: Callback for unaligned access handling, if
92 * the target defines #TARGET_ALIGNED_ONLY.
93 * @do_transaction_failed: Callback for handling failed memory transactions
94 * (ie bus faults or external aborts; not MMU faults)
95 * @virtio_is_big_endian: Callback to return %true if a CPU which supports
96 * runtime configurable endianness is currently big-endian. Non-configurable
97 * CPUs can use the default implementation of this method. This method should
98 * not be used by any callers other than the pre-1.0 virtio devices.
99 * @memory_rw_debug: Callback for GDB memory access.
100 * @dump_state: Callback for dumping state.
101 * @dump_statistics: Callback for dumping statistics.
102 * @get_arch_id: Callback for getting architecture-dependent CPU ID.
103 * @get_paging_enabled: Callback for inquiring whether paging is enabled.
104 * @get_memory_mapping: Callback for obtaining the memory mappings.
105 * @set_pc: Callback for setting the Program Counter register. This
106 * should have the semantics used by the target architecture when
107 * setting the PC from a source such as an ELF file entry point;
108 * for example on Arm it will also set the Thumb mode bit based
109 * on the least significant bit of the new PC value.
110 * If the target behaviour here is anything other than "set
111 * the PC register to the value passed in" then the target must
112 * also implement the synchronize_from_tb hook.
113 * @synchronize_from_tb: Callback for synchronizing state from a TCG
114 * #TranslationBlock. This is called when we abandon execution
115 * of a TB before starting it, and must set all parts of the CPU
116 * state which the previous TB in the chain may not have updated.
117 * This always includes at least the program counter; some targets
118 * will need to do more. If this hook is not implemented then the
119 * default is to call @set_pc(tb->pc).
120 * @tlb_fill: Callback for handling a softmmu tlb miss or user-only
121 * address fault. For system mode, if the access is valid, call
122 * tlb_set_page and return true; if the access is invalid, and
123 * probe is true, return false; otherwise raise an exception and
124 * do not return. For user-only mode, always raise an exception
126 * @get_phys_page_debug: Callback for obtaining a physical address.
127 * @get_phys_page_attrs_debug: Callback for obtaining a physical address and the
128 * associated memory transaction attributes to use for the access.
129 * CPUs which use memory transaction attributes should implement this
130 * instead of get_phys_page_debug.
131 * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
132 * a memory access with the specified memory transaction attributes.
133 * @gdb_read_register: Callback for letting GDB read a register.
134 * @gdb_write_register: Callback for letting GDB write a register.
135 * @debug_check_watchpoint: Callback: return true if the architectural
136 * watchpoint whose address has matched should really fire.
137 * @debug_excp_handler: Callback for handling debug exceptions.
138 * @write_elf64_note: Callback for writing a CPU-specific ELF note to a
139 * 64-bit VM coredump.
140 * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
141 * note to a 32-bit VM coredump.
142 * @write_elf32_note: Callback for writing a CPU-specific ELF note to a
143 * 32-bit VM coredump.
144 * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
145 * note to a 32-bit VM coredump.
146 * @vmsd: State description for migration.
147 * @gdb_num_core_regs: Number of core registers accessible to GDB.
148 * @gdb_core_xml_file: File name for core registers GDB XML description.
149 * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
150 * before the insn which triggers a watchpoint rather than after it.
151 * @gdb_arch_name: Optional callback that returns the architecture name known
152 * to GDB. The caller must free the returned string with g_free.
153 * @gdb_get_dynamic_xml: Callback to return dynamically generated XML for the
154 * gdb stub. Returns a pointer to the XML contents for the specified XML file
155 * or NULL if the CPU doesn't have a dynamically generated content for it.
156 * @cpu_exec_enter: Callback for cpu_exec preparation.
157 * @cpu_exec_exit: Callback for cpu_exec cleanup.
158 * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec.
159 * @disas_set_info: Setup architecture specific components of disassembly info
160 * @adjust_watchpoint_address: Perform a target-specific adjustment to an
161 * address before attempting to match it against watchpoints.
163 * Represents a CPU family or model.
165 typedef struct CPUClass
{
167 DeviceClass parent_class
;
170 ObjectClass
*(*class_by_name
)(const char *cpu_model
);
171 void (*parse_features
)(const char *typename
, char *str
, Error
**errp
);
173 void (*reset
)(CPUState
*cpu
);
174 int reset_dump_flags
;
175 bool (*has_work
)(CPUState
*cpu
);
176 void (*do_interrupt
)(CPUState
*cpu
);
177 CPUUnassignedAccess do_unassigned_access
;
178 void (*do_unaligned_access
)(CPUState
*cpu
, vaddr addr
,
179 MMUAccessType access_type
,
180 int mmu_idx
, uintptr_t retaddr
);
181 void (*do_transaction_failed
)(CPUState
*cpu
, hwaddr physaddr
, vaddr addr
,
182 unsigned size
, MMUAccessType access_type
,
183 int mmu_idx
, MemTxAttrs attrs
,
184 MemTxResult response
, uintptr_t retaddr
);
185 bool (*virtio_is_big_endian
)(CPUState
*cpu
);
186 int (*memory_rw_debug
)(CPUState
*cpu
, vaddr addr
,
187 uint8_t *buf
, int len
, bool is_write
);
188 void (*dump_state
)(CPUState
*cpu
, FILE *, int flags
);
189 GuestPanicInformation
* (*get_crash_info
)(CPUState
*cpu
);
190 void (*dump_statistics
)(CPUState
*cpu
, int flags
);
191 int64_t (*get_arch_id
)(CPUState
*cpu
);
192 bool (*get_paging_enabled
)(const CPUState
*cpu
);
193 void (*get_memory_mapping
)(CPUState
*cpu
, MemoryMappingList
*list
,
195 void (*set_pc
)(CPUState
*cpu
, vaddr value
);
196 void (*synchronize_from_tb
)(CPUState
*cpu
, struct TranslationBlock
*tb
);
197 bool (*tlb_fill
)(CPUState
*cpu
, vaddr address
, int size
,
198 MMUAccessType access_type
, int mmu_idx
,
199 bool probe
, uintptr_t retaddr
);
200 hwaddr (*get_phys_page_debug
)(CPUState
*cpu
, vaddr addr
);
201 hwaddr (*get_phys_page_attrs_debug
)(CPUState
*cpu
, vaddr addr
,
203 int (*asidx_from_attrs
)(CPUState
*cpu
, MemTxAttrs attrs
);
204 int (*gdb_read_register
)(CPUState
*cpu
, uint8_t *buf
, int reg
);
205 int (*gdb_write_register
)(CPUState
*cpu
, uint8_t *buf
, int reg
);
206 bool (*debug_check_watchpoint
)(CPUState
*cpu
, CPUWatchpoint
*wp
);
207 void (*debug_excp_handler
)(CPUState
*cpu
);
209 int (*write_elf64_note
)(WriteCoreDumpFunction f
, CPUState
*cpu
,
210 int cpuid
, void *opaque
);
211 int (*write_elf64_qemunote
)(WriteCoreDumpFunction f
, CPUState
*cpu
,
213 int (*write_elf32_note
)(WriteCoreDumpFunction f
, CPUState
*cpu
,
214 int cpuid
, void *opaque
);
215 int (*write_elf32_qemunote
)(WriteCoreDumpFunction f
, CPUState
*cpu
,
218 const VMStateDescription
*vmsd
;
219 const char *gdb_core_xml_file
;
220 gchar
* (*gdb_arch_name
)(CPUState
*cpu
);
221 const char * (*gdb_get_dynamic_xml
)(CPUState
*cpu
, const char *xmlname
);
222 void (*cpu_exec_enter
)(CPUState
*cpu
);
223 void (*cpu_exec_exit
)(CPUState
*cpu
);
224 bool (*cpu_exec_interrupt
)(CPUState
*cpu
, int interrupt_request
);
226 void (*disas_set_info
)(CPUState
*cpu
, disassemble_info
*info
);
227 vaddr (*adjust_watchpoint_address
)(CPUState
*cpu
, vaddr addr
, int len
);
228 void (*tcg_initialize
)(void);
230 /* Keep non-pointer data at the end to minimize holes. */
231 int gdb_num_core_regs
;
232 bool gdb_stop_before_watchpoint
;
236 * Low 16 bits: number of cycles left, used only in icount mode.
237 * High 16 bits: Set to -1 to force TCG to stop executing linked TBs
238 * for this CPU and return to its top level loop (even in non-icount mode).
239 * This allows a single read-compare-cbranch-write sequence to test
240 * for both decrementer underflow and exceptions.
242 typedef union IcountDecr
{
245 #ifdef HOST_WORDS_BIGENDIAN
255 typedef struct CPUBreakpoint
{
257 int flags
; /* BP_* */
258 QTAILQ_ENTRY(CPUBreakpoint
) entry
;
261 struct CPUWatchpoint
{
266 int flags
; /* BP_* */
267 QTAILQ_ENTRY(CPUWatchpoint
) entry
;
273 struct hax_vcpu_state
;
275 #define TB_JMP_CACHE_BITS 12
276 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
280 /* The union type allows passing of 64 bit target pointers on 32 bit
281 * hosts in a single parameter
285 unsigned long host_ulong
;
290 #define RUN_ON_CPU_HOST_PTR(p) ((run_on_cpu_data){.host_ptr = (p)})
291 #define RUN_ON_CPU_HOST_INT(i) ((run_on_cpu_data){.host_int = (i)})
292 #define RUN_ON_CPU_HOST_ULONG(ul) ((run_on_cpu_data){.host_ulong = (ul)})
293 #define RUN_ON_CPU_TARGET_PTR(v) ((run_on_cpu_data){.target_ptr = (v)})
294 #define RUN_ON_CPU_NULL RUN_ON_CPU_HOST_PTR(NULL)
296 typedef void (*run_on_cpu_func
)(CPUState
*cpu
, run_on_cpu_data data
);
298 struct qemu_work_item
;
300 #define CPU_UNSET_NUMA_NODE_ID -1
301 #define CPU_TRACE_DSTATE_MAX_EVENTS 32
305 * @cpu_index: CPU index (informative).
306 * @cluster_index: Identifies which cluster this CPU is in.
307 * For boards which don't define clusters or for "loose" CPUs not assigned
308 * to a cluster this will be UNASSIGNED_CLUSTER_INDEX; otherwise it will
309 * be the same as the cluster-id property of the CPU object's TYPE_CPU_CLUSTER
311 * @nr_cores: Number of cores within this CPU package.
312 * @nr_threads: Number of threads within this CPU.
313 * @running: #true if CPU is currently running (lockless).
314 * @has_waiter: #true if a CPU is currently waiting for the cpu_exec_end;
315 * valid under cpu_list_lock.
316 * @created: Indicates whether the CPU thread has been successfully created.
317 * @interrupt_request: Indicates a pending interrupt request.
318 * @halted: Nonzero if the CPU is in suspended state.
319 * @stop: Indicates a pending stop request.
320 * @stopped: Indicates the CPU has been artificially stopped.
321 * @unplug: Indicates a pending CPU unplug request.
322 * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU
323 * @singlestep_enabled: Flags for single-stepping.
324 * @icount_extra: Instructions until next timer event.
325 * @can_do_io: Nonzero if memory-mapped IO is safe. Deterministic execution
326 * requires that IO only be performed on the last instruction of a TB
327 * so that interrupts take effect immediately.
328 * @cpu_ases: Pointer to array of CPUAddressSpaces (which define the
329 * AddressSpaces this CPU has)
330 * @num_ases: number of CPUAddressSpaces in @cpu_ases
331 * @as: Pointer to the first AddressSpace, for the convenience of targets which
332 * only have a single AddressSpace
333 * @env_ptr: Pointer to subclass-specific CPUArchState field.
334 * @icount_decr_ptr: Pointer to IcountDecr field within subclass.
335 * @gdb_regs: Additional GDB registers.
336 * @gdb_num_regs: Number of total registers accessible to GDB.
337 * @gdb_num_g_regs: Number of registers in GDB 'g' packets.
338 * @next_cpu: Next CPU sharing TB cache.
339 * @opaque: User data.
340 * @mem_io_pc: Host Program Counter at which the memory was accessed.
341 * @kvm_fd: vCPU file descriptor for KVM.
342 * @work_mutex: Lock to prevent multiple access to queued_work_*.
343 * @queued_work_first: First asynchronous work pending.
344 * @trace_dstate_delayed: Delayed changes to trace_dstate (includes all changes
346 * @trace_dstate: Dynamic tracing state of events for this vCPU (bitmask).
347 * @ignore_memory_transaction_failures: Cached copy of the MachineState
348 * flag of the same name: allows the board to suppress calling of the
349 * CPU do_transaction_failed hook function.
351 * State of one CPU core or thread.
355 DeviceState parent_obj
;
361 struct QemuThread
*thread
;
366 bool running
, has_waiter
;
367 struct QemuCond
*halt_cond
;
375 uint32_t cflags_next_tb
;
376 /* updates protected by BQL */
377 uint32_t interrupt_request
;
378 int singlestep_enabled
;
379 int64_t icount_budget
;
380 int64_t icount_extra
;
381 uint64_t random_seed
;
384 QemuMutex work_mutex
;
385 struct qemu_work_item
*queued_work_first
, *queued_work_last
;
387 CPUAddressSpace
*cpu_ases
;
390 MemoryRegion
*memory
;
392 void *env_ptr
; /* CPUArchState */
393 IcountDecr
*icount_decr_ptr
;
395 /* Accessed in parallel; all accesses must be atomic */
396 struct TranslationBlock
*tb_jmp_cache
[TB_JMP_CACHE_SIZE
];
398 struct GDBRegisterState
*gdb_regs
;
401 QTAILQ_ENTRY(CPUState
) node
;
403 /* ice debug support */
404 QTAILQ_HEAD(, CPUBreakpoint
) breakpoints
;
406 QTAILQ_HEAD(, CPUWatchpoint
) watchpoints
;
407 CPUWatchpoint
*watchpoint_hit
;
411 /* In order to avoid passing too many arguments to the MMIO helpers,
412 * we store some rarely used information in the CPU context.
416 * This is only needed for the legacy cpu_unassigned_access() hook;
417 * when all targets using it have been converted to use
418 * cpu_transaction_failed() instead it can be removed.
420 MMUAccessType mem_io_access_type
;
423 struct KVMState
*kvm_state
;
424 struct kvm_run
*kvm_run
;
426 /* Used for events with 'vcpu' and *without* the 'disabled' properties */
427 DECLARE_BITMAP(trace_dstate_delayed
, CPU_TRACE_DSTATE_MAX_EVENTS
);
428 DECLARE_BITMAP(trace_dstate
, CPU_TRACE_DSTATE_MAX_EVENTS
);
430 /* TODO Move common fields from CPUArchState here. */
435 int32_t exception_index
;
437 /* shared by kvm, hax and hvf */
440 /* Used to keep track of an outstanding cpu throttle thread for migration
443 bool throttle_thread_scheduled
;
445 bool ignore_memory_transaction_failures
;
447 struct hax_vcpu_state
*hax_vcpu
;
451 /* track IOMMUs whose translations we've cached in the TCG TLB */
452 GArray
*iommu_notifiers
;
455 typedef QTAILQ_HEAD(CPUTailQ
, CPUState
) CPUTailQ
;
456 extern CPUTailQ cpus
;
458 #define first_cpu QTAILQ_FIRST_RCU(&cpus)
459 #define CPU_NEXT(cpu) QTAILQ_NEXT_RCU(cpu, node)
460 #define CPU_FOREACH(cpu) QTAILQ_FOREACH_RCU(cpu, &cpus, node)
461 #define CPU_FOREACH_SAFE(cpu, next_cpu) \
462 QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus, node, next_cpu)
464 extern __thread CPUState
*current_cpu
;
466 static inline void cpu_tb_jmp_cache_clear(CPUState
*cpu
)
470 for (i
= 0; i
< TB_JMP_CACHE_SIZE
; i
++) {
471 atomic_set(&cpu
->tb_jmp_cache
[i
], NULL
);
476 * qemu_tcg_mttcg_enabled:
477 * Check whether we are running MultiThread TCG or not.
479 * Returns: %true if we are in MTTCG mode %false otherwise.
481 extern bool mttcg_enabled
;
482 #define qemu_tcg_mttcg_enabled() (mttcg_enabled)
485 * cpu_paging_enabled:
486 * @cpu: The CPU whose state is to be inspected.
488 * Returns: %true if paging is enabled, %false otherwise.
490 bool cpu_paging_enabled(const CPUState
*cpu
);
493 * cpu_get_memory_mapping:
494 * @cpu: The CPU whose memory mappings are to be obtained.
495 * @list: Where to write the memory mappings to.
496 * @errp: Pointer for reporting an #Error.
498 void cpu_get_memory_mapping(CPUState
*cpu
, MemoryMappingList
*list
,
502 * cpu_write_elf64_note:
503 * @f: pointer to a function that writes memory to a file
504 * @cpu: The CPU whose memory is to be dumped
505 * @cpuid: ID number of the CPU
506 * @opaque: pointer to the CPUState struct
508 int cpu_write_elf64_note(WriteCoreDumpFunction f
, CPUState
*cpu
,
509 int cpuid
, void *opaque
);
512 * cpu_write_elf64_qemunote:
513 * @f: pointer to a function that writes memory to a file
514 * @cpu: The CPU whose memory is to be dumped
515 * @cpuid: ID number of the CPU
516 * @opaque: pointer to the CPUState struct
518 int cpu_write_elf64_qemunote(WriteCoreDumpFunction f
, CPUState
*cpu
,
522 * cpu_write_elf32_note:
523 * @f: pointer to a function that writes memory to a file
524 * @cpu: The CPU whose memory is to be dumped
525 * @cpuid: ID number of the CPU
526 * @opaque: pointer to the CPUState struct
528 int cpu_write_elf32_note(WriteCoreDumpFunction f
, CPUState
*cpu
,
529 int cpuid
, void *opaque
);
532 * cpu_write_elf32_qemunote:
533 * @f: pointer to a function that writes memory to a file
534 * @cpu: The CPU whose memory is to be dumped
535 * @cpuid: ID number of the CPU
536 * @opaque: pointer to the CPUState struct
538 int cpu_write_elf32_qemunote(WriteCoreDumpFunction f
, CPUState
*cpu
,
542 * cpu_get_crash_info:
543 * @cpu: The CPU to get crash information for
545 * Gets the previously saved crash information.
546 * Caller is responsible for freeing the data.
548 GuestPanicInformation
*cpu_get_crash_info(CPUState
*cpu
);
553 * @CPU_DUMP_FPU: dump FPU register state, not just integer
554 * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state
557 CPU_DUMP_CODE
= 0x00010000,
558 CPU_DUMP_FPU
= 0x00020000,
559 CPU_DUMP_CCOP
= 0x00040000,
564 * @cpu: The CPU whose state is to be dumped.
565 * @f: If non-null, dump to this stream, else to current print sink.
569 void cpu_dump_state(CPUState
*cpu
, FILE *f
, int flags
);
572 * cpu_dump_statistics:
573 * @cpu: The CPU whose state is to be dumped.
574 * @flags: Flags what to dump.
576 * Dump CPU statistics to the current monitor if we have one, else to
579 void cpu_dump_statistics(CPUState
*cpu
, int flags
);
581 #ifndef CONFIG_USER_ONLY
583 * cpu_get_phys_page_attrs_debug:
584 * @cpu: The CPU to obtain the physical page address for.
585 * @addr: The virtual address.
586 * @attrs: Updated on return with the memory transaction attributes to use
589 * Obtains the physical page corresponding to a virtual one, together
590 * with the corresponding memory transaction attributes to use for the access.
591 * Use it only for debugging because no protection checks are done.
593 * Returns: Corresponding physical page address or -1 if no page found.
595 static inline hwaddr
cpu_get_phys_page_attrs_debug(CPUState
*cpu
, vaddr addr
,
598 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
600 if (cc
->get_phys_page_attrs_debug
) {
601 return cc
->get_phys_page_attrs_debug(cpu
, addr
, attrs
);
603 /* Fallback for CPUs which don't implement the _attrs_ hook */
604 *attrs
= MEMTXATTRS_UNSPECIFIED
;
605 return cc
->get_phys_page_debug(cpu
, addr
);
609 * cpu_get_phys_page_debug:
610 * @cpu: The CPU to obtain the physical page address for.
611 * @addr: The virtual address.
613 * Obtains the physical page corresponding to a virtual one.
614 * Use it only for debugging because no protection checks are done.
616 * Returns: Corresponding physical page address or -1 if no page found.
618 static inline hwaddr
cpu_get_phys_page_debug(CPUState
*cpu
, vaddr addr
)
620 MemTxAttrs attrs
= {};
622 return cpu_get_phys_page_attrs_debug(cpu
, addr
, &attrs
);
625 /** cpu_asidx_from_attrs:
627 * @attrs: memory transaction attributes
629 * Returns the address space index specifying the CPU AddressSpace
630 * to use for a memory access with the given transaction attributes.
632 static inline int cpu_asidx_from_attrs(CPUState
*cpu
, MemTxAttrs attrs
)
634 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
637 if (cc
->asidx_from_attrs
) {
638 ret
= cc
->asidx_from_attrs(cpu
, attrs
);
639 assert(ret
< cpu
->num_ases
&& ret
>= 0);
647 * @cpu: The CPU to be added to the list of CPUs.
649 void cpu_list_add(CPUState
*cpu
);
653 * @cpu: The CPU to be removed from the list of CPUs.
655 void cpu_list_remove(CPUState
*cpu
);
659 * @cpu: The CPU whose state is to be reset.
661 void cpu_reset(CPUState
*cpu
);
665 * @typename: The CPU base type.
666 * @cpu_model: The model string without any parameters.
668 * Looks up a CPU #ObjectClass matching name @cpu_model.
670 * Returns: A #CPUClass or %NULL if not matching class is found.
672 ObjectClass
*cpu_class_by_name(const char *typename
, const char *cpu_model
);
676 * @typename: The CPU type.
678 * Instantiates a CPU and realizes the CPU.
680 * Returns: A #CPUState or %NULL if an error occurred.
682 CPUState
*cpu_create(const char *typename
);
686 * @cpu_option: The -cpu option including optional parameters.
688 * processes optional parameters and registers them as global properties
690 * Returns: type of CPU to create or prints error and terminates process
691 * if an error occurred.
693 const char *parse_cpu_option(const char *cpu_option
);
697 * @cpu: The vCPU to check.
699 * Checks whether the CPU has work to do.
701 * Returns: %true if the CPU has work, %false otherwise.
703 static inline bool cpu_has_work(CPUState
*cpu
)
705 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
707 g_assert(cc
->has_work
);
708 return cc
->has_work(cpu
);
713 * @cpu: The vCPU to check against.
715 * Checks whether the caller is executing on the vCPU thread.
717 * Returns: %true if called from @cpu's thread, %false otherwise.
719 bool qemu_cpu_is_self(CPUState
*cpu
);
723 * @cpu: The vCPU to kick.
725 * Kicks @cpu's thread.
727 void qemu_cpu_kick(CPUState
*cpu
);
731 * @cpu: The CPU to check.
733 * Checks whether the CPU is stopped.
735 * Returns: %true if run state is not running or if artificially stopped;
738 bool cpu_is_stopped(CPUState
*cpu
);
742 * @cpu: The vCPU to run on.
743 * @func: The function to be executed.
744 * @data: Data to pass to the function.
745 * @mutex: Mutex to release while waiting for @func to run.
747 * Used internally in the implementation of run_on_cpu.
749 void do_run_on_cpu(CPUState
*cpu
, run_on_cpu_func func
, run_on_cpu_data data
,
754 * @cpu: The vCPU to run on.
755 * @func: The function to be executed.
756 * @data: Data to pass to the function.
758 * Schedules the function @func for execution on the vCPU @cpu.
760 void run_on_cpu(CPUState
*cpu
, run_on_cpu_func func
, run_on_cpu_data data
);
764 * @cpu: The vCPU to run on.
765 * @func: The function to be executed.
766 * @data: Data to pass to the function.
768 * Schedules the function @func for execution on the vCPU @cpu asynchronously.
770 void async_run_on_cpu(CPUState
*cpu
, run_on_cpu_func func
, run_on_cpu_data data
);
773 * async_safe_run_on_cpu:
774 * @cpu: The vCPU to run on.
775 * @func: The function to be executed.
776 * @data: Data to pass to the function.
778 * Schedules the function @func for execution on the vCPU @cpu asynchronously,
779 * while all other vCPUs are sleeping.
781 * Unlike run_on_cpu and async_run_on_cpu, the function is run outside the
784 void async_safe_run_on_cpu(CPUState
*cpu
, run_on_cpu_func func
, run_on_cpu_data data
);
788 * @index: The CPUState@cpu_index value of the CPU to obtain.
790 * Gets a CPU matching @index.
792 * Returns: The CPU or %NULL if there is no matching CPU.
794 CPUState
*qemu_get_cpu(int index
);
798 * @id: Guest-exposed CPU ID to lookup.
800 * Search for CPU with specified ID.
802 * Returns: %true - CPU is found, %false - CPU isn't found.
804 bool cpu_exists(int64_t id
);
808 * @id: Guest-exposed CPU ID of the CPU to obtain.
810 * Get a CPU with matching @id.
812 * Returns: The CPU or %NULL if there is no matching CPU.
814 CPUState
*cpu_by_arch_id(int64_t id
);
818 * @new_throttle_pct: Percent of sleep time. Valid range is 1 to 99.
820 * Throttles all vcpus by forcing them to sleep for the given percentage of
821 * time. A throttle_percentage of 25 corresponds to a 75% duty cycle roughly.
822 * (example: 10ms sleep for every 30ms awake).
824 * cpu_throttle_set can be called as needed to adjust new_throttle_pct.
825 * Once the throttling starts, it will remain in effect until cpu_throttle_stop
828 void cpu_throttle_set(int new_throttle_pct
);
833 * Stops the vcpu throttling started by cpu_throttle_set.
835 void cpu_throttle_stop(void);
838 * cpu_throttle_active:
840 * Returns: %true if the vcpus are currently being throttled, %false otherwise.
842 bool cpu_throttle_active(void);
845 * cpu_throttle_get_percentage:
847 * Returns the vcpu throttle percentage. See cpu_throttle_set for details.
849 * Returns: The throttle percentage in range 1 to 99.
851 int cpu_throttle_get_percentage(void);
853 #ifndef CONFIG_USER_ONLY
855 typedef void (*CPUInterruptHandler
)(CPUState
*, int);
857 extern CPUInterruptHandler cpu_interrupt_handler
;
861 * @cpu: The CPU to set an interrupt on.
862 * @mask: The interrupts to set.
864 * Invokes the interrupt handler.
866 static inline void cpu_interrupt(CPUState
*cpu
, int mask
)
868 cpu_interrupt_handler(cpu
, mask
);
871 #else /* USER_ONLY */
873 void cpu_interrupt(CPUState
*cpu
, int mask
);
875 #endif /* USER_ONLY */
879 #ifdef CONFIG_SOFTMMU
880 static inline void cpu_unassigned_access(CPUState
*cpu
, hwaddr addr
,
881 bool is_write
, bool is_exec
,
882 int opaque
, unsigned size
)
884 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
886 if (cc
->do_unassigned_access
) {
887 cc
->do_unassigned_access(cpu
, addr
, is_write
, is_exec
, opaque
, size
);
891 static inline void cpu_unaligned_access(CPUState
*cpu
, vaddr addr
,
892 MMUAccessType access_type
,
893 int mmu_idx
, uintptr_t retaddr
)
895 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
897 cc
->do_unaligned_access(cpu
, addr
, access_type
, mmu_idx
, retaddr
);
900 static inline void cpu_transaction_failed(CPUState
*cpu
, hwaddr physaddr
,
901 vaddr addr
, unsigned size
,
902 MMUAccessType access_type
,
903 int mmu_idx
, MemTxAttrs attrs
,
904 MemTxResult response
,
907 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
909 if (!cpu
->ignore_memory_transaction_failures
&& cc
->do_transaction_failed
) {
910 cc
->do_transaction_failed(cpu
, physaddr
, addr
, size
, access_type
,
911 mmu_idx
, attrs
, response
, retaddr
);
916 #endif /* NEED_CPU_H */
920 * @cpu: The CPU to set the program counter for.
921 * @addr: Program counter value.
923 * Sets the program counter for a CPU.
925 static inline void cpu_set_pc(CPUState
*cpu
, vaddr addr
)
927 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
929 cc
->set_pc(cpu
, addr
);
933 * cpu_reset_interrupt:
934 * @cpu: The CPU to clear the interrupt on.
935 * @mask: The interrupt mask to clear.
937 * Resets interrupts on the vCPU @cpu.
939 void cpu_reset_interrupt(CPUState
*cpu
, int mask
);
943 * @cpu: The CPU to exit.
945 * Requests the CPU @cpu to exit execution.
947 void cpu_exit(CPUState
*cpu
);
951 * @cpu: The CPU to resume.
953 * Resumes CPU, i.e. puts CPU into runnable state.
955 void cpu_resume(CPUState
*cpu
);
959 * @cpu: The CPU to remove.
961 * Requests the CPU to be removed.
963 void cpu_remove(CPUState
*cpu
);
967 * @cpu: The CPU to remove.
969 * Requests the CPU to be removed and waits till it is removed.
971 void cpu_remove_sync(CPUState
*cpu
);
974 * process_queued_cpu_work() - process all items on CPU work queue
975 * @cpu: The CPU which work queue to process.
977 void process_queued_cpu_work(CPUState
*cpu
);
981 * @cpu: The CPU for the current thread.
983 * Record that a CPU has started execution and can be interrupted with
986 void cpu_exec_start(CPUState
*cpu
);
990 * @cpu: The CPU for the current thread.
992 * Record that a CPU has stopped execution and exclusive sections
993 * can be executed without interrupting it.
995 void cpu_exec_end(CPUState
*cpu
);
1000 * Wait for a concurrent exclusive section to end, and then start
1001 * a section of work that is run while other CPUs are not running
1002 * between cpu_exec_start and cpu_exec_end. CPUs that are running
1003 * cpu_exec are exited immediately. CPUs that call cpu_exec_start
1004 * during the exclusive section go to sleep until this CPU calls
1007 void start_exclusive(void);
1012 * Concludes an exclusive execution section started by start_exclusive.
1014 void end_exclusive(void);
1018 * @cpu: The vCPU to initialize.
1020 * Initializes a vCPU.
1022 void qemu_init_vcpu(CPUState
*cpu
);
1024 #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
1025 #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
1026 #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
1030 * @cpu: CPU to the flags for.
1031 * @enabled: Flags to enable.
1033 * Enables or disables single-stepping for @cpu.
1035 void cpu_single_step(CPUState
*cpu
, int enabled
);
1037 /* Breakpoint/watchpoint flags */
1038 #define BP_MEM_READ 0x01
1039 #define BP_MEM_WRITE 0x02
1040 #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE)
1041 #define BP_STOP_BEFORE_ACCESS 0x04
1042 /* 0x08 currently unused */
1045 #define BP_ANY (BP_GDB | BP_CPU)
1046 #define BP_WATCHPOINT_HIT_READ 0x40
1047 #define BP_WATCHPOINT_HIT_WRITE 0x80
1048 #define BP_WATCHPOINT_HIT (BP_WATCHPOINT_HIT_READ | BP_WATCHPOINT_HIT_WRITE)
1050 int cpu_breakpoint_insert(CPUState
*cpu
, vaddr pc
, int flags
,
1051 CPUBreakpoint
**breakpoint
);
1052 int cpu_breakpoint_remove(CPUState
*cpu
, vaddr pc
, int flags
);
1053 void cpu_breakpoint_remove_by_ref(CPUState
*cpu
, CPUBreakpoint
*breakpoint
);
1054 void cpu_breakpoint_remove_all(CPUState
*cpu
, int mask
);
1056 /* Return true if PC matches an installed breakpoint. */
1057 static inline bool cpu_breakpoint_test(CPUState
*cpu
, vaddr pc
, int mask
)
1061 if (unlikely(!QTAILQ_EMPTY(&cpu
->breakpoints
))) {
1062 QTAILQ_FOREACH(bp
, &cpu
->breakpoints
, entry
) {
1063 if (bp
->pc
== pc
&& (bp
->flags
& mask
)) {
1071 #ifdef CONFIG_USER_ONLY
1072 static inline int cpu_watchpoint_insert(CPUState
*cpu
, vaddr addr
, vaddr len
,
1073 int flags
, CPUWatchpoint
**watchpoint
)
1078 static inline int cpu_watchpoint_remove(CPUState
*cpu
, vaddr addr
,
1079 vaddr len
, int flags
)
1084 static inline void cpu_watchpoint_remove_by_ref(CPUState
*cpu
,
1089 static inline void cpu_watchpoint_remove_all(CPUState
*cpu
, int mask
)
1093 static inline void cpu_check_watchpoint(CPUState
*cpu
, vaddr addr
, vaddr len
,
1094 MemTxAttrs atr
, int fl
, uintptr_t ra
)
1098 static inline int cpu_watchpoint_address_matches(CPUState
*cpu
,
1099 vaddr addr
, vaddr len
)
1104 int cpu_watchpoint_insert(CPUState
*cpu
, vaddr addr
, vaddr len
,
1105 int flags
, CPUWatchpoint
**watchpoint
);
1106 int cpu_watchpoint_remove(CPUState
*cpu
, vaddr addr
,
1107 vaddr len
, int flags
);
1108 void cpu_watchpoint_remove_by_ref(CPUState
*cpu
, CPUWatchpoint
*watchpoint
);
1109 void cpu_watchpoint_remove_all(CPUState
*cpu
, int mask
);
1110 void cpu_check_watchpoint(CPUState
*cpu
, vaddr addr
, vaddr len
,
1111 MemTxAttrs attrs
, int flags
, uintptr_t ra
);
1112 int cpu_watchpoint_address_matches(CPUState
*cpu
, vaddr addr
, vaddr len
);
1116 * cpu_get_address_space:
1117 * @cpu: CPU to get address space from
1118 * @asidx: index identifying which address space to get
1120 * Return the requested address space of this CPU. @asidx
1121 * specifies which address space to read.
1123 AddressSpace
*cpu_get_address_space(CPUState
*cpu
, int asidx
);
1125 void QEMU_NORETURN
cpu_abort(CPUState
*cpu
, const char *fmt
, ...)
1127 extern Property cpu_common_props
[];
1128 void cpu_exec_initfn(CPUState
*cpu
);
1129 void cpu_exec_realizefn(CPUState
*cpu
, Error
**errp
);
1130 void cpu_exec_unrealizefn(CPUState
*cpu
);
1133 * target_words_bigendian:
1134 * Returns true if the (default) endianness of the target is big endian,
1135 * false otherwise. Note that in target-specific code, you can use
1136 * TARGET_WORDS_BIGENDIAN directly instead. On the other hand, common
1137 * code should normally never need to know about the endianness of the
1138 * target, so please do *not* use this function unless you know very well
1139 * what you are doing!
1141 bool target_words_bigendian(void);
1145 #ifdef CONFIG_SOFTMMU
1146 extern const VMStateDescription vmstate_cpu_common
;
1148 #define vmstate_cpu_common vmstate_dummy
1151 #define VMSTATE_CPU() { \
1152 .name = "parent_obj", \
1153 .size = sizeof(CPUState), \
1154 .vmsd = &vmstate_cpu_common, \
1155 .flags = VMS_STRUCT, \
1159 #endif /* NEED_CPU_H */
1161 #define UNASSIGNED_CPU_INDEX -1
1162 #define UNASSIGNED_CLUSTER_INDEX -1