include/i2s.h

   1 /*
   2  * Copyright (C) 2012 Samsung Electronics
   3  * R. Chandrasekar <rcsekar@samsung.com>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __I2S_H__
  25 #define __I2S_H__
  26
  27 /*
  28  * DAI hardware audio formats.
  29  *
  30  * Describes the physical PCM data formating and clocking. Add new formats
  31  * to the end.
  32  */
  33 #define SND_SOC_DAIFMT_I2S              1 /* I2S mode */
  34 #define SND_SOC_DAIFMT_RIGHT_J          2 /* Right Justified mode */
  35 #define SND_SOC_DAIFMT_LEFT_J           3 /* Left Justified mode */
  36 #define SND_SOC_DAIFMT_DSP_A            4 /* L data MSB after FRM LRC */
  37 #define SND_SOC_DAIFMT_DSP_B            5 /* L data MSB during FRM LRC */
  38 #define SND_SOC_DAIFMT_AC97             6 /* AC97 */
  39 #define SND_SOC_DAIFMT_PDM              7 /* Pulse density modulation */
  40
  41 /* left and right justified also known as MSB and LSB respectively */
  42 #define SND_SOC_DAIFMT_MSB              SND_SOC_DAIFMT_LEFT_J
  43 #define SND_SOC_DAIFMT_LSB              SND_SOC_DAIFMT_RIGHT_J
  44
  45 /*
  46  * DAI hardware signal inversions.
  47  *
  48  * Specifies whether the DAI can also support inverted clocks for the specified
  49  * format.
  50  */
  51 #define SND_SOC_DAIFMT_NB_NF    (1 << 8) /* normal bit clock + frame */
  52 #define SND_SOC_DAIFMT_NB_IF    (2 << 8) /* normal BCLK + inv FRM */
  53 #define SND_SOC_DAIFMT_IB_NF    (3 << 8) /* invert BCLK + nor FRM */
  54 #define SND_SOC_DAIFMT_IB_IF    (4 << 8) /* invert BCLK + FRM */
  55
  56 /*
  57  * DAI hardware clock masters.
  58  *
  59  * This is wrt the codec, the inverse is true for the interface
  60  * i.e. if the codec is clk and FRM master then the interface is
  61  * clk and frame slave.
  62  */
  63 #define SND_SOC_DAIFMT_CBM_CFM  (1 << 12) /* codec clk & FRM master */
  64 #define SND_SOC_DAIFMT_CBS_CFM  (2 << 12) /* codec clk slave & FRM master */
  65 #define SND_SOC_DAIFMT_CBM_CFS  (3 << 12) /* codec clk master & frame slave */
  66 #define SND_SOC_DAIFMT_CBS_CFS  (4 << 12) /* codec clk & FRM slave */
  67
  68 #define SND_SOC_DAIFMT_FORMAT_MASK      0x000f
  69 #define SND_SOC_DAIFMT_CLOCK_MASK       0x00f0
  70 #define SND_SOC_DAIFMT_INV_MASK         0x0f00
  71 #define SND_SOC_DAIFMT_MASTER_MASK      0xf000
  72
  73 /*
  74  * Master Clock Directions
  75  */
  76 #define SND_SOC_CLOCK_IN                0
  77 #define SND_SOC_CLOCK_OUT               1
  78
  79 /* I2S Tx Control */
  80 #define I2S_TX_ON       1
  81 #define I2S_TX_OFF      0
  82
  83 #define FIFO_LENGTH     64
  84
  85 /* I2s Registers */
  86 struct i2s_reg {
  87         unsigned int con;       /* base + 0 , Control register */
  88         unsigned int mod;       /* Mode register */
  89         unsigned int fic;       /* FIFO control register */
  90         unsigned int psr;       /* Reserved */
  91         unsigned int txd;       /* Transmit data register */
  92         unsigned int rxd;       /* Receive Data Register */
  93 };
  94
  95 /* This structure stores the i2s related information */
  96 struct i2stx_info {
  97         unsigned int rfs;               /* LR clock frame size */
  98         unsigned int bfs;               /* Bit slock frame size */
  99         unsigned int audio_pll_clk;     /* Audio pll frequency in Hz */
 100         unsigned int samplingrate;      /* sampling rate */
 101         unsigned int bitspersample;     /* bits per sample */
 102         unsigned int channels;          /* audio channels */
 103         unsigned int base_address;      /* I2S Register Base */
 104 };
 105
 106 /*
 107  * Sends the given data through i2s tx
 108  *
 109  * @param pi2s_tx       pointer of i2s transmitter parameter structure.
 110  * @param data          address of the data buffer
 111  * @param data_size     array size of the int buffer (total size / size of int)
 112  *
 113  * @return              int value 0 for success, -1 in case of error
 114  */
 115 int i2s_transfer_tx_data(struct i2stx_info *pi2s_tx, unsigned *data,
 116                                 unsigned long data_size);
 117
 118 /*
 119  * Initialise i2s transmiter
 120  *
 121  * @param pi2s_tx       pointer of i2s transmitter parameter structure.
 122  *
 123  * @return              int value 0 for success, -1 in case of error
 124  */
 125 int i2s_tx_init(struct i2stx_info *pi2s_tx);
 126
 127 #endif /* __I2S_H__ */