include/imx8image.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2018 NXP
   4  *
   5  * Peng Fan <peng.fan@nxp.com>
   6  */
   7
   8 #ifndef _IMX8IMAGE_H_
   9 #define _IMX8IMAGE_H_
  10
  11 #include <image.h>
  12 #include <inttypes.h>
  13 #include "imagetool.h"
  14
  15 #define __packed   __attribute__((packed))
  16
  17 #define IV_MAX_LEN                      32
  18 #define HASH_MAX_LEN                    64
  19 #define MAX_NUM_IMGS                    6
  20 #define MAX_NUM_SRK_RECORDS             4
  21
  22 #define IVT_HEADER_TAG_B0               0x87
  23 #define IVT_VERSION_B0                  0x00
  24
  25 #define IMG_FLAG_HASH_SHA256            0x000
  26 #define IMG_FLAG_HASH_SHA384            0x100
  27 #define IMG_FLAG_HASH_SHA512            0x200
  28
  29 #define IMG_FLAG_ENCRYPTED_MASK         0x400
  30 #define IMG_FLAG_ENCRYPTED_SHIFT        0x0A
  31
  32 #define IMG_FLAG_BOOTFLAGS_MASK         0xFFFF0000
  33 #define IMG_FLAG_BOOTFLAGS_SHIFT        0x10
  34
  35 #define IMG_ARRAY_ENTRY_SIZE            128
  36 #define HEADER_IMG_ARRAY_OFFSET         0x10
  37
  38 #define HASH_TYPE_SHA_256               256
  39 #define HASH_TYPE_SHA_384               384
  40 #define HASH_TYPE_SHA_512               512
  41
  42 #define IMAGE_HASH_ALGO_DEFAULT         384
  43 #define IMAGE_PADDING_DEFAULT           0x1000
  44
  45 #define DCD_ENTRY_ADDR_IN_SCFW          0x240
  46
  47 #define CONTAINER_ALIGNMENT             0x400
  48 #define CONTAINER_PQC_ALIGNMENT         0x4000
  49 #define CONTAINER_FLAGS_DEFAULT         0x10
  50 #define CONTAINER_FUSE_DEFAULT          0x0
  51
  52 #define SIGNATURE_BLOCK_HEADER_LENGTH   0x10
  53
  54 #define MAX_NUM_OF_CONTAINER            2
  55
  56 #define FIRST_CONTAINER_HEADER_LENGTH   0x400
  57
  58 #define BOOT_IMG_META_MU_RID_SHIFT      10
  59 #define BOOT_IMG_META_PART_ID_SHIFT     20
  60
  61 #define IMAGE_A35_DEFAULT_META(PART)    (((PART == 0) ? \
  62                                          PARTITION_ID_AP : PART) << \
  63                                          BOOT_IMG_META_PART_ID_SHIFT | \
  64                                          SC_R_MU_0A << \
  65                                          BOOT_IMG_META_MU_RID_SHIFT | \
  66                                          SC_R_A35_0)
  67
  68 #define IMAGE_A53_DEFAULT_META(PART)    (((PART == 0) ? \
  69                                          PARTITION_ID_AP : PART) << \
  70                                          BOOT_IMG_META_PART_ID_SHIFT | \
  71                                          SC_R_MU_0A << \
  72                                          BOOT_IMG_META_MU_RID_SHIFT | \
  73                                          SC_R_A53_0)
  74
  75 #define IMAGE_A72_DEFAULT_META(PART)    (((PART == 0) ? \
  76                                          PARTITION_ID_AP : PART) << \
  77                                          BOOT_IMG_META_PART_ID_SHIFT | \
  78                                          SC_R_MU_0A << \
  79                                          BOOT_IMG_META_MU_RID_SHIFT | \
  80                                          SC_R_A72_0)
  81
  82 #define IMAGE_M4_0_DEFAULT_META(PART)   (((PART == 0) ? \
  83                                          PARTITION_ID_M4 : PART) << \
  84                                          BOOT_IMG_META_PART_ID_SHIFT | \
  85                                          SC_R_M4_0_MU_1A << \
  86                                          BOOT_IMG_META_MU_RID_SHIFT | \
  87                                          SC_R_M4_0_PID0)
  88
  89 #define IMAGE_M4_1_DEFAULT_META(PART)   (((PART == 0) ? \
  90                                          PARTITION_ID_M4 : PART) << \
  91                                          BOOT_IMG_META_PART_ID_SHIFT | \
  92                                          SC_R_M4_1_MU_1A << \
  93                                          BOOT_IMG_META_MU_RID_SHIFT | \
  94                                          SC_R_M4_1_PID0)
  95
  96 #define CONTAINER_IMAGE_ARRAY_START_OFFSET      0x2000
  97
  98 typedef struct {
  99         uint8_t version;
 100         uint16_t length;
 101         uint8_t tag;
 102         uint16_t srk_table_offset;
 103         uint16_t cert_offset;
 104         uint16_t blob_offset;
 105         uint16_t signature_offset;
 106         uint32_t reserved;
 107 } __packed sig_blk_hdr_t;
 108
 109 typedef struct {
 110         uint32_t offset;
 111         uint32_t size;
 112         uint64_t dst;
 113         uint64_t entry;
 114         uint32_t hab_flags;
 115         uint32_t meta;
 116         uint8_t hash[HASH_MAX_LEN];
 117         uint8_t iv[IV_MAX_LEN];
 118 } __packed boot_img_t;
 119
 120 typedef struct {
 121         uint8_t version;
 122         uint16_t length;
 123         uint8_t tag;
 124         uint32_t flags;
 125         uint16_t sw_version;
 126         uint8_t fuse_version;
 127         uint8_t num_images;
 128         uint16_t sig_blk_offset;
 129         uint16_t reserved;
 130         boot_img_t img[MAX_NUM_IMGS];
 131         sig_blk_hdr_t sig_blk_hdr;
 132         uint32_t sigblk_size;
 133         uint32_t padding;
 134 } __packed flash_header_v3_t;
 135
 136 typedef struct {
 137         flash_header_v3_t fhdr[MAX_NUM_OF_CONTAINER];
 138 }  __packed imx_header_v3_t;
 139
 140 struct image_array {
 141         char *name;
 142         unsigned int core_type;
 143         unsigned int core_id;
 144         unsigned int load_addr;
 145 };
 146
 147 enum imx8image_cmd {
 148         CMD_INVALID,
 149         CMD_BOOT_FROM,
 150         CMD_DCD_SKIP,
 151         CMD_FUSE_VERSION,
 152         CMD_SW_VERSION,
 153         CMD_MSG_BLOCK,
 154         CMD_FILEOFF,
 155         CMD_FLAG,
 156         CMD_APPEND,
 157         CMD_PARTITION,
 158         CMD_SOC_TYPE,
 159         CMD_CONTAINER,
 160         CMD_IMAGE,
 161         CMD_DATA,
 162         CMD_DUMMY_V2X,
 163         CMD_HOLD,
 164         CMD_CNTR_VERSION,
 165         CMD_DUMMY_DDR,
 166 };
 167
 168 enum imx8image_core_type {
 169         CFG_CORE_INVALID,
 170         CFG_SCU,
 171         CFG_PWR,
 172         CFG_M40,
 173         CFG_M41,
 174         CFG_A35,
 175         CFG_A55,
 176         CFG_A53,
 177         CFG_A72,
 178         CFG_M33,
 179         CFG_OEI,
 180 };
 181
 182 enum imx8image_fld_types {
 183         CFG_INVALID = -1,
 184         CFG_COMMAND,
 185         CFG_CORE_TYPE,
 186         CFG_IMAGE_NAME,
 187         CFG_LOAD_ADDR
 188 };
 189
 190 typedef enum SOC_TYPE {
 191         NONE = 0,
 192         QX,
 193         QM,
 194         ULP,
 195         IMX9
 196 } soc_type_t;
 197
 198 typedef enum option_type {
 199         NO_IMG = 0,
 200         DCD,
 201         SCFW,
 202         SECO,
 203         M40,
 204         M41,
 205         AP,
 206         OUTPUT,
 207         SCD,
 208         CSF,
 209         FLAG,
 210         DEVICE,
 211         NEW_CONTAINER,
 212         APPEND,
 213         DATA,
 214         PARTITION,
 215         FILEOFF,
 216         MSG_BLOCK,
 217         SENTINEL,
 218         UPOWER,
 219         OEI,
 220         DUMMY_V2X,
 221         HOLD,
 222         CNTR_VERSION,
 223         DUMMY_DDR,
 224 } option_type_t;
 225
 226 typedef struct {
 227         option_type_t option;
 228         char *filename;
 229         uint64_t src;
 230         uint64_t dst;
 231         uint64_t entry;
 232         uint64_t ext;
 233 } image_t;
 234
 235 #define CORE_SC         1
 236 #define CORE_CM4_0      2
 237 #define CORE_CM4_1      3
 238 #define CORE_CA53       4
 239 #define CORE_CA35       4
 240 #define CORE_CA72       5
 241 #define CORE_SECO       6
 242 #define CORE_M33        7
 243
 244 #define CORE_ULP_CM33           0x1
 245 #define CORE_ULP_CA35           0x2
 246 #define CORE_ULP_UPOWER         0x4
 247 #define CORE_ULP_SENTINEL       0x6
 248
 249 #define CORE_IMX95_M33P         0
 250 #define CORE_IMX95_A55C0        2
 251
 252 #define SC_R_OTP        357U
 253 #define SC_R_DEBUG      354U
 254 #define SC_R_ROM_0      236U
 255
 256 #define MSG_DEBUG_EN    SC_R_DEBUG
 257 #define MSG_FUSE        SC_R_OTP
 258 #define MSG_FIELD       SC_R_ROM_0
 259
 260 #define IMG_TYPE_CSF     0x01   /* CSF image type */
 261 #define IMG_TYPE_SCD     0x02   /* SCD image type */
 262 #define IMG_TYPE_EXEC    0x03   /* Executable image type */
 263 #define IMG_TYPE_DATA    0x04   /* Data image type */
 264 #define IMG_TYPE_DCD_DDR 0x05   /* DCD/DDR image type */
 265 #define IMG_TYPE_OEI     0x05   /* Optional Executable image type */
 266 #define IMG_TYPE_SECO    0x06   /* SECO image type */
 267 #define IMG_TYPE_SENTINEL 0x06  /* SENTINEL image type */
 268 #define IMG_TYPE_PROV    0x07   /* Provisioning image type */
 269 #define IMG_TYPE_DEK     0x08   /* DEK validation type */
 270 #define IMG_TYPE_DDR_DUMMY 0x0D /* DDR training data dummy entry */
 271 #define IMG_TYPE_V2X_DUMMY 0x0E /* V2X Dummy image */
 272
 273 #define IMG_TYPE_SHIFT   0
 274 #define IMG_TYPE_MASK    0x1f
 275 #define IMG_TYPE(x)      (((x) & IMG_TYPE_MASK) >> IMG_TYPE_SHIFT)
 276
 277 #define BOOT_IMG_FLAGS_CORE_MASK                0xF
 278 #define BOOT_IMG_FLAGS_CORE_SHIFT               0x04
 279 #define BOOT_IMG_FLAGS_CPU_RID_MASK             0x3FF0
 280 #define BOOT_IMG_FLAGS_CPU_RID_SHIFT            4
 281 #define BOOT_IMG_FLAGS_MU_RID_MASK              0xFFC000
 282 #define BOOT_IMG_FLAGS_MU_RID_SHIFT             14
 283 #define BOOT_IMG_FLAGS_PARTITION_ID_MASK        0x1F000000
 284 #define BOOT_IMG_FLAGS_PARTITION_ID_SHIFT       24
 285
 286 /* Resource id used in scfw */
 287 #define SC_R_A35_0              508
 288 #define SC_R_A53_0              1
 289 #define SC_R_A72_0              6
 290 #define SC_R_MU_0A              213
 291 #define SC_R_M4_0_PID0          278
 292 #define SC_R_M4_0_MU_1A         297
 293 #define SC_R_M4_1_PID0          298
 294 #define SC_R_M4_1_MU_1A         317
 295 #define PARTITION_ID_M4         0
 296 #define PARTITION_ID_AP         1
 297
 298 #define IMG_STACK_SIZE  32
 299
 300 #define append(p, s, l) do { \
 301         memcpy((p), (uint8_t *)(s), (l)); (p) += (l); \
 302         } while (0)
 303
 304 #endif