]> git.ipfire.org Git - thirdparty/linux.git/blob - include/linux/mlx5/driver.h
projects / thirdparty / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge tag 'x86-fpu-2020-06-01' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
[thirdparty/linux.git] / include / linux / mlx5 / driver.h
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX5_DRIVER_H
34 #define MLX5_DRIVER_H
35
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/xarray.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/idr.h>
49 #include <linux/notifier.h>
50 #include <linux/refcount.h>
51
52 #include <linux/mlx5/device.h>
53 #include <linux/mlx5/doorbell.h>
54 #include <linux/mlx5/eq.h>
55 #include <linux/timecounter.h>
56 #include <linux/ptp_clock_kernel.h>
57 #include <net/devlink.h>
58
59 enum {
60 MLX5_BOARD_ID_LEN = 64,
61 };
62
63 enum {
64 /* one minute for the sake of bringup. Generally, commands must always
65 * complete and we may need to increase this timeout value
66 */
67 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000,
68 MLX5_CMD_WQ_MAX_NAME = 32,
69 };
70
71 enum {
72 CMD_OWNER_SW = 0x0,
73 CMD_OWNER_HW = 0x1,
74 CMD_STATUS_SUCCESS = 0,
75 };
76
77 enum mlx5_sqp_t {
78 MLX5_SQP_SMI = 0,
79 MLX5_SQP_GSI = 1,
80 MLX5_SQP_IEEE_1588 = 2,
81 MLX5_SQP_SNIFFER = 3,
82 MLX5_SQP_SYNC_UMR = 4,
83 };
84
85 enum {
86 MLX5_MAX_PORTS = 2,
87 };
88
89 enum {
90 MLX5_ATOMIC_MODE_OFFSET = 16,
91 MLX5_ATOMIC_MODE_IB_COMP = 1,
92 MLX5_ATOMIC_MODE_CX = 2,
93 MLX5_ATOMIC_MODE_8B = 3,
94 MLX5_ATOMIC_MODE_16B = 4,
95 MLX5_ATOMIC_MODE_32B = 5,
96 MLX5_ATOMIC_MODE_64B = 6,
97 MLX5_ATOMIC_MODE_128B = 7,
98 MLX5_ATOMIC_MODE_256B = 8,
99 };
100
101 enum {
102 MLX5_REG_QPTS = 0x4002,
103 MLX5_REG_QETCR = 0x4005,
104 MLX5_REG_QTCT = 0x400a,
105 MLX5_REG_QPDPM = 0x4013,
106 MLX5_REG_QCAM = 0x4019,
107 MLX5_REG_DCBX_PARAM = 0x4020,
108 MLX5_REG_DCBX_APP = 0x4021,
109 MLX5_REG_FPGA_CAP = 0x4022,
110 MLX5_REG_FPGA_CTRL = 0x4023,
111 MLX5_REG_FPGA_ACCESS_REG = 0x4024,
112 MLX5_REG_CORE_DUMP = 0x402e,
113 MLX5_REG_PCAP = 0x5001,
114 MLX5_REG_PMTU = 0x5003,
115 MLX5_REG_PTYS = 0x5004,
116 MLX5_REG_PAOS = 0x5006,
117 MLX5_REG_PFCC = 0x5007,
118 MLX5_REG_PPCNT = 0x5008,
119 MLX5_REG_PPTB = 0x500b,
120 MLX5_REG_PBMC = 0x500c,
121 MLX5_REG_PMAOS = 0x5012,
122 MLX5_REG_PUDE = 0x5009,
123 MLX5_REG_PMPE = 0x5010,
124 MLX5_REG_PELC = 0x500e,
125 MLX5_REG_PVLC = 0x500f,
126 MLX5_REG_PCMR = 0x5041,
127 MLX5_REG_PMLP = 0x5002,
128 MLX5_REG_PPLM = 0x5023,
129 MLX5_REG_PCAM = 0x507f,
130 MLX5_REG_NODE_DESC = 0x6001,
131 MLX5_REG_HOST_ENDIANNESS = 0x7004,
132 MLX5_REG_MCIA = 0x9014,
133 MLX5_REG_MLCR = 0x902b,
134 MLX5_REG_MTRC_CAP = 0x9040,
135 MLX5_REG_MTRC_CONF = 0x9041,
136 MLX5_REG_MTRC_STDB = 0x9042,
137 MLX5_REG_MTRC_CTRL = 0x9043,
138 MLX5_REG_MPEIN = 0x9050,
139 MLX5_REG_MPCNT = 0x9051,
140 MLX5_REG_MTPPS = 0x9053,
141 MLX5_REG_MTPPSE = 0x9054,
142 MLX5_REG_MPEGC = 0x9056,
143 MLX5_REG_MCQS = 0x9060,
144 MLX5_REG_MCQI = 0x9061,
145 MLX5_REG_MCC = 0x9062,
146 MLX5_REG_MCDA = 0x9063,
147 MLX5_REG_MCAM = 0x907f,
148 MLX5_REG_MIRC = 0x9162,
149 MLX5_REG_RESOURCE_DUMP = 0xC000,
150 };
151
152 enum mlx5_qpts_trust_state {
153 MLX5_QPTS_TRUST_PCP = 1,
154 MLX5_QPTS_TRUST_DSCP = 2,
155 };
156
157 enum mlx5_dcbx_oper_mode {
158 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0,
159 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3,
160 };
161
162 enum {
163 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
164 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
165 MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
166 MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
167 };
168
169 enum mlx5_page_fault_resume_flags {
170 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
171 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
172 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
173 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
174 };
175
176 enum dbg_rsc_type {
177 MLX5_DBG_RSC_QP,
178 MLX5_DBG_RSC_EQ,
179 MLX5_DBG_RSC_CQ,
180 };
181
182 enum port_state_policy {
183 MLX5_POLICY_DOWN = 0,
184 MLX5_POLICY_UP = 1,
185 MLX5_POLICY_FOLLOW = 2,
186 MLX5_POLICY_INVALID = 0xffffffff
187 };
188
189 enum mlx5_coredev_type {
190 MLX5_COREDEV_PF,
191 MLX5_COREDEV_VF
192 };
193
194 struct mlx5_field_desc {
195 int i;
196 };
197
198 struct mlx5_rsc_debug {
199 struct mlx5_core_dev *dev;
200 void *object;
201 enum dbg_rsc_type type;
202 struct dentry *root;
203 struct mlx5_field_desc fields[0];
204 };
205
206 enum mlx5_dev_event {
207 MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
208 MLX5_DEV_EVENT_PORT_AFFINITY = 129,
209 };
210
211 enum mlx5_port_status {
212 MLX5_PORT_UP = 1,
213 MLX5_PORT_DOWN = 2,
214 };
215
216 enum mlx5_cmdif_state {
217 MLX5_CMDIF_STATE_UNINITIALIZED,
218 MLX5_CMDIF_STATE_UP,
219 MLX5_CMDIF_STATE_DOWN,
220 };
221
222 struct mlx5_cmd_first {
223 __be32 data[4];
224 };
225
226 struct mlx5_cmd_msg {
227 struct list_head list;
228 struct cmd_msg_cache *parent;
229 u32 len;
230 struct mlx5_cmd_first first;
231 struct mlx5_cmd_mailbox *next;
232 };
233
234 struct mlx5_cmd_debug {
235 struct dentry *dbg_root;
236 void *in_msg;
237 void *out_msg;
238 u8 status;
239 u16 inlen;
240 u16 outlen;
241 };
242
243 struct cmd_msg_cache {
244 /* protect block chain allocations
245 */
246 spinlock_t lock;
247 struct list_head head;
248 unsigned int max_inbox_size;
249 unsigned int num_ent;
250 };
251
252 enum {
253 MLX5_NUM_COMMAND_CACHES = 5,
254 };
255
256 struct mlx5_cmd_stats {
257 u64 sum;
258 u64 n;
259 struct dentry *root;
260 /* protect command average calculations */
261 spinlock_t lock;
262 };
263
264 struct mlx5_cmd {
265 struct mlx5_nb nb;
266
267 enum mlx5_cmdif_state state;
268 void *cmd_alloc_buf;
269 dma_addr_t alloc_dma;
270 int alloc_size;
271 void *cmd_buf;
272 dma_addr_t dma;
273 u16 cmdif_rev;
274 u8 log_sz;
275 u8 log_stride;
276 int max_reg_cmds;
277 int events;
278 u32 __iomem *vector;
279
280 /* protect command queue allocations
281 */
282 spinlock_t alloc_lock;
283
284 /* protect token allocations
285 */
286 spinlock_t token_lock;
287 u8 token;
288 unsigned long bitmask;
289 char wq_name[MLX5_CMD_WQ_MAX_NAME];
290 struct workqueue_struct *wq;
291 struct semaphore sem;
292 struct semaphore pages_sem;
293 int mode;
294 u16 allowed_opcode;
295 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
296 struct dma_pool *pool;
297 struct mlx5_cmd_debug dbg;
298 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
299 int checksum_disabled;
300 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
301 };
302
303 struct mlx5_port_caps {
304 int gid_table_len;
305 int pkey_table_len;
306 u8 ext_port_cap;
307 bool has_smi;
308 };
309
310 struct mlx5_cmd_mailbox {
311 void *buf;
312 dma_addr_t dma;
313 struct mlx5_cmd_mailbox *next;
314 };
315
316 struct mlx5_buf_list {
317 void *buf;
318 dma_addr_t map;
319 };
320
321 struct mlx5_frag_buf {
322 struct mlx5_buf_list *frags;
323 int npages;
324 int size;
325 u8 page_shift;
326 };
327
328 struct mlx5_frag_buf_ctrl {
329 struct mlx5_buf_list *frags;
330 u32 sz_m1;
331 u16 frag_sz_m1;
332 u16 strides_offset;
333 u8 log_sz;
334 u8 log_stride;
335 u8 log_frag_strides;
336 };
337
338 struct mlx5_core_psv {
339 u32 psv_idx;
340 struct psv_layout {
341 u32 pd;
342 u16 syndrome;
343 u16 reserved;
344 u16 bg;
345 u16 app_tag;
346 u32 ref_tag;
347 } psv;
348 };
349
350 struct mlx5_core_sig_ctx {
351 struct mlx5_core_psv psv_memory;
352 struct mlx5_core_psv psv_wire;
353 struct ib_sig_err err_item;
354 bool sig_status_checked;
355 bool sig_err_exists;
356 u32 sigerr_count;
357 };
358
359 enum {
360 MLX5_MKEY_MR = 1,
361 MLX5_MKEY_MW,
362 MLX5_MKEY_INDIRECT_DEVX,
363 };
364
365 struct mlx5_core_mkey {
366 u64 iova;
367 u64 size;
368 u32 key;
369 u32 pd;
370 u32 type;
371 };
372
373 #define MLX5_24BIT_MASK ((1 << 24) - 1)
374
375 enum mlx5_res_type {
376 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
377 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
378 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
379 MLX5_RES_SRQ = 3,
380 MLX5_RES_XSRQ = 4,
381 MLX5_RES_XRQ = 5,
382 MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT,
383 };
384
385 struct mlx5_core_rsc_common {
386 enum mlx5_res_type res;
387 refcount_t refcount;
388 struct completion free;
389 };
390
391 struct mlx5_uars_page {
392 void __iomem *map;
393 bool wc;
394 u32 index;
395 struct list_head list;
396 unsigned int bfregs;
397 unsigned long *reg_bitmap; /* for non fast path bf regs */
398 unsigned long *fp_bitmap;
399 unsigned int reg_avail;
400 unsigned int fp_avail;
401 struct kref ref_count;
402 struct mlx5_core_dev *mdev;
403 };
404
405 struct mlx5_bfreg_head {
406 /* protect blue flame registers allocations */
407 struct mutex lock;
408 struct list_head list;
409 };
410
411 struct mlx5_bfreg_data {
412 struct mlx5_bfreg_head reg_head;
413 struct mlx5_bfreg_head wc_head;
414 };
415
416 struct mlx5_sq_bfreg {
417 void __iomem *map;
418 struct mlx5_uars_page *up;
419 bool wc;
420 u32 index;
421 unsigned int offset;
422 };
423
424 struct mlx5_core_health {
425 struct health_buffer __iomem *health;
426 __be32 __iomem *health_counter;
427 struct timer_list timer;
428 u32 prev;
429 int miss_counter;
430 u8 synd;
431 u32 fatal_error;
432 u32 crdump_size;
433 /* wq spinlock to synchronize draining */
434 spinlock_t wq_lock;
435 struct workqueue_struct *wq;
436 unsigned long flags;
437 struct work_struct fatal_report_work;
438 struct work_struct report_work;
439 struct delayed_work recover_work;
440 struct devlink_health_reporter *fw_reporter;
441 struct devlink_health_reporter *fw_fatal_reporter;
442 };
443
444 struct mlx5_qp_table {
445 struct notifier_block nb;
446
447 /* protect radix tree
448 */
449 spinlock_t lock;
450 struct radix_tree_root tree;
451 };
452
453 struct mlx5_vf_context {
454 int enabled;
455 u64 port_guid;
456 u64 node_guid;
457 /* Valid bits are used to validate administrative guid only.
458 * Enabled after ndo_set_vf_guid
459 */
460 u8 port_guid_valid:1;
461 u8 node_guid_valid:1;
462 enum port_state_policy policy;
463 };
464
465 struct mlx5_core_sriov {
466 struct mlx5_vf_context *vfs_ctx;
467 int num_vfs;
468 u16 max_vfs;
469 };
470
471 struct mlx5_fc_pool {
472 struct mlx5_core_dev *dev;
473 struct mutex pool_lock; /* protects pool lists */
474 struct list_head fully_used;
475 struct list_head partially_used;
476 struct list_head unused;
477 int available_fcs;
478 int used_fcs;
479 int threshold;
480 };
481
482 struct mlx5_fc_stats {
483 spinlock_t counters_idr_lock; /* protects counters_idr */
484 struct idr counters_idr;
485 struct list_head counters;
486 struct llist_head addlist;
487 struct llist_head dellist;
488
489 struct workqueue_struct *wq;
490 struct delayed_work work;
491 unsigned long next_query;
492 unsigned long sampling_interval; /* jiffies */
493 u32 *bulk_query_out;
494 struct mlx5_fc_pool fc_pool;
495 };
496
497 struct mlx5_events;
498 struct mlx5_mpfs;
499 struct mlx5_eswitch;
500 struct mlx5_lag;
501 struct mlx5_devcom;
502 struct mlx5_eq_table;
503 struct mlx5_irq_table;
504
505 struct mlx5_rate_limit {
506 u32 rate;
507 u32 max_burst_sz;
508 u16 typical_pkt_sz;
509 };
510
511 struct mlx5_rl_entry {
512 u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)];
513 u16 index;
514 u64 refcount;
515 u16 uid;
516 u8 dedicated : 1;
517 };
518
519 struct mlx5_rl_table {
520 /* protect rate limit table */
521 struct mutex rl_lock;
522 u16 max_size;
523 u32 max_rate;
524 u32 min_rate;
525 struct mlx5_rl_entry *rl_entry;
526 };
527
528 struct mlx5_core_roce {
529 struct mlx5_flow_table *ft;
530 struct mlx5_flow_group *fg;
531 struct mlx5_flow_handle *allow_rule;
532 };
533
534 struct mlx5_priv {
535 /* IRQ table valid only for real pci devices PF or VF */
536 struct mlx5_irq_table *irq_table;
537 struct mlx5_eq_table *eq_table;
538
539 /* pages stuff */
540 struct mlx5_nb pg_nb;
541 struct workqueue_struct *pg_wq;
542 struct rb_root page_root;
543 int fw_pages;
544 atomic_t reg_pages;
545 struct list_head free_list;
546 int vfs_pages;
547 int peer_pf_pages;
548
549 struct mlx5_core_health health;
550
551 /* start: qp staff */
552 struct mlx5_qp_table qp_table;
553 struct dentry *qp_debugfs;
554 struct dentry *eq_debugfs;
555 struct dentry *cq_debugfs;
556 struct dentry *cmdif_debugfs;
557 /* end: qp staff */
558
559 /* start: alloc staff */
560 /* protect buffer alocation according to numa node */
561 struct mutex alloc_mutex;
562 int numa_node;
563
564 struct mutex pgdir_mutex;
565 struct list_head pgdir_list;
566 /* end: alloc staff */
567 struct dentry *dbg_root;
568
569 struct list_head dev_list;
570 struct list_head ctx_list;
571 spinlock_t ctx_lock;
572 struct mlx5_events *events;
573
574 struct mlx5_flow_steering *steering;
575 struct mlx5_mpfs *mpfs;
576 struct mlx5_eswitch *eswitch;
577 struct mlx5_core_sriov sriov;
578 struct mlx5_lag *lag;
579 struct mlx5_devcom *devcom;
580 struct mlx5_core_roce roce;
581 struct mlx5_fc_stats fc_stats;
582 struct mlx5_rl_table rl_table;
583
584 struct mlx5_bfreg_data bfregs;
585 struct mlx5_uars_page *uar;
586 };
587
588 enum mlx5_device_state {
589 MLX5_DEVICE_STATE_UNINITIALIZED,
590 MLX5_DEVICE_STATE_UP,
591 MLX5_DEVICE_STATE_INTERNAL_ERROR,
592 };
593
594 enum mlx5_interface_state {
595 MLX5_INTERFACE_STATE_UP = BIT(0),
596 };
597
598 enum mlx5_pci_status {
599 MLX5_PCI_STATUS_DISABLED,
600 MLX5_PCI_STATUS_ENABLED,
601 };
602
603 enum mlx5_pagefault_type_flags {
604 MLX5_PFAULT_REQUESTOR = 1 << 0,
605 MLX5_PFAULT_WRITE = 1 << 1,
606 MLX5_PFAULT_RDMA = 1 << 2,
607 };
608
609 struct mlx5_td {
610 /* protects tirs list changes while tirs refresh */
611 struct mutex list_lock;
612 struct list_head tirs_list;
613 u32 tdn;
614 };
615
616 struct mlx5e_resources {
617 u32 pdn;
618 struct mlx5_td td;
619 struct mlx5_core_mkey mkey;
620 struct mlx5_sq_bfreg bfreg;
621 };
622
623 enum mlx5_sw_icm_type {
624 MLX5_SW_ICM_TYPE_STEERING,
625 MLX5_SW_ICM_TYPE_HEADER_MODIFY,
626 };
627
628 #define MLX5_MAX_RESERVED_GIDS 8
629
630 struct mlx5_rsvd_gids {
631 unsigned int start;
632 unsigned int count;
633 struct ida ida;
634 };
635
636 #define MAX_PIN_NUM 8
637 struct mlx5_pps {
638 u8 pin_caps[MAX_PIN_NUM];
639 struct work_struct out_work;
640 u64 start[MAX_PIN_NUM];
641 u8 enabled;
642 };
643
644 struct mlx5_clock {
645 struct mlx5_core_dev *mdev;
646 struct mlx5_nb pps_nb;
647 seqlock_t lock;
648 struct cyclecounter cycles;
649 struct timecounter tc;
650 struct hwtstamp_config hwtstamp_config;
651 u32 nominal_c_mult;
652 unsigned long overflow_period;
653 struct delayed_work overflow_work;
654 struct ptp_clock *ptp;
655 struct ptp_clock_info ptp_info;
656 struct mlx5_pps pps_info;
657 };
658
659 struct mlx5_dm;
660 struct mlx5_fw_tracer;
661 struct mlx5_vxlan;
662 struct mlx5_geneve;
663 struct mlx5_hv_vhca;
664
665 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
666 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
667
668 struct mlx5_core_dev {
669 struct device *device;
670 enum mlx5_coredev_type coredev_type;
671 struct pci_dev *pdev;
672 /* sync pci state */
673 struct mutex pci_status_mutex;
674 enum mlx5_pci_status pci_status;
675 u8 rev_id;
676 char board_id[MLX5_BOARD_ID_LEN];
677 struct mlx5_cmd cmd;
678 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
679 struct {
680 u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
681 u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
682 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
683 u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
684 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
685 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
686 u8 embedded_cpu;
687 } caps;
688 u64 sys_image_guid;
689 phys_addr_t iseg_base;
690 struct mlx5_init_seg __iomem *iseg;
691 phys_addr_t bar_addr;
692 enum mlx5_device_state state;
693 /* sync interface state */
694 struct mutex intf_state_mutex;
695 unsigned long intf_state;
696 struct mlx5_priv priv;
697 struct mlx5_profile *profile;
698 atomic_t num_qps;
699 u32 issi;
700 struct mlx5e_resources mlx5e_res;
701 struct mlx5_dm *dm;
702 struct mlx5_vxlan *vxlan;
703 struct mlx5_geneve *geneve;
704 struct {
705 struct mlx5_rsvd_gids reserved_gids;
706 u32 roce_en;
707 } roce;
708 #ifdef CONFIG_MLX5_FPGA
709 struct mlx5_fpga_device *fpga;
710 #endif
711 struct mlx5_clock clock;
712 struct mlx5_ib_clock_info *clock_info;
713 struct mlx5_fw_tracer *tracer;
714 struct mlx5_rsc_dump *rsc_dump;
715 u32 vsc_addr;
716 struct mlx5_hv_vhca *hv_vhca;
717 };
718
719 struct mlx5_db {
720 __be32 *db;
721 union {
722 struct mlx5_db_pgdir *pgdir;
723 struct mlx5_ib_user_db_page *user_page;
724 } u;
725 dma_addr_t dma;
726 int index;
727 };
728
729 enum {
730 MLX5_COMP_EQ_SIZE = 1024,
731 };
732
733 enum {
734 MLX5_PTYS_IB = 1 << 0,
735 MLX5_PTYS_EN = 1 << 2,
736 };
737
738 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
739
740 enum {
741 MLX5_CMD_ENT_STATE_PENDING_COMP,
742 };
743
744 struct mlx5_cmd_work_ent {
745 unsigned long state;
746 struct mlx5_cmd_msg *in;
747 struct mlx5_cmd_msg *out;
748 void *uout;
749 int uout_size;
750 mlx5_cmd_cbk_t callback;
751 struct delayed_work cb_timeout_work;
752 void *context;
753 int idx;
754 struct completion handling;
755 struct completion done;
756 struct mlx5_cmd *cmd;
757 struct work_struct work;
758 struct mlx5_cmd_layout *lay;
759 int ret;
760 int page_queue;
761 u8 status;
762 u8 token;
763 u64 ts1;
764 u64 ts2;
765 u16 op;
766 bool polling;
767 };
768
769 struct mlx5_pas {
770 u64 pa;
771 u8 log_sz;
772 };
773
774 enum phy_port_state {
775 MLX5_AAA_111
776 };
777
778 struct mlx5_hca_vport_context {
779 u32 field_select;
780 bool sm_virt_aware;
781 bool has_smi;
782 bool has_raw;
783 enum port_state_policy policy;
784 enum phy_port_state phys_state;
785 enum ib_port_state vport_state;
786 u8 port_physical_state;
787 u64 sys_image_guid;
788 u64 port_guid;
789 u64 node_guid;
790 u32 cap_mask1;
791 u32 cap_mask1_perm;
792 u16 cap_mask2;
793 u16 cap_mask2_perm;
794 u16 lid;
795 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
796 u8 lmc;
797 u8 subnet_timeout;
798 u16 sm_lid;
799 u8 sm_sl;
800 u16 qkey_violation_counter;
801 u16 pkey_violation_counter;
802 bool grh_required;
803 };
804
805 static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset)
806 {
807 return buf->frags->buf + offset;
808 }
809
810 #define STRUCT_FIELD(header, field) \
811 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
812 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
813
814 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
815 {
816 return pci_get_drvdata(pdev);
817 }
818
819 extern struct dentry *mlx5_debugfs_root;
820
821 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
822 {
823 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
824 }
825
826 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
827 {
828 return ioread32be(&dev->iseg->fw_rev) >> 16;
829 }
830
831 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
832 {
833 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
834 }
835
836 static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
837 {
838 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
839 }
840
841 static inline u32 mlx5_base_mkey(const u32 key)
842 {
843 return key & 0xffffff00u;
844 }
845
846 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
847 u8 log_stride, u8 log_sz,
848 u16 strides_offset,
849 struct mlx5_frag_buf_ctrl *fbc)
850 {
851 fbc->frags = frags;
852 fbc->log_stride = log_stride;
853 fbc->log_sz = log_sz;
854 fbc->sz_m1 = (1 << fbc->log_sz) - 1;
855 fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
856 fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1;
857 fbc->strides_offset = strides_offset;
858 }
859
860 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
861 u8 log_stride, u8 log_sz,
862 struct mlx5_frag_buf_ctrl *fbc)
863 {
864 mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc);
865 }
866
867 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
868 u32 ix)
869 {
870 unsigned int frag;
871
872 ix += fbc->strides_offset;
873 frag = ix >> fbc->log_frag_strides;
874
875 return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
876 }
877
878 static inline u32
879 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
880 {
881 u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
882
883 return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
884 }
885
886 enum {
887 CMD_ALLOWED_OPCODE_ALL,
888 };
889
890 int mlx5_cmd_init(struct mlx5_core_dev *dev);
891 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
892 void mlx5_cmd_set_state(struct mlx5_core_dev *dev,
893 enum mlx5_cmdif_state cmdif_state);
894 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
895 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
896 void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);
897
898 struct mlx5_async_ctx {
899 struct mlx5_core_dev *dev;
900 atomic_t num_inflight;
901 struct wait_queue_head wait;
902 };
903
904 struct mlx5_async_work;
905
906 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
907
908 struct mlx5_async_work {
909 struct mlx5_async_ctx *ctx;
910 mlx5_async_cbk_t user_callback;
911 };
912
913 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
914 struct mlx5_async_ctx *ctx);
915 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
916 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
917 void *out, int out_size, mlx5_async_cbk_t callback,
918 struct mlx5_async_work *work);
919
920 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
921 int out_size);
922 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
923 void *out, int out_size);
924 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
925
926 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
927 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
928 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
929 void mlx5_health_flush(struct mlx5_core_dev *dev);
930 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
931 int mlx5_health_init(struct mlx5_core_dev *dev);
932 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
933 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
934 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
935 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
936 int mlx5_buf_alloc(struct mlx5_core_dev *dev,
937 int size, struct mlx5_frag_buf *buf);
938 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
939 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
940 struct mlx5_frag_buf *buf, int node);
941 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
942 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
943 gfp_t flags, int npages);
944 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
945 struct mlx5_cmd_mailbox *head);
946 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
947 struct mlx5_core_mkey *mkey,
948 u32 *in, int inlen);
949 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
950 struct mlx5_core_mkey *mkey);
951 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
952 u32 *out, int outlen);
953 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
954 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
955 int mlx5_pagealloc_init(struct mlx5_core_dev *dev);
956 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
957 void mlx5_pagealloc_start(struct mlx5_core_dev *dev);
958 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
959 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
960 s32 npages, bool ec_function);
961 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
962 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
963 void mlx5_register_debugfs(void);
964 void mlx5_unregister_debugfs(void);
965
966 void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas);
967 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
968 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
969 unsigned int *irqn);
970 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
971 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
972
973 void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
974 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
975 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
976 int size_in, void *data_out, int size_out,
977 u16 reg_num, int arg, int write);
978
979 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
980 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
981 int node);
982 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
983
984 const char *mlx5_command_str(int command);
985 void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
986 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
987 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
988 int npsvs, u32 *sig_index);
989 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
990 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
991 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
992 struct mlx5_odp_caps *odp_caps);
993 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
994 u8 port_num, void *out, size_t sz);
995
996 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
997 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
998 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
999 struct mlx5_rate_limit *rl);
1000 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1001 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1002 int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
1003 bool dedicated_entry, u16 *index);
1004 void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index);
1005 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1006 struct mlx5_rate_limit *rl_1);
1007 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1008 bool map_wc, bool fast_path);
1009 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1010
1011 unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev);
1012 struct cpumask *
1013 mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector);
1014 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1015 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1016 u8 roce_version, u8 roce_l3_type, const u8 *gid,
1017 const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1018
1019 static inline int fw_initializing(struct mlx5_core_dev *dev)
1020 {
1021 return ioread32be(&dev->iseg->initializing) >> 31;
1022 }
1023
1024 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1025 {
1026 return mkey >> 8;
1027 }
1028
1029 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1030 {
1031 return mkey_idx << 8;
1032 }
1033
1034 static inline u8 mlx5_mkey_variant(u32 mkey)
1035 {
1036 return mkey & 0xff;
1037 }
1038
1039 enum {
1040 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
1041 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
1042 };
1043
1044 enum {
1045 MR_CACHE_LAST_STD_ENTRY = 20,
1046 MLX5_IMR_MTT_CACHE_ENTRY,
1047 MLX5_IMR_KSM_CACHE_ENTRY,
1048 MAX_MR_CACHE_ENTRIES
1049 };
1050
1051 enum {
1052 MLX5_INTERFACE_PROTOCOL_IB = 0,
1053 MLX5_INTERFACE_PROTOCOL_ETH = 1,
1054 };
1055
1056 struct mlx5_interface {
1057 void * (*add)(struct mlx5_core_dev *dev);
1058 void (*remove)(struct mlx5_core_dev *dev, void *context);
1059 int (*attach)(struct mlx5_core_dev *dev, void *context);
1060 void (*detach)(struct mlx5_core_dev *dev, void *context);
1061 int protocol;
1062 struct list_head list;
1063 };
1064
1065 int mlx5_register_interface(struct mlx5_interface *intf);
1066 void mlx5_unregister_interface(struct mlx5_interface *intf);
1067 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1068 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1069 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1070 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1071
1072 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1073
1074 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1075 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1076 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
1077 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
1078 bool mlx5_lag_is_multipath(struct mlx5_core_dev *dev);
1079 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1080 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1081 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1082 u64 *values,
1083 int num_counters,
1084 size_t *offsets);
1085 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1086 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1087 int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1088 u64 length, u16 uid, phys_addr_t *addr, u32 *obj_id);
1089 int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1090 u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
1091
1092 #ifdef CONFIG_MLX5_CORE_IPOIB
1093 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1094 struct ib_device *ibdev,
1095 const char *name,
1096 void (*setup)(struct net_device *));
1097 #endif /* CONFIG_MLX5_CORE_IPOIB */
1098 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
1099 struct ib_device *device,
1100 struct rdma_netdev_alloc_params *params);
1101
1102 struct mlx5_profile {
1103 u64 mask;
1104 u8 log_max_qp;
1105 struct {
1106 int size;
1107 int limit;
1108 } mr_cache[MAX_MR_CACHE_ENTRIES];
1109 };
1110
1111 enum {
1112 MLX5_PCI_DEV_IS_VF = 1 << 0,
1113 };
1114
1115 static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
1116 {
1117 return dev->coredev_type == MLX5_COREDEV_PF;
1118 }
1119
1120 static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
1121 {
1122 return dev->coredev_type == MLX5_COREDEV_VF;
1123 }
1124
1125 static inline bool mlx5_core_is_ecpf(struct mlx5_core_dev *dev)
1126 {
1127 return dev->caps.embedded_cpu;
1128 }
1129
1130 static inline bool
1131 mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
1132 {
1133 return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1134 }
1135
1136 static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
1137 {
1138 return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1139 }
1140
1141 static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
1142 {
1143 return dev->priv.sriov.max_vfs;
1144 }
1145
1146 static inline int mlx5_get_gid_table_len(u16 param)
1147 {
1148 if (param > 4) {
1149 pr_warn("gid table length is zero\n");
1150 return 0;
1151 }
1152
1153 return 8 * (1 << param);
1154 }
1155
1156 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1157 {
1158 return !!(dev->priv.rl_table.max_size);
1159 }
1160
1161 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1162 {
1163 return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1164 MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1165 }
1166
1167 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1168 {
1169 return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1170 }
1171
1172 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1173 {
1174 return mlx5_core_is_mp_slave(dev) ||
1175 mlx5_core_is_mp_master(dev);
1176 }
1177
1178 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1179 {
1180 if (!mlx5_core_mp_enabled(dev))
1181 return 1;
1182
1183 return MLX5_CAP_GEN(dev, native_port_num);
1184 }
1185
1186 enum {
1187 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1188 };
1189
1190 static inline bool mlx5_is_roce_enabled(struct mlx5_core_dev *dev)
1191 {
1192 struct devlink *devlink = priv_to_devlink(dev);
1193 union devlink_param_value val;
1194
1195 devlink_param_driverinit_value_get(devlink,
1196 DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE,
1197 &val);
1198 return val.vbool;
1199 }
1200
1201 #endif /* MLX5_DRIVER_H */
A mirror of Linus' kernel repository