2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/radix-tree.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/idr.h>
50 #include <linux/mlx5/device.h>
51 #include <linux/mlx5/doorbell.h>
52 #include <linux/mlx5/srq.h>
53 #include <linux/timecounter.h>
54 #include <linux/ptp_clock_kernel.h>
57 MLX5_BOARD_ID_LEN
= 64,
58 MLX5_MAX_NAME_LEN
= 16,
62 /* one minute for the sake of bringup. Generally, commands must always
63 * complete and we may need to increase this timeout value
65 MLX5_CMD_TIMEOUT_MSEC
= 60 * 1000,
66 MLX5_CMD_WQ_MAX_NAME
= 32,
72 CMD_STATUS_SUCCESS
= 0,
78 MLX5_SQP_IEEE_1588
= 2,
80 MLX5_SQP_SYNC_UMR
= 4,
88 MLX5_EQ_VEC_PAGES
= 0,
90 MLX5_EQ_VEC_ASYNC
= 2,
91 MLX5_EQ_VEC_PFAULT
= 3,
92 MLX5_EQ_VEC_COMP_BASE
,
96 MLX5_MAX_IRQ_NAME
= 32
100 MLX5_ATOMIC_MODE_IB_COMP
= 1 << 16,
101 MLX5_ATOMIC_MODE_CX
= 2 << 16,
102 MLX5_ATOMIC_MODE_8B
= 3 << 16,
103 MLX5_ATOMIC_MODE_16B
= 4 << 16,
104 MLX5_ATOMIC_MODE_32B
= 5 << 16,
105 MLX5_ATOMIC_MODE_64B
= 6 << 16,
106 MLX5_ATOMIC_MODE_128B
= 7 << 16,
107 MLX5_ATOMIC_MODE_256B
= 8 << 16,
111 MLX5_REG_QPTS
= 0x4002,
112 MLX5_REG_QETCR
= 0x4005,
113 MLX5_REG_QTCT
= 0x400a,
114 MLX5_REG_QPDPM
= 0x4013,
115 MLX5_REG_QCAM
= 0x4019,
116 MLX5_REG_DCBX_PARAM
= 0x4020,
117 MLX5_REG_DCBX_APP
= 0x4021,
118 MLX5_REG_FPGA_CAP
= 0x4022,
119 MLX5_REG_FPGA_CTRL
= 0x4023,
120 MLX5_REG_FPGA_ACCESS_REG
= 0x4024,
121 MLX5_REG_PCAP
= 0x5001,
122 MLX5_REG_PMTU
= 0x5003,
123 MLX5_REG_PTYS
= 0x5004,
124 MLX5_REG_PAOS
= 0x5006,
125 MLX5_REG_PFCC
= 0x5007,
126 MLX5_REG_PPCNT
= 0x5008,
127 MLX5_REG_PPTB
= 0x500b,
128 MLX5_REG_PBMC
= 0x500c,
129 MLX5_REG_PMAOS
= 0x5012,
130 MLX5_REG_PUDE
= 0x5009,
131 MLX5_REG_PMPE
= 0x5010,
132 MLX5_REG_PELC
= 0x500e,
133 MLX5_REG_PVLC
= 0x500f,
134 MLX5_REG_PCMR
= 0x5041,
135 MLX5_REG_PMLP
= 0x5002,
136 MLX5_REG_PCAM
= 0x507f,
137 MLX5_REG_NODE_DESC
= 0x6001,
138 MLX5_REG_HOST_ENDIANNESS
= 0x7004,
139 MLX5_REG_MCIA
= 0x9014,
140 MLX5_REG_MLCR
= 0x902b,
141 MLX5_REG_MTRC_CAP
= 0x9040,
142 MLX5_REG_MTRC_CONF
= 0x9041,
143 MLX5_REG_MTRC_STDB
= 0x9042,
144 MLX5_REG_MTRC_CTRL
= 0x9043,
145 MLX5_REG_MPCNT
= 0x9051,
146 MLX5_REG_MTPPS
= 0x9053,
147 MLX5_REG_MTPPSE
= 0x9054,
148 MLX5_REG_MPEGC
= 0x9056,
149 MLX5_REG_MCQI
= 0x9061,
150 MLX5_REG_MCC
= 0x9062,
151 MLX5_REG_MCDA
= 0x9063,
152 MLX5_REG_MCAM
= 0x907f,
155 enum mlx5_qpts_trust_state
{
156 MLX5_QPTS_TRUST_PCP
= 1,
157 MLX5_QPTS_TRUST_DSCP
= 2,
160 enum mlx5_dcbx_oper_mode
{
161 MLX5E_DCBX_PARAM_VER_OPER_HOST
= 0x0,
162 MLX5E_DCBX_PARAM_VER_OPER_AUTO
= 0x3,
165 enum mlx5_dct_atomic_mode
{
166 MLX5_ATOMIC_MODE_DCT_OFF
= 20,
167 MLX5_ATOMIC_MODE_DCT_NONE
= 0 << MLX5_ATOMIC_MODE_DCT_OFF
,
168 MLX5_ATOMIC_MODE_DCT_IB_COMP
= 1 << MLX5_ATOMIC_MODE_DCT_OFF
,
169 MLX5_ATOMIC_MODE_DCT_CX
= 2 << MLX5_ATOMIC_MODE_DCT_OFF
,
173 MLX5_ATOMIC_OPS_CMP_SWAP
= 1 << 0,
174 MLX5_ATOMIC_OPS_FETCH_ADD
= 1 << 1,
177 enum mlx5_page_fault_resume_flags
{
178 MLX5_PAGE_FAULT_RESUME_REQUESTOR
= 1 << 0,
179 MLX5_PAGE_FAULT_RESUME_WRITE
= 1 << 1,
180 MLX5_PAGE_FAULT_RESUME_RDMA
= 1 << 2,
181 MLX5_PAGE_FAULT_RESUME_ERROR
= 1 << 7,
190 enum port_state_policy
{
191 MLX5_POLICY_DOWN
= 0,
193 MLX5_POLICY_FOLLOW
= 2,
194 MLX5_POLICY_INVALID
= 0xffffffff
197 struct mlx5_field_desc
{
202 struct mlx5_rsc_debug
{
203 struct mlx5_core_dev
*dev
;
205 enum dbg_rsc_type type
;
207 struct mlx5_field_desc fields
[0];
210 enum mlx5_dev_event
{
211 MLX5_DEV_EVENT_SYS_ERROR
,
212 MLX5_DEV_EVENT_PORT_UP
,
213 MLX5_DEV_EVENT_PORT_DOWN
,
214 MLX5_DEV_EVENT_PORT_INITIALIZED
,
215 MLX5_DEV_EVENT_LID_CHANGE
,
216 MLX5_DEV_EVENT_PKEY_CHANGE
,
217 MLX5_DEV_EVENT_GUID_CHANGE
,
218 MLX5_DEV_EVENT_CLIENT_REREG
,
220 MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT
,
223 enum mlx5_port_status
{
231 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
236 struct mlx5_bfreg_info
{
238 int num_low_latency_bfregs
;
242 * protect bfreg allocation data structs
248 u32 num_static_sys_pages
;
249 u32 total_num_bfregs
;
253 struct mlx5_cmd_first
{
257 struct mlx5_cmd_msg
{
258 struct list_head list
;
259 struct cmd_msg_cache
*parent
;
261 struct mlx5_cmd_first first
;
262 struct mlx5_cmd_mailbox
*next
;
265 struct mlx5_cmd_debug
{
266 struct dentry
*dbg_root
;
267 struct dentry
*dbg_in
;
268 struct dentry
*dbg_out
;
269 struct dentry
*dbg_outlen
;
270 struct dentry
*dbg_status
;
271 struct dentry
*dbg_run
;
279 struct cmd_msg_cache
{
280 /* protect block chain allocations
283 struct list_head head
;
284 unsigned int max_inbox_size
;
285 unsigned int num_ent
;
289 MLX5_NUM_COMMAND_CACHES
= 5,
292 struct mlx5_cmd_stats
{
297 struct dentry
*count
;
298 /* protect command average calculations */
304 dma_addr_t alloc_dma
;
315 /* protect command queue allocations
317 spinlock_t alloc_lock
;
319 /* protect token allocations
321 spinlock_t token_lock
;
323 unsigned long bitmask
;
324 char wq_name
[MLX5_CMD_WQ_MAX_NAME
];
325 struct workqueue_struct
*wq
;
326 struct semaphore sem
;
327 struct semaphore pages_sem
;
329 struct mlx5_cmd_work_ent
*ent_arr
[MLX5_MAX_COMMANDS
];
330 struct dma_pool
*pool
;
331 struct mlx5_cmd_debug dbg
;
332 struct cmd_msg_cache cache
[MLX5_NUM_COMMAND_CACHES
];
333 int checksum_disabled
;
334 struct mlx5_cmd_stats stats
[MLX5_CMD_OP_MAX
];
337 struct mlx5_port_caps
{
344 struct mlx5_cmd_mailbox
{
347 struct mlx5_cmd_mailbox
*next
;
350 struct mlx5_buf_list
{
355 struct mlx5_frag_buf
{
356 struct mlx5_buf_list
*frags
;
362 struct mlx5_frag_buf_ctrl
{
363 struct mlx5_frag_buf frag_buf
;
372 struct mlx5_eq_tasklet
{
373 struct list_head list
;
374 struct list_head process_list
;
375 struct tasklet_struct task
;
376 /* lock on completion tasklet list */
380 struct mlx5_eq_pagefault
{
381 struct work_struct work
;
382 /* Pagefaults lock */
384 struct workqueue_struct
*wq
;
388 struct mlx5_cq_table
{
389 /* protect radix tree */
391 struct radix_tree_root tree
;
395 struct mlx5_core_dev
*dev
;
396 struct mlx5_cq_table cq_table
;
397 __be32 __iomem
*doorbell
;
399 struct mlx5_frag_buf buf
;
405 struct list_head list
;
407 struct mlx5_rsc_debug
*dbg
;
408 enum mlx5_eq_type type
;
410 struct mlx5_eq_tasklet tasklet_ctx
;
411 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
412 struct mlx5_eq_pagefault pf_ctx
;
417 struct mlx5_core_psv
{
429 struct mlx5_core_sig_ctx
{
430 struct mlx5_core_psv psv_memory
;
431 struct mlx5_core_psv psv_wire
;
432 struct ib_sig_err err_item
;
433 bool sig_status_checked
;
443 struct mlx5_core_mkey
{
451 #define MLX5_24BIT_MASK ((1 << 24) - 1)
454 MLX5_RES_QP
= MLX5_EVENT_QUEUE_TYPE_QP
,
455 MLX5_RES_RQ
= MLX5_EVENT_QUEUE_TYPE_RQ
,
456 MLX5_RES_SQ
= MLX5_EVENT_QUEUE_TYPE_SQ
,
460 MLX5_RES_DCT
= MLX5_EVENT_QUEUE_TYPE_DCT
,
463 struct mlx5_core_rsc_common
{
464 enum mlx5_res_type res
;
466 struct completion free
;
469 struct mlx5_core_srq
{
470 struct mlx5_core_rsc_common common
; /* must be first */
474 size_t max_avail_gather
;
476 void (*event
) (struct mlx5_core_srq
*, enum mlx5_event
);
479 struct completion free
;
482 struct mlx5_eq_table
{
483 void __iomem
*update_ci
;
484 void __iomem
*update_arm_ci
;
485 struct list_head comp_eqs_list
;
486 struct mlx5_eq pages_eq
;
487 struct mlx5_eq async_eq
;
488 struct mlx5_eq cmd_eq
;
489 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
490 struct mlx5_eq pfault_eq
;
492 int num_comp_vectors
;
498 struct mlx5_uars_page
{
502 struct list_head list
;
504 unsigned long *reg_bitmap
; /* for non fast path bf regs */
505 unsigned long *fp_bitmap
;
506 unsigned int reg_avail
;
507 unsigned int fp_avail
;
508 struct kref ref_count
;
509 struct mlx5_core_dev
*mdev
;
512 struct mlx5_bfreg_head
{
513 /* protect blue flame registers allocations */
515 struct list_head list
;
518 struct mlx5_bfreg_data
{
519 struct mlx5_bfreg_head reg_head
;
520 struct mlx5_bfreg_head wc_head
;
523 struct mlx5_sq_bfreg
{
525 struct mlx5_uars_page
*up
;
531 struct mlx5_core_health
{
532 struct health_buffer __iomem
*health
;
533 __be32 __iomem
*health_counter
;
534 struct timer_list timer
;
538 /* wq spinlock to synchronize draining */
540 struct workqueue_struct
*wq
;
542 struct work_struct work
;
543 struct delayed_work recover_work
;
546 struct mlx5_qp_table
{
547 /* protect radix tree
550 struct radix_tree_root tree
;
553 struct mlx5_srq_table
{
554 /* protect radix tree
557 struct radix_tree_root tree
;
560 struct mlx5_mkey_table
{
561 /* protect radix tree
564 struct radix_tree_root tree
;
567 struct mlx5_vf_context
{
571 enum port_state_policy policy
;
574 struct mlx5_core_sriov
{
575 struct mlx5_vf_context
*vfs_ctx
;
580 struct mlx5_irq_info
{
582 char name
[MLX5_MAX_IRQ_NAME
];
585 struct mlx5_fc_stats
{
586 struct rb_root counters
;
587 struct list_head addlist
;
588 /* protect addlist add/splice operations */
589 spinlock_t addlist_lock
;
591 struct workqueue_struct
*wq
;
592 struct delayed_work work
;
593 unsigned long next_query
;
594 unsigned long sampling_interval
; /* jiffies */
600 struct mlx5_pagefault
;
602 struct mlx5_rate_limit
{
608 struct mlx5_rl_entry
{
609 struct mlx5_rate_limit rl
;
614 struct mlx5_rl_table
{
615 /* protect rate limit table */
616 struct mutex rl_lock
;
620 struct mlx5_rl_entry
*rl_entry
;
623 enum port_module_event_status_type
{
624 MLX5_MODULE_STATUS_PLUGGED
= 0x1,
625 MLX5_MODULE_STATUS_UNPLUGGED
= 0x2,
626 MLX5_MODULE_STATUS_ERROR
= 0x3,
627 MLX5_MODULE_STATUS_NUM
= 0x3,
630 enum port_module_event_error_type
{
631 MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED
,
632 MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE
,
633 MLX5_MODULE_EVENT_ERROR_BUS_STUCK
,
634 MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT
,
635 MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST
,
636 MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER
,
637 MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE
,
638 MLX5_MODULE_EVENT_ERROR_BAD_CABLE
,
639 MLX5_MODULE_EVENT_ERROR_UNKNOWN
,
640 MLX5_MODULE_EVENT_ERROR_NUM
,
643 struct mlx5_port_module_event_stats
{
644 u64 status_counters
[MLX5_MODULE_STATUS_NUM
];
645 u64 error_counters
[MLX5_MODULE_EVENT_ERROR_NUM
];
649 char name
[MLX5_MAX_NAME_LEN
];
650 struct mlx5_eq_table eq_table
;
651 struct mlx5_irq_info
*irq_info
;
654 struct workqueue_struct
*pg_wq
;
655 struct rb_root page_root
;
658 struct list_head free_list
;
661 struct mlx5_core_health health
;
663 struct mlx5_srq_table srq_table
;
665 /* start: qp staff */
666 struct mlx5_qp_table qp_table
;
667 struct dentry
*qp_debugfs
;
668 struct dentry
*eq_debugfs
;
669 struct dentry
*cq_debugfs
;
670 struct dentry
*cmdif_debugfs
;
673 /* start: mkey staff */
674 struct mlx5_mkey_table mkey_table
;
675 /* end: mkey staff */
677 /* start: alloc staff */
678 /* protect buffer alocation according to numa node */
679 struct mutex alloc_mutex
;
682 struct mutex pgdir_mutex
;
683 struct list_head pgdir_list
;
684 /* end: alloc staff */
685 struct dentry
*dbg_root
;
687 /* protect mkey key part */
688 spinlock_t mkey_lock
;
691 struct list_head dev_list
;
692 struct list_head ctx_list
;
695 struct list_head waiting_events_list
;
696 bool is_accum_events
;
698 struct mlx5_flow_steering
*steering
;
699 struct mlx5_mpfs
*mpfs
;
700 struct mlx5_eswitch
*eswitch
;
701 struct mlx5_core_sriov sriov
;
702 struct mlx5_lag
*lag
;
703 unsigned long pci_dev_data
;
704 struct mlx5_fc_stats fc_stats
;
705 struct mlx5_rl_table rl_table
;
707 struct mlx5_port_module_event_stats pme_stats
;
709 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
710 void (*pfault
)(struct mlx5_core_dev
*dev
,
712 struct mlx5_pagefault
*pfault
);
714 struct srcu_struct pfault_srcu
;
716 struct mlx5_bfreg_data bfregs
;
717 struct mlx5_uars_page
*uar
;
720 enum mlx5_device_state
{
721 MLX5_DEVICE_STATE_UP
,
722 MLX5_DEVICE_STATE_INTERNAL_ERROR
,
725 enum mlx5_interface_state
{
726 MLX5_INTERFACE_STATE_UP
= BIT(0),
729 enum mlx5_pci_status
{
730 MLX5_PCI_STATUS_DISABLED
,
731 MLX5_PCI_STATUS_ENABLED
,
734 enum mlx5_pagefault_type_flags
{
735 MLX5_PFAULT_REQUESTOR
= 1 << 0,
736 MLX5_PFAULT_WRITE
= 1 << 1,
737 MLX5_PFAULT_RDMA
= 1 << 2,
740 /* Contains the details of a pagefault. */
741 struct mlx5_pagefault
{
747 /* Initiator or send message responder pagefault details. */
749 /* Received packet size, only valid for responders. */
752 * Number of resource holding WQE, depends on type.
756 * WQE index. Refers to either the send queue or
757 * receive queue, according to event_subtype.
761 /* RDMA responder pagefault details */
765 * Received packet size, minimal size page fault
766 * resolution required for forward progress.
775 struct work_struct work
;
779 struct list_head tirs_list
;
783 struct mlx5e_resources
{
786 struct mlx5_core_mkey mkey
;
787 struct mlx5_sq_bfreg bfreg
;
790 #define MLX5_MAX_RESERVED_GIDS 8
792 struct mlx5_rsvd_gids
{
798 #define MAX_PIN_NUM 8
800 u8 pin_caps
[MAX_PIN_NUM
];
801 struct work_struct out_work
;
802 u64 start
[MAX_PIN_NUM
];
808 struct cyclecounter cycles
;
809 struct timecounter tc
;
810 struct hwtstamp_config hwtstamp_config
;
812 unsigned long overflow_period
;
813 struct delayed_work overflow_work
;
814 struct mlx5_core_dev
*mdev
;
815 struct ptp_clock
*ptp
;
816 struct ptp_clock_info ptp_info
;
817 struct mlx5_pps pps_info
;
820 struct mlx5_fw_tracer
;
823 struct mlx5_core_dev
{
824 struct pci_dev
*pdev
;
826 struct mutex pci_status_mutex
;
827 enum mlx5_pci_status pci_status
;
829 char board_id
[MLX5_BOARD_ID_LEN
];
831 struct mlx5_port_caps port_caps
[MLX5_MAX_PORTS
];
833 u32 hca_cur
[MLX5_CAP_NUM
][MLX5_UN_SZ_DW(hca_cap_union
)];
834 u32 hca_max
[MLX5_CAP_NUM
][MLX5_UN_SZ_DW(hca_cap_union
)];
835 u32 pcam
[MLX5_ST_SZ_DW(pcam_reg
)];
836 u32 mcam
[MLX5_ST_SZ_DW(mcam_reg
)];
837 u32 fpga
[MLX5_ST_SZ_DW(fpga_cap
)];
838 u32 qcam
[MLX5_ST_SZ_DW(qcam_reg
)];
840 phys_addr_t iseg_base
;
841 struct mlx5_init_seg __iomem
*iseg
;
842 enum mlx5_device_state state
;
843 /* sync interface state */
844 struct mutex intf_state_mutex
;
845 unsigned long intf_state
;
846 void (*event
) (struct mlx5_core_dev
*dev
,
847 enum mlx5_dev_event event
,
848 unsigned long param
);
849 struct mlx5_priv priv
;
850 struct mlx5_profile
*profile
;
853 struct mlx5e_resources mlx5e_res
;
854 struct mlx5_vxlan
*vxlan
;
856 struct mlx5_rsvd_gids reserved_gids
;
859 #ifdef CONFIG_MLX5_FPGA
860 struct mlx5_fpga_device
*fpga
;
862 #ifdef CONFIG_RFS_ACCEL
863 struct cpu_rmap
*rmap
;
865 struct mlx5_clock clock
;
866 struct mlx5_ib_clock_info
*clock_info
;
867 struct page
*clock_info_page
;
868 struct mlx5_fw_tracer
*tracer
;
874 struct mlx5_db_pgdir
*pgdir
;
875 struct mlx5_ib_user_db_page
*user_page
;
882 MLX5_COMP_EQ_SIZE
= 1024,
886 MLX5_PTYS_IB
= 1 << 0,
887 MLX5_PTYS_EN
= 1 << 2,
890 typedef void (*mlx5_cmd_cbk_t
)(int status
, void *context
);
893 MLX5_CMD_ENT_STATE_PENDING_COMP
,
896 struct mlx5_cmd_work_ent
{
898 struct mlx5_cmd_msg
*in
;
899 struct mlx5_cmd_msg
*out
;
902 mlx5_cmd_cbk_t callback
;
903 struct delayed_work cb_timeout_work
;
906 struct completion done
;
907 struct mlx5_cmd
*cmd
;
908 struct work_struct work
;
909 struct mlx5_cmd_layout
*lay
;
925 enum phy_port_state
{
929 struct mlx5_hca_vport_context
{
934 enum port_state_policy policy
;
935 enum phy_port_state phys_state
;
936 enum ib_port_state vport_state
;
937 u8 port_physical_state
;
946 u8 init_type_reply
; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
951 u16 qkey_violation_counter
;
952 u16 pkey_violation_counter
;
956 static inline void *mlx5_buf_offset(struct mlx5_frag_buf
*buf
, int offset
)
958 return buf
->frags
->buf
+ offset
;
961 #define STRUCT_FIELD(header, field) \
962 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
963 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
965 static inline struct mlx5_core_dev
*pci2mlx5_core_dev(struct pci_dev
*pdev
)
967 return pci_get_drvdata(pdev
);
970 extern struct dentry
*mlx5_debugfs_root
;
972 static inline u16
fw_rev_maj(struct mlx5_core_dev
*dev
)
974 return ioread32be(&dev
->iseg
->fw_rev
) & 0xffff;
977 static inline u16
fw_rev_min(struct mlx5_core_dev
*dev
)
979 return ioread32be(&dev
->iseg
->fw_rev
) >> 16;
982 static inline u16
fw_rev_sub(struct mlx5_core_dev
*dev
)
984 return ioread32be(&dev
->iseg
->cmdif_rev_fw_sub
) & 0xffff;
987 static inline u16
cmdif_rev(struct mlx5_core_dev
*dev
)
989 return ioread32be(&dev
->iseg
->cmdif_rev_fw_sub
) >> 16;
992 static inline u32
mlx5_base_mkey(const u32 key
)
994 return key
& 0xffffff00u
;
997 static inline void mlx5_fill_fbc_offset(u8 log_stride
, u8 log_sz
,
999 struct mlx5_frag_buf_ctrl
*fbc
)
1001 fbc
->log_stride
= log_stride
;
1002 fbc
->log_sz
= log_sz
;
1003 fbc
->sz_m1
= (1 << fbc
->log_sz
) - 1;
1004 fbc
->log_frag_strides
= PAGE_SHIFT
- fbc
->log_stride
;
1005 fbc
->frag_sz_m1
= (1 << fbc
->log_frag_strides
) - 1;
1006 fbc
->strides_offset
= strides_offset
;
1009 static inline void mlx5_fill_fbc(u8 log_stride
, u8 log_sz
,
1010 struct mlx5_frag_buf_ctrl
*fbc
)
1012 mlx5_fill_fbc_offset(log_stride
, log_sz
, 0, fbc
);
1015 static inline void mlx5_core_init_cq_frag_buf(struct mlx5_frag_buf_ctrl
*fbc
,
1018 mlx5_fill_fbc(6 + MLX5_GET(cqc
, cqc
, cqe_sz
),
1019 MLX5_GET(cqc
, cqc
, log_cq_size
),
1023 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl
*fbc
,
1028 ix
+= fbc
->strides_offset
;
1029 frag
= ix
>> fbc
->log_frag_strides
;
1031 return fbc
->frag_buf
.frags
[frag
].buf
+
1032 ((fbc
->frag_sz_m1
& ix
) << fbc
->log_stride
);
1035 int mlx5_cmd_init(struct mlx5_core_dev
*dev
);
1036 void mlx5_cmd_cleanup(struct mlx5_core_dev
*dev
);
1037 void mlx5_cmd_use_events(struct mlx5_core_dev
*dev
);
1038 void mlx5_cmd_use_polling(struct mlx5_core_dev
*dev
);
1040 int mlx5_cmd_exec(struct mlx5_core_dev
*dev
, void *in
, int in_size
, void *out
,
1042 int mlx5_cmd_exec_cb(struct mlx5_core_dev
*dev
, void *in
, int in_size
,
1043 void *out
, int out_size
, mlx5_cmd_cbk_t callback
,
1045 int mlx5_cmd_exec_polling(struct mlx5_core_dev
*dev
, void *in
, int in_size
,
1046 void *out
, int out_size
);
1047 void mlx5_cmd_mbox_status(void *out
, u8
*status
, u32
*syndrome
);
1049 int mlx5_core_get_caps(struct mlx5_core_dev
*dev
, enum mlx5_cap_type cap_type
);
1050 int mlx5_cmd_alloc_uar(struct mlx5_core_dev
*dev
, u32
*uarn
);
1051 int mlx5_cmd_free_uar(struct mlx5_core_dev
*dev
, u32 uarn
);
1052 void mlx5_health_cleanup(struct mlx5_core_dev
*dev
);
1053 int mlx5_health_init(struct mlx5_core_dev
*dev
);
1054 void mlx5_start_health_poll(struct mlx5_core_dev
*dev
);
1055 void mlx5_stop_health_poll(struct mlx5_core_dev
*dev
);
1056 void mlx5_drain_health_wq(struct mlx5_core_dev
*dev
);
1057 void mlx5_trigger_health_work(struct mlx5_core_dev
*dev
);
1058 void mlx5_drain_health_recovery(struct mlx5_core_dev
*dev
);
1059 int mlx5_buf_alloc_node(struct mlx5_core_dev
*dev
, int size
,
1060 struct mlx5_frag_buf
*buf
, int node
);
1061 int mlx5_buf_alloc(struct mlx5_core_dev
*dev
,
1062 int size
, struct mlx5_frag_buf
*buf
);
1063 void mlx5_buf_free(struct mlx5_core_dev
*dev
, struct mlx5_frag_buf
*buf
);
1064 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev
*dev
, int size
,
1065 struct mlx5_frag_buf
*buf
, int node
);
1066 void mlx5_frag_buf_free(struct mlx5_core_dev
*dev
, struct mlx5_frag_buf
*buf
);
1067 struct mlx5_cmd_mailbox
*mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev
*dev
,
1068 gfp_t flags
, int npages
);
1069 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev
*dev
,
1070 struct mlx5_cmd_mailbox
*head
);
1071 int mlx5_core_create_srq(struct mlx5_core_dev
*dev
, struct mlx5_core_srq
*srq
,
1072 struct mlx5_srq_attr
*in
);
1073 int mlx5_core_destroy_srq(struct mlx5_core_dev
*dev
, struct mlx5_core_srq
*srq
);
1074 int mlx5_core_query_srq(struct mlx5_core_dev
*dev
, struct mlx5_core_srq
*srq
,
1075 struct mlx5_srq_attr
*out
);
1076 int mlx5_core_arm_srq(struct mlx5_core_dev
*dev
, struct mlx5_core_srq
*srq
,
1077 u16 lwm
, int is_srq
);
1078 void mlx5_init_mkey_table(struct mlx5_core_dev
*dev
);
1079 void mlx5_cleanup_mkey_table(struct mlx5_core_dev
*dev
);
1080 int mlx5_core_create_mkey_cb(struct mlx5_core_dev
*dev
,
1081 struct mlx5_core_mkey
*mkey
,
1083 u32
*out
, int outlen
,
1084 mlx5_cmd_cbk_t callback
, void *context
);
1085 int mlx5_core_create_mkey(struct mlx5_core_dev
*dev
,
1086 struct mlx5_core_mkey
*mkey
,
1087 u32
*in
, int inlen
);
1088 int mlx5_core_destroy_mkey(struct mlx5_core_dev
*dev
,
1089 struct mlx5_core_mkey
*mkey
);
1090 int mlx5_core_query_mkey(struct mlx5_core_dev
*dev
, struct mlx5_core_mkey
*mkey
,
1091 u32
*out
, int outlen
);
1092 int mlx5_core_alloc_pd(struct mlx5_core_dev
*dev
, u32
*pdn
);
1093 int mlx5_core_dealloc_pd(struct mlx5_core_dev
*dev
, u32 pdn
);
1094 int mlx5_core_mad_ifc(struct mlx5_core_dev
*dev
, const void *inb
, void *outb
,
1095 u16 opmod
, u8 port
);
1096 void mlx5_pagealloc_init(struct mlx5_core_dev
*dev
);
1097 void mlx5_pagealloc_cleanup(struct mlx5_core_dev
*dev
);
1098 int mlx5_pagealloc_start(struct mlx5_core_dev
*dev
);
1099 void mlx5_pagealloc_stop(struct mlx5_core_dev
*dev
);
1100 void mlx5_core_req_pages_handler(struct mlx5_core_dev
*dev
, u16 func_id
,
1102 int mlx5_satisfy_startup_pages(struct mlx5_core_dev
*dev
, int boot
);
1103 int mlx5_reclaim_startup_pages(struct mlx5_core_dev
*dev
);
1104 void mlx5_register_debugfs(void);
1105 void mlx5_unregister_debugfs(void);
1107 void mlx5_fill_page_array(struct mlx5_frag_buf
*buf
, __be64
*pas
);
1108 void mlx5_fill_page_frag_array(struct mlx5_frag_buf
*frag_buf
, __be64
*pas
);
1109 void mlx5_rsc_event(struct mlx5_core_dev
*dev
, u32 rsn
, int event_type
);
1110 void mlx5_srq_event(struct mlx5_core_dev
*dev
, u32 srqn
, int event_type
);
1111 struct mlx5_core_srq
*mlx5_core_get_srq(struct mlx5_core_dev
*dev
, u32 srqn
);
1112 int mlx5_vector2eqn(struct mlx5_core_dev
*dev
, int vector
, int *eqn
,
1113 unsigned int *irqn
);
1114 int mlx5_core_attach_mcg(struct mlx5_core_dev
*dev
, union ib_gid
*mgid
, u32 qpn
);
1115 int mlx5_core_detach_mcg(struct mlx5_core_dev
*dev
, union ib_gid
*mgid
, u32 qpn
);
1117 int mlx5_qp_debugfs_init(struct mlx5_core_dev
*dev
);
1118 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev
*dev
);
1119 int mlx5_core_access_reg(struct mlx5_core_dev
*dev
, void *data_in
,
1120 int size_in
, void *data_out
, int size_out
,
1121 u16 reg_num
, int arg
, int write
);
1123 int mlx5_db_alloc(struct mlx5_core_dev
*dev
, struct mlx5_db
*db
);
1124 int mlx5_db_alloc_node(struct mlx5_core_dev
*dev
, struct mlx5_db
*db
,
1126 void mlx5_db_free(struct mlx5_core_dev
*dev
, struct mlx5_db
*db
);
1128 const char *mlx5_command_str(int command
);
1129 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev
*dev
);
1130 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev
*dev
);
1131 int mlx5_core_create_psv(struct mlx5_core_dev
*dev
, u32 pdn
,
1132 int npsvs
, u32
*sig_index
);
1133 int mlx5_core_destroy_psv(struct mlx5_core_dev
*dev
, int psv_num
);
1134 void mlx5_core_put_rsc(struct mlx5_core_rsc_common
*common
);
1135 int mlx5_query_odp_caps(struct mlx5_core_dev
*dev
,
1136 struct mlx5_odp_caps
*odp_caps
);
1137 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev
*dev
,
1138 u8 port_num
, void *out
, size_t sz
);
1139 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1140 int mlx5_core_page_fault_resume(struct mlx5_core_dev
*dev
, u32 token
,
1141 u32 wq_num
, u8 type
, int error
);
1144 int mlx5_init_rl_table(struct mlx5_core_dev
*dev
);
1145 void mlx5_cleanup_rl_table(struct mlx5_core_dev
*dev
);
1146 int mlx5_rl_add_rate(struct mlx5_core_dev
*dev
, u16
*index
,
1147 struct mlx5_rate_limit
*rl
);
1148 void mlx5_rl_remove_rate(struct mlx5_core_dev
*dev
, struct mlx5_rate_limit
*rl
);
1149 bool mlx5_rl_is_in_range(struct mlx5_core_dev
*dev
, u32 rate
);
1150 bool mlx5_rl_are_equal(struct mlx5_rate_limit
*rl_0
,
1151 struct mlx5_rate_limit
*rl_1
);
1152 int mlx5_alloc_bfreg(struct mlx5_core_dev
*mdev
, struct mlx5_sq_bfreg
*bfreg
,
1153 bool map_wc
, bool fast_path
);
1154 void mlx5_free_bfreg(struct mlx5_core_dev
*mdev
, struct mlx5_sq_bfreg
*bfreg
);
1156 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev
*dev
);
1157 int mlx5_core_roce_gid_set(struct mlx5_core_dev
*dev
, unsigned int index
,
1158 u8 roce_version
, u8 roce_l3_type
, const u8
*gid
,
1159 const u8
*mac
, bool vlan
, u16 vlan_id
, u8 port_num
);
1161 static inline int fw_initializing(struct mlx5_core_dev
*dev
)
1163 return ioread32be(&dev
->iseg
->initializing
) >> 31;
1166 static inline u32
mlx5_mkey_to_idx(u32 mkey
)
1171 static inline u32
mlx5_idx_to_mkey(u32 mkey_idx
)
1173 return mkey_idx
<< 8;
1176 static inline u8
mlx5_mkey_variant(u32 mkey
)
1182 MLX5_PROF_MASK_QP_SIZE
= (u64
)1 << 0,
1183 MLX5_PROF_MASK_MR_CACHE
= (u64
)1 << 1,
1187 MR_CACHE_LAST_STD_ENTRY
= 20,
1188 MLX5_IMR_MTT_CACHE_ENTRY
,
1189 MLX5_IMR_KSM_CACHE_ENTRY
,
1190 MAX_MR_CACHE_ENTRIES
1194 MLX5_INTERFACE_PROTOCOL_IB
= 0,
1195 MLX5_INTERFACE_PROTOCOL_ETH
= 1,
1198 struct mlx5_interface
{
1199 void * (*add
)(struct mlx5_core_dev
*dev
);
1200 void (*remove
)(struct mlx5_core_dev
*dev
, void *context
);
1201 int (*attach
)(struct mlx5_core_dev
*dev
, void *context
);
1202 void (*detach
)(struct mlx5_core_dev
*dev
, void *context
);
1203 void (*event
)(struct mlx5_core_dev
*dev
, void *context
,
1204 enum mlx5_dev_event event
, unsigned long param
);
1205 void (*pfault
)(struct mlx5_core_dev
*dev
,
1207 struct mlx5_pagefault
*pfault
);
1208 void * (*get_dev
)(void *context
);
1210 struct list_head list
;
1213 void *mlx5_get_protocol_dev(struct mlx5_core_dev
*mdev
, int protocol
);
1214 int mlx5_register_interface(struct mlx5_interface
*intf
);
1215 void mlx5_unregister_interface(struct mlx5_interface
*intf
);
1216 int mlx5_core_query_vendor_id(struct mlx5_core_dev
*mdev
, u32
*vendor_id
);
1218 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev
*dev
);
1219 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev
*dev
);
1220 bool mlx5_lag_is_active(struct mlx5_core_dev
*dev
);
1221 struct net_device
*mlx5_lag_get_roce_netdev(struct mlx5_core_dev
*dev
);
1222 int mlx5_lag_query_cong_counters(struct mlx5_core_dev
*dev
,
1226 struct mlx5_uars_page
*mlx5_get_uars_page(struct mlx5_core_dev
*mdev
);
1227 void mlx5_put_uars_page(struct mlx5_core_dev
*mdev
, struct mlx5_uars_page
*up
);
1229 #ifndef CONFIG_MLX5_CORE_IPOIB
1231 struct net_device
*mlx5_rdma_netdev_alloc(struct mlx5_core_dev
*mdev
,
1232 struct ib_device
*ibdev
,
1234 void (*setup
)(struct net_device
*))
1236 return ERR_PTR(-EOPNOTSUPP
);
1239 struct net_device
*mlx5_rdma_netdev_alloc(struct mlx5_core_dev
*mdev
,
1240 struct ib_device
*ibdev
,
1242 void (*setup
)(struct net_device
*));
1243 #endif /* CONFIG_MLX5_CORE_IPOIB */
1245 struct mlx5_profile
{
1251 } mr_cache
[MAX_MR_CACHE_ENTRIES
];
1255 MLX5_PCI_DEV_IS_VF
= 1 << 0,
1258 static inline int mlx5_core_is_pf(struct mlx5_core_dev
*dev
)
1260 return !(dev
->priv
.pci_dev_data
& MLX5_PCI_DEV_IS_VF
);
1263 #define MLX5_TOTAL_VPORTS(mdev) (1 + pci_sriov_get_totalvfs((mdev)->pdev))
1264 #define MLX5_VPORT_MANAGER(mdev) \
1265 (MLX5_CAP_GEN(mdev, vport_group_manager) && \
1266 (MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && \
1267 mlx5_core_is_pf(mdev))
1269 static inline int mlx5_get_gid_table_len(u16 param
)
1272 pr_warn("gid table length is zero\n");
1276 return 8 * (1 << param
);
1279 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev
*dev
)
1281 return !!(dev
->priv
.rl_table
.max_size
);
1284 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev
*dev
)
1286 return MLX5_CAP_GEN(dev
, affiliate_nic_vport_criteria
) &&
1287 MLX5_CAP_GEN(dev
, num_vhca_ports
) <= 1;
1290 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev
*dev
)
1292 return MLX5_CAP_GEN(dev
, num_vhca_ports
) > 1;
1295 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev
*dev
)
1297 return mlx5_core_is_mp_slave(dev
) ||
1298 mlx5_core_is_mp_master(dev
);
1301 static inline int mlx5_core_native_port_num(struct mlx5_core_dev
*dev
)
1303 if (!mlx5_core_mp_enabled(dev
))
1306 return MLX5_CAP_GEN(dev
, native_port_num
);
1310 MLX5_TRIGGERED_CMD_COMP
= (u64
)1 << 32,
1313 static inline const struct cpumask
*
1314 mlx5_get_vector_affinity_hint(struct mlx5_core_dev
*dev
, int vector
)
1316 return dev
->priv
.irq_info
[vector
].mask
;
1319 #endif /* MLX5_DRIVER_H */