include/linux/mtd/fsmc_nand.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2010
   4  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
   5  */
   6
   7 #ifndef __FSMC_NAND_H__
   8 #define __FSMC_NAND_H__
   9
  10 #include <linux/mtd/rawnand.h>
  11
  12 struct fsmc_regs {
  13         u32 ctrl;                       /* 0x00 */
  14         u8 reserved_1[0x40 - 0x04];
  15         u32 pc;                         /* 0x40 */
  16         u32 sts;                        /* 0x44 */
  17         u32 comm;                       /* 0x48 */
  18         u32 attrib;                     /* 0x4c */
  19         u32 ioata;                      /* 0x50 */
  20         u32 ecc1;                       /* 0x54 */
  21         u32 ecc2;                       /* 0x58 */
  22         u32 ecc3;                       /* 0x5c */
  23         u8 reserved_2[0xfe0 - 0x60];
  24         u32 peripid0;                   /* 0xfe0 */
  25         u32 peripid1;                   /* 0xfe4 */
  26         u32 peripid2;                   /* 0xfe8 */
  27         u32 peripid3;                   /* 0xfec */
  28         u32 pcellid0;                   /* 0xff0 */
  29         u32 pcellid1;                   /* 0xff4 */
  30         u32 pcellid2;                   /* 0xff8 */
  31         u32 pcellid3;                   /* 0xffc */
  32 };
  33
  34 /* ctrl register definitions */
  35 #define FSMC_WP                 (1 << 7)
  36
  37 /* pc register definitions */
  38 #define FSMC_RESET              (1 << 0)
  39 #define FSMC_WAITON             (1 << 1)
  40 #define FSMC_ENABLE             (1 << 2)
  41 #define FSMC_DEVTYPE_NAND       (1 << 3)
  42 #define FSMC_DEVWID_8           (0 << 4)
  43 #define FSMC_DEVWID_16          (1 << 4)
  44 #define FSMC_ECCEN              (1 << 6)
  45 #define FSMC_ECCPLEN_512        (0 << 7)
  46 #define FSMC_ECCPLEN_256        (1 << 7)
  47 #define FSMC_TCLR_1             (1 << 9)
  48 #define FSMC_TAR_1              (1 << 13)
  49
  50 /* sts register definitions */
  51 #define FSMC_CODE_RDY           (1 << 15)
  52
  53 /* comm register definitions */
  54 #define FSMC_TSET_0             (0 << 0)
  55 #define FSMC_TWAIT_6            (6 << 8)
  56 #define FSMC_THOLD_4            (4 << 16)
  57 #define FSMC_THIZ_1             (1 << 24)
  58
  59 /* peripid2 register definitions */
  60 #define FSMC_REVISION_MSK       (0xf)
  61 #define FSMC_REVISION_SHFT      (0x4)
  62
  63 #define FSMC_VER8               0x8
  64
  65 /*
  66  * There are 13 bytes of ecc for every 512 byte block and it has to be read
  67  * consecutively and immediately after the 512 byte data block for hardware to
  68  * generate the error bit offsets
  69  * Managing the ecc bytes in the following way is easier. This way is similar to
  70  * oobfree structure maintained already in u-boot nand driver
  71  */
  72 #define FSMC_MAX_ECCPLACE_ENTRIES       32
  73
  74 struct fsmc_nand_eccplace {
  75         u32 offset;
  76         u32 length;
  77 };
  78
  79 struct fsmc_eccplace {
  80         struct fsmc_nand_eccplace eccplace[FSMC_MAX_ECCPLACE_ENTRIES];
  81 };
  82
  83 extern int fsmc_nand_init(struct nand_chip *nand);
  84 #endif