include/linux/stmmac.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*******************************************************************************
   3
   4   Header file for stmmac platform data
   5
   6   Copyright (C) 2009  STMicroelectronics Ltd
   7
   8
   9   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  10 *******************************************************************************/
  11
  12 #ifndef __STMMAC_PLATFORM_DATA
  13 #define __STMMAC_PLATFORM_DATA
  14
  15 #include <linux/platform_device.h>
  16 #include <linux/phylink.h>
  17
  18 #define MTL_MAX_RX_QUEUES       8
  19 #define MTL_MAX_TX_QUEUES       8
  20 #define STMMAC_CH_MAX           8
  21
  22 #define STMMAC_RX_COE_NONE      0
  23 #define STMMAC_RX_COE_TYPE1     1
  24 #define STMMAC_RX_COE_TYPE2     2
  25
  26 /* Define the macros for CSR clock range parameters to be passed by
  27  * platform code.
  28  * This could also be configured at run time using CPU freq framework. */
  29
  30 /* MDC Clock Selection define*/
  31 #define STMMAC_CSR_60_100M      0x0     /* MDC = clk_scr_i/42 */
  32 #define STMMAC_CSR_100_150M     0x1     /* MDC = clk_scr_i/62 */
  33 #define STMMAC_CSR_20_35M       0x2     /* MDC = clk_scr_i/16 */
  34 #define STMMAC_CSR_35_60M       0x3     /* MDC = clk_scr_i/26 */
  35 #define STMMAC_CSR_150_250M     0x4     /* MDC = clk_scr_i/102 */
  36 #define STMMAC_CSR_250_300M     0x5     /* MDC = clk_scr_i/124 */
  37 #define STMMAC_CSR_300_500M     0x6     /* MDC = clk_scr_i/204 */
  38 #define STMMAC_CSR_500_800M     0x7     /* MDC = clk_scr_i/324 */
  39
  40 /* MTL algorithms identifiers */
  41 #define MTL_TX_ALGORITHM_WRR    0x0
  42 #define MTL_TX_ALGORITHM_WFQ    0x1
  43 #define MTL_TX_ALGORITHM_DWRR   0x2
  44 #define MTL_TX_ALGORITHM_SP     0x3
  45 #define MTL_RX_ALGORITHM_SP     0x4
  46 #define MTL_RX_ALGORITHM_WSP    0x5
  47
  48 /* RX/TX Queue Mode */
  49 #define MTL_QUEUE_AVB           0x0
  50 #define MTL_QUEUE_DCB           0x1
  51
  52 /* The MDC clock could be set higher than the IEEE 802.3
  53  * specified frequency limit 0f 2.5 MHz, by programming a clock divider
  54  * of value different than the above defined values. The resultant MDIO
  55  * clock frequency of 12.5 MHz is applicable for the interfacing chips
  56  * supporting higher MDC clocks.
  57  * The MDC clock selection macros need to be defined for MDC clock rate
  58  * of 12.5 MHz, corresponding to the following selection.
  59  */
  60 #define STMMAC_CSR_I_4          0x8     /* clk_csr_i/4 */
  61 #define STMMAC_CSR_I_6          0x9     /* clk_csr_i/6 */
  62 #define STMMAC_CSR_I_8          0xA     /* clk_csr_i/8 */
  63 #define STMMAC_CSR_I_10         0xB     /* clk_csr_i/10 */
  64 #define STMMAC_CSR_I_12         0xC     /* clk_csr_i/12 */
  65 #define STMMAC_CSR_I_14         0xD     /* clk_csr_i/14 */
  66 #define STMMAC_CSR_I_16         0xE     /* clk_csr_i/16 */
  67 #define STMMAC_CSR_I_18         0xF     /* clk_csr_i/18 */
  68
  69 /* AXI DMA Burst length supported */
  70 #define DMA_AXI_BLEN_4          (1 << 1)
  71 #define DMA_AXI_BLEN_8          (1 << 2)
  72 #define DMA_AXI_BLEN_16         (1 << 3)
  73 #define DMA_AXI_BLEN_32         (1 << 4)
  74 #define DMA_AXI_BLEN_64         (1 << 5)
  75 #define DMA_AXI_BLEN_128        (1 << 6)
  76 #define DMA_AXI_BLEN_256        (1 << 7)
  77 #define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \
  78                         | DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \
  79                         | DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256)
  80
  81 struct clk;
  82 struct stmmac_priv;
  83
  84 /* Platfrom data for platform device structure's platform_data field */
  85
  86 struct stmmac_mdio_bus_data {
  87         unsigned int phy_mask;
  88         unsigned int pcs_mask;
  89         unsigned int default_an_inband;
  90         int *irqs;
  91         int probed_phy_irq;
  92         bool needs_reset;
  93 };
  94
  95 struct stmmac_dma_cfg {
  96         int pbl;
  97         int txpbl;
  98         int rxpbl;
  99         bool pblx8;
 100         int fixed_burst;
 101         int mixed_burst;
 102         bool aal;
 103         bool eame;
 104         bool multi_msi_en;
 105         bool dche;
 106         bool atds;
 107 };
 108
 109 #define AXI_BLEN        7
 110 struct stmmac_axi {
 111         bool axi_lpi_en;
 112         bool axi_xit_frm;
 113         u32 axi_wr_osr_lmt;
 114         u32 axi_rd_osr_lmt;
 115         bool axi_kbbe;
 116         u32 axi_blen[AXI_BLEN];
 117         bool axi_fb;
 118         bool axi_mb;
 119         bool axi_rb;
 120 };
 121
 122 struct stmmac_rxq_cfg {
 123         u8 mode_to_use;
 124         u32 chan;
 125         u8 pkt_route;
 126         bool use_prio;
 127         u32 prio;
 128 };
 129
 130 struct stmmac_txq_cfg {
 131         u32 weight;
 132         bool coe_unsupported;
 133         u8 mode_to_use;
 134         /* Credit Base Shaper parameters */
 135         u32 send_slope;
 136         u32 idle_slope;
 137         u32 high_credit;
 138         u32 low_credit;
 139         bool use_prio;
 140         u32 prio;
 141         int tbs_en;
 142 };
 143
 144 struct stmmac_safety_feature_cfg {
 145         u32 tsoee;
 146         u32 mrxpee;
 147         u32 mestee;
 148         u32 mrxee;
 149         u32 mtxee;
 150         u32 epsi;
 151         u32 edpp;
 152         u32 prtyen;
 153         u32 tmouten;
 154 };
 155
 156 /* Addresses that may be customized by a platform */
 157 struct dwmac4_addrs {
 158         u32 dma_chan;
 159         u32 dma_chan_offset;
 160         u32 mtl_chan;
 161         u32 mtl_chan_offset;
 162         u32 mtl_ets_ctrl;
 163         u32 mtl_ets_ctrl_offset;
 164         u32 mtl_txq_weight;
 165         u32 mtl_txq_weight_offset;
 166         u32 mtl_send_slp_cred;
 167         u32 mtl_send_slp_cred_offset;
 168         u32 mtl_high_cred;
 169         u32 mtl_high_cred_offset;
 170         u32 mtl_low_cred;
 171         u32 mtl_low_cred_offset;
 172 };
 173
 174 #define STMMAC_FLAG_HAS_INTEGRATED_PCS          BIT(0)
 175 #define STMMAC_FLAG_SPH_DISABLE                 BIT(1)
 176 #define STMMAC_FLAG_USE_PHY_WOL                 BIT(2)
 177 #define STMMAC_FLAG_HAS_SUN8I                   BIT(3)
 178 #define STMMAC_FLAG_TSO_EN                      BIT(4)
 179 #define STMMAC_FLAG_SERDES_UP_AFTER_PHY_LINKUP  BIT(5)
 180 #define STMMAC_FLAG_VLAN_FAIL_Q_EN              BIT(6)
 181 #define STMMAC_FLAG_MULTI_MSI_EN                BIT(7)
 182 #define STMMAC_FLAG_EXT_SNAPSHOT_EN             BIT(8)
 183 #define STMMAC_FLAG_INT_SNAPSHOT_EN             BIT(9)
 184 #define STMMAC_FLAG_RX_CLK_RUNS_IN_LPI          BIT(10)
 185 #define STMMAC_FLAG_EN_TX_LPI_CLOCKGATING       BIT(11)
 186 #define STMMAC_FLAG_EN_TX_LPI_CLK_PHY_CAP       BIT(12)
 187 #define STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY    BIT(13)
 188
 189 struct plat_stmmacenet_data {
 190         int bus_id;
 191         int phy_addr;
 192         /* MAC ----- optional PCS ----- SerDes ----- optional PHY ----- Media
 193          *       ^                               ^
 194          * mac_interface                   phy_interface
 195          *
 196          * mac_interface is the MAC-side interface, which may be the same
 197          * as phy_interface if there is no intervening PCS. If there is a
 198          * PCS, then mac_interface describes the interface mode between the
 199          * MAC and PCS, and phy_interface describes the interface mode
 200          * between the PCS and PHY.
 201          */
 202         phy_interface_t mac_interface;
 203         /* phy_interface is the PHY-side interface - the interface used by
 204          * an attached PHY.
 205          */
 206         phy_interface_t phy_interface;
 207         struct stmmac_mdio_bus_data *mdio_bus_data;
 208         struct device_node *phy_node;
 209         struct fwnode_handle *port_node;
 210         struct device_node *mdio_node;
 211         struct stmmac_dma_cfg *dma_cfg;
 212         struct stmmac_safety_feature_cfg *safety_feat_cfg;
 213         int clk_csr;
 214         int has_gmac;
 215         int enh_desc;
 216         int tx_coe;
 217         int rx_coe;
 218         int bugged_jumbo;
 219         int pmt;
 220         int force_sf_dma_mode;
 221         int force_thresh_dma_mode;
 222         int riwt_off;
 223         int max_speed;
 224         int maxmtu;
 225         int multicast_filter_bins;
 226         int unicast_filter_entries;
 227         int tx_fifo_size;
 228         int rx_fifo_size;
 229         u32 host_dma_width;
 230         u32 rx_queues_to_use;
 231         u32 tx_queues_to_use;
 232         u8 rx_sched_algorithm;
 233         u8 tx_sched_algorithm;
 234         struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];
 235         struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES];
 236         void (*get_interfaces)(struct stmmac_priv *priv, void *bsp_priv,
 237                                unsigned long *interfaces);
 238         int (*set_clk_tx_rate)(void *priv, struct clk *clk_tx_i,
 239                                phy_interface_t interface, int speed);
 240         void (*fix_mac_speed)(void *priv, int speed, unsigned int mode);
 241         int (*fix_soc_reset)(void *priv, void __iomem *ioaddr);
 242         int (*serdes_powerup)(struct net_device *ndev, void *priv);
 243         void (*serdes_powerdown)(struct net_device *ndev, void *priv);
 244         int (*mac_finish)(struct net_device *ndev,
 245                           void *priv,
 246                           unsigned int mode,
 247                           phy_interface_t interface);
 248         void (*ptp_clk_freq_config)(struct stmmac_priv *priv);
 249         int (*init)(struct platform_device *pdev, void *priv);
 250         void (*exit)(struct platform_device *pdev, void *priv);
 251         struct mac_device_info *(*setup)(void *priv);
 252         int (*clks_config)(void *priv, bool enabled);
 253         int (*crosststamp)(ktime_t *device, struct system_counterval_t *system,
 254                            void *ctx);
 255         void (*dump_debug_regs)(void *priv);
 256         int (*pcs_init)(struct stmmac_priv *priv);
 257         void (*pcs_exit)(struct stmmac_priv *priv);
 258         struct phylink_pcs *(*select_pcs)(struct stmmac_priv *priv,
 259                                           phy_interface_t interface);
 260         void *bsp_priv;
 261         struct clk *stmmac_clk;
 262         struct clk *pclk;
 263         struct clk *clk_ptp_ref;
 264         struct clk *clk_tx_i;           /* clk_tx_i to MAC core */
 265         unsigned long clk_ptp_rate;
 266         unsigned long clk_ref_rate;
 267         struct clk_bulk_data *clks;
 268         int num_clks;
 269         unsigned int mult_fact_100ns;
 270         s32 ptp_max_adj;
 271         u32 cdc_error_adj;
 272         struct reset_control *stmmac_rst;
 273         struct reset_control *stmmac_ahb_rst;
 274         struct stmmac_axi *axi;
 275         int has_gmac4;
 276         int rss_en;
 277         int mac_port_sel_speed;
 278         int has_xgmac;
 279         u8 vlan_fail_q;
 280         struct pci_dev *pdev;
 281         int int_snapshot_num;
 282         int msi_mac_vec;
 283         int msi_wol_vec;
 284         int msi_lpi_vec;
 285         int msi_sfty_ce_vec;
 286         int msi_sfty_ue_vec;
 287         int msi_rx_base_vec;
 288         int msi_tx_base_vec;
 289         const struct dwmac4_addrs *dwmac4_addrs;
 290         unsigned int flags;
 291 };
 292 #endif