include/lpd7a400_cpld.h

   1 /*
   2  * See file CREDITS for list of people who contributed to this
   3  * project.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20
  21 /*
  22  * Logic lh7a400-10 Card Engine CPLD interface
  23  */
  24
  25 #ifndef __LPD7A400_CPLD_H_
  26 #define __LPD7A400_CPLD_H_
  27
  28
  29 /*
  30  * IO Controller Address and Register Definitions
  31  *   - using LH7A400-10 Card Engine IO Controller Specification
  32  *     (logic PN: 70000079)
  33  */
  34
  35 /*------------------------------------------------------------------
  36  * Slow Peripherals (nCS6)
  37  */
  38 #define LPD7A400_CPLD_CF                (0x60200000)
  39 #define LPD7A400_CPLD_ISA               (0x60400000)
  40
  41 /*------------------------------------------------------------------
  42  * Fast Peripherals (nCS7)
  43  *
  44  * The CPLD directs access to 0x70000000-0x701fffff to the onboard
  45  * ethernet controller
  46  */
  47 #define LPD7A400_CPLD_WLAN_BASE         (0x70000000)
  48
  49 /* All registers are 8 bit */
  50 #define LPD7A400_CPLD_CECTL_REG         (0x70200000)
  51 #define LPD7A400_CPLD_SPIDATA_REG       (0x70600000)
  52 #define LPD7A400_CPLD_SPICTL_REG        (0x70800000)
  53 #define LPD7A400_CPLD_EEPSPI_REG        (0x70a00000)
  54 #define LPD7A400_CPLD_INTMASK_REG       (0x70c00000)
  55 #define LPD7A400_CPLD_MODE_REG          (0x70e00000)
  56 #define LPD7A400_CPLD_FLASH_REG         (0x71000000)
  57 #define LPD7A400_CPLD_PWRMG_REG         (0x71200000)
  58 #define LPD7A400_CPLD_REV_REG           (0x71400000)
  59 #define LPD7A400_CPLD_EXTGPIO_REG       (0x71600000)
  60 #define LPD7A400_CPLD_GPIODATA_REG      (0x71800000)
  61 #define LPD7A400_CPLD_GPIODIR_REG       (0x71a00000)
  62
  63 #define LPD7A400_CPLD_REGPTR            (volatile u8*)
  64
  65 /* Card Engine Control Register (section 3.1.2) */
  66 #define CECTL_SWINT     (0x80)  /* Software settable interrupt source
  67                                    (routed to uP PF3)
  68                                    0 = generate interrupt, 1 = do not */
  69 #define CECTL_OCMSK     (0x40)  /* USB1 connection interrupt mask
  70                                    0 = not masked, 1 = masked */
  71 #define CECTL_PDRV      (0x20)  /* PCC_nDRV output
  72                                    0 = active, 1 = inactive */
  73 #define CECTL_USB1C     (0x10)  /* USB1 connection interrupt
  74                                    0 = active, 1 = inactive */
  75 #define CECTL_USB1P     (0x08)  /* USB1 Power enable
  76                                    0 = enabled, 1 = disabled */
  77 #define CECTL_AWKP      (0x04)  /* Auto-Wakeup enable
  78                                    0 = enabled, 1 = disabled */
  79 #define CECTL_LCDV      (0x02)  /* LCD VEE enable
  80                                    0 = disabled, 1 = enabled */
  81 #define CECTL_WLPE      (0x01)  /* Wired LAN power enable
  82                                    0 = enabled, 1 = disabled */
  83
  84 /* SPI Control Register (section 3.1.5) */
  85 #define SPICTL_SPLD     (0x20)  /* SPI load (R)
  86                                    0 = data reg. has not been loaded, shift
  87                                        count has not been reset
  88                                    1 = data reg. loaded, shift count reset */
  89 #define SPICTL_SPST     (0x10)  /* SPI start (RW)
  90                                    0 = don't load data reg. and reset shift count
  91                                    1 = ready to load data reg and reset shift count */
  92 #define SPICTL_SPDN     (0x08)  /* SPI done (R)
  93                                    0 = not done
  94                                    1 = access done */
  95 #define SPICTL_SPRW     (0x04)  /* SPI read/write (RW)
  96                                    0 = SPI write access
  97                                    1 = SPI read access */
  98 #define SPICTL_STCS     (0x02)  /* SPI touch chip select (RW)
  99                                    0 = not selected
 100                                    1 = selected */
 101 #define SPICTL_SCCS     (0x01)  /* SPI CODEC chip select (RW) {not used}
 102                                    0 = not selected
 103                                    1 = selected */
 104
 105 /* EEPROM SPI Interface Register (section 3.1.6) */
 106 #define EEPSPI_EECS     (0x08)  /* EEPROM chip select (RW)
 107                                    0 = not selected
 108                                    1 = selected */
 109 #define EEPSPI_EECK     (0x04)  /* EEPROM SPI clock (RW) */
 110 #define EEPSPI_EETX     (0x02)  /* EEPROM SPI tx data (RW) */
 111 #define EEPSPI_EERX     (0x01)  /* EEPROM SPI rx data (R) */
 112
 113 /* Interrupt/Mask Register (section 3.1.7) */
 114 #define INTMASK_CMSK    (0x80)  /* CPLD_nIRQD interrupt mask (RW)
 115                                    0 = not masked
 116                                    1 = masked */
 117 #define INTMASK_CIRQ    (0x40)  /* interrupt signal to CPLD (R)
 118                                    0 = interrupt active
 119                                    1 = no interrupt */
 120 #define INTMASK_PIRQ    (0x10)  /* legacy, no effect */
 121 #define INTMASK_TMSK    (0x08)  /* Touch chip interrupt mask (RW)
 122                                    0 = not masked
 123                                    1 = masked */
 124 #define INTMASK_WMSK    (0x04)  /* Wired LAN interrupt mask (RW)
 125                                    0 = not masked
 126                                    1 = masked */
 127 #define INTMASK_TIRQ    (0x02)  /* Touch chip interrupt request (R)
 128                                    0 = interrupt active
 129                                    1 = no interrupt */
 130 #define INTMASK_WIRQ    (0x01)  /* Wired LAN interrupt request (R)
 131                                    0 = interrupt active
 132                                    1 = no interrupt */
 133
 134 /* Mode Register (section 3.1.8) */
 135 #define MODE_VS1        (0x80)  /* PCMCIA Voltage Sense 1 input (PCC_VS1) (R)
 136                                    0 = active slot VS1 pin is low
 137                                    1 = active slot VS1 pin is high */
 138 #define MODE_CD2        (0x40)  /* PCMCIA Card Detect 2 input (PCC_nCD2) (R)
 139                                    0 = active slot CD2 is low
 140                                    1 = active slot CD2 is high */
 141 #define MODE_IOIS16     (0x20)  /* PCMCIA IOIS16 input (PCC_nIOIS16) (R)
 142                                    0 = 16 bit access area
 143                                    1 = 8 bit access area */
 144 #define MODE_CD1        (0x10)  /* PCMCIA Card Detect 1 input (PCC_nCD1) (R)
 145                                    0 = active slot CD1 is low
 146                                    1 = active slot CD1 is high */
 147 #define MODE_upMODE3    (0x08)  /* Mode Pin 3 (R)
 148                                    0 = off-board boot device
 149                                    1 = on-board boot device (flash) */
 150 #define MODE_upMODE2    (0x04)  /* Mode Pin 2 (R) (LH7A400 Little Endian only)
 151                                    0 = big endian
 152                                    1 = little endian */
 153 #define MODE_upMODE1    (0x02)  /* Mode Pin 1 and Mode Pin 2 (R) */
 154 #define MODE_upMODE0    (0x01)  /*   - bus width at boot */
 155
 156
 157 /* Flash Register (section 3.1.9) */
 158 #define FLASH_FPOP      (0x08)  /* Flash populated (RW)
 159                                    0 = populated, 1 = not */
 160 #define FLASH_FST2      (0x04)  /* Flash status (R) (RY/BY# pin for upper 16 bit chip
 161                                    0 = busy, 1 = ready */
 162 #define FLASH_FST1      (0x02)  /* Flash status (R) (RY/BY# pin for lower 16 bit chip
 163                                    0 = busy, 1 = ready */
 164 #define FLASH_FPEN      (0x01)  /* Flash program enable (RW)
 165                                    0 = flash write protected
 166                                    1 = programming enabled */
 167
 168 /* Power Management Register (section 3.1.10)
 169  *    - when either of these is low an unmaskable interrupt to cpu
 170  *      is generated
 171  */
 172 #define PWRMG_STBY      (0x10)  /* state of nSTANDBY signal to CPLD (R)
 173                                    0 = low, 1 = high */
 174 #define PWRMG_SPND      (0x04)  /* state of nSUSPEND signal to CPLD (R)
 175                                    0 = low, 1 = high */
 176
 177
 178 /* Extended GPIO Register (section 3.1.12) */
 179 #define EXTGPIO_STATUS1 (0x04)  /* Status 1 output (RW) (uP_STATUS_1)
 180                                    0 = set pin low, 1 = set pin high */
 181 #define EXTGPIO_STATUS2 (0x02)  /* Status 2 output (RW) (uP_STATUS_2)
 182                                    0 = set pin low, 1 = set pin high */
 183 #define EXTGPIO_GPIO1   (0x01)  /* General purpose output (RW) (CPLD_GPIO_1)
 184                                    0 = set pin low, 1 = set pin high */
 185
 186 /* GPIO Data Register (section 3.1.13) */
 187 #define GPIODATA_GPIO2  (0x01)  /* General purpose input/output (RW) (CPLD_GPIO_2)
 188                                    0 = set low (output) / read low (input)
 189                                    1 = set high (output) / read high (input) */
 190
 191 /* GPIO Direction Register (section 3.1.14) */
 192 #define GPIODIR_GPDR0   (0x01)  /* GPIO2 direction (RW)
 193                                    0 = output, 1 = input */
 194
 195 #endif  /* __LH7A400_H__ */