include/mmc.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2008,2010 Freescale Semiconductor, Inc
   4  * Andy Fleming
   5  *
   6  * Based (loosely) on the Linux code
   7  */
   8
   9 #ifndef _MMC_H_
  10 #define _MMC_H_
  11
  12 #include <linux/list.h>
  13 #include <linux/sizes.h>
  14 #include <linux/compiler.h>
  15 #include <part.h>
  16
  17 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
  18 #define MMC_SUPPORTS_TUNING
  19 #endif
  20 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  21 #define MMC_SUPPORTS_TUNING
  22 #endif
  23
  24 /* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */
  25 #define SD_VERSION_SD   (1U << 31)
  26 #define MMC_VERSION_MMC (1U << 30)
  27
  28 #define MAKE_SDMMC_VERSION(a, b, c)     \
  29         ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c))
  30 #define MAKE_SD_VERSION(a, b, c)        \
  31         (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c))
  32 #define MAKE_MMC_VERSION(a, b, c)       \
  33         (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c))
  34
  35 #define EXTRACT_SDMMC_MAJOR_VERSION(x)  \
  36         (((u32)(x) >> 16) & 0xff)
  37 #define EXTRACT_SDMMC_MINOR_VERSION(x)  \
  38         (((u32)(x) >> 8) & 0xff)
  39 #define EXTRACT_SDMMC_CHANGE_VERSION(x) \
  40         ((u32)(x) & 0xff)
  41
  42 #define SD_VERSION_3            MAKE_SD_VERSION(3, 0, 0)
  43 #define SD_VERSION_2            MAKE_SD_VERSION(2, 0, 0)
  44 #define SD_VERSION_1_0          MAKE_SD_VERSION(1, 0, 0)
  45 #define SD_VERSION_1_10         MAKE_SD_VERSION(1, 10, 0)
  46
  47 #define MMC_VERSION_UNKNOWN     MAKE_MMC_VERSION(0, 0, 0)
  48 #define MMC_VERSION_1_2         MAKE_MMC_VERSION(1, 2, 0)
  49 #define MMC_VERSION_1_4         MAKE_MMC_VERSION(1, 4, 0)
  50 #define MMC_VERSION_2_2         MAKE_MMC_VERSION(2, 2, 0)
  51 #define MMC_VERSION_3           MAKE_MMC_VERSION(3, 0, 0)
  52 #define MMC_VERSION_4           MAKE_MMC_VERSION(4, 0, 0)
  53 #define MMC_VERSION_4_1         MAKE_MMC_VERSION(4, 1, 0)
  54 #define MMC_VERSION_4_2         MAKE_MMC_VERSION(4, 2, 0)
  55 #define MMC_VERSION_4_3         MAKE_MMC_VERSION(4, 3, 0)
  56 #define MMC_VERSION_4_4         MAKE_MMC_VERSION(4, 4, 0)
  57 #define MMC_VERSION_4_41        MAKE_MMC_VERSION(4, 4, 1)
  58 #define MMC_VERSION_4_5         MAKE_MMC_VERSION(4, 5, 0)
  59 #define MMC_VERSION_5_0         MAKE_MMC_VERSION(5, 0, 0)
  60 #define MMC_VERSION_5_1         MAKE_MMC_VERSION(5, 1, 0)
  61
  62 #define MMC_CAP(mode)           (1 << mode)
  63 #define MMC_MODE_HS             (MMC_CAP(MMC_HS) | MMC_CAP(SD_HS))
  64 #define MMC_MODE_HS_52MHz       MMC_CAP(MMC_HS_52)
  65 #define MMC_MODE_DDR_52MHz      MMC_CAP(MMC_DDR_52)
  66 #define MMC_MODE_HS200          MMC_CAP(MMC_HS_200)
  67 #define MMC_MODE_HS400          MMC_CAP(MMC_HS_400)
  68
  69 #define MMC_MODE_8BIT           BIT(30)
  70 #define MMC_MODE_4BIT           BIT(29)
  71 #define MMC_MODE_1BIT           BIT(28)
  72 #define MMC_MODE_SPI            BIT(27)
  73
  74
  75 #define SD_DATA_4BIT    0x00040000
  76
  77 #define IS_SD(x)        ((x)->version & SD_VERSION_SD)
  78 #define IS_MMC(x)       ((x)->version & MMC_VERSION_MMC)
  79
  80 #define MMC_DATA_READ           1
  81 #define MMC_DATA_WRITE          2
  82
  83 #define MMC_CMD_GO_IDLE_STATE           0
  84 #define MMC_CMD_SEND_OP_COND            1
  85 #define MMC_CMD_ALL_SEND_CID            2
  86 #define MMC_CMD_SET_RELATIVE_ADDR       3
  87 #define MMC_CMD_SET_DSR                 4
  88 #define MMC_CMD_SWITCH                  6
  89 #define MMC_CMD_SELECT_CARD             7
  90 #define MMC_CMD_SEND_EXT_CSD            8
  91 #define MMC_CMD_SEND_CSD                9
  92 #define MMC_CMD_SEND_CID                10
  93 #define MMC_CMD_STOP_TRANSMISSION       12
  94 #define MMC_CMD_SEND_STATUS             13
  95 #define MMC_CMD_SET_BLOCKLEN            16
  96 #define MMC_CMD_READ_SINGLE_BLOCK       17
  97 #define MMC_CMD_READ_MULTIPLE_BLOCK     18
  98 #define MMC_CMD_SEND_TUNING_BLOCK               19
  99 #define MMC_CMD_SEND_TUNING_BLOCK_HS200 21
 100 #define MMC_CMD_SET_BLOCK_COUNT         23
 101 #define MMC_CMD_WRITE_SINGLE_BLOCK      24
 102 #define MMC_CMD_WRITE_MULTIPLE_BLOCK    25
 103 #define MMC_CMD_ERASE_GROUP_START       35
 104 #define MMC_CMD_ERASE_GROUP_END         36
 105 #define MMC_CMD_ERASE                   38
 106 #define MMC_CMD_APP_CMD                 55
 107 #define MMC_CMD_SPI_READ_OCR            58
 108 #define MMC_CMD_SPI_CRC_ON_OFF          59
 109 #define MMC_CMD_RES_MAN                 62
 110
 111 #define MMC_CMD62_ARG1                  0xefac62ec
 112 #define MMC_CMD62_ARG2                  0xcbaea7
 113
 114
 115 #define SD_CMD_SEND_RELATIVE_ADDR       3
 116 #define SD_CMD_SWITCH_FUNC              6
 117 #define SD_CMD_SEND_IF_COND             8
 118 #define SD_CMD_SWITCH_UHS18V            11
 119
 120 #define SD_CMD_APP_SET_BUS_WIDTH        6
 121 #define SD_CMD_APP_SD_STATUS            13
 122 #define SD_CMD_ERASE_WR_BLK_START       32
 123 #define SD_CMD_ERASE_WR_BLK_END         33
 124 #define SD_CMD_APP_SEND_OP_COND         41
 125 #define SD_CMD_APP_SEND_SCR             51
 126
 127 static inline bool mmc_is_tuning_cmd(uint cmdidx)
 128 {
 129         if ((cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) ||
 130             (cmdidx == MMC_CMD_SEND_TUNING_BLOCK))
 131                 return true;
 132         return false;
 133 }
 134
 135 /* SCR definitions in different words */
 136 #define SD_HIGHSPEED_BUSY       0x00020000
 137 #define SD_HIGHSPEED_SUPPORTED  0x00020000
 138
 139 #define UHS_SDR12_BUS_SPEED     0
 140 #define HIGH_SPEED_BUS_SPEED    1
 141 #define UHS_SDR25_BUS_SPEED     1
 142 #define UHS_SDR50_BUS_SPEED     2
 143 #define UHS_SDR104_BUS_SPEED    3
 144 #define UHS_DDR50_BUS_SPEED     4
 145
 146 #define SD_MODE_UHS_SDR12       BIT(UHS_SDR12_BUS_SPEED)
 147 #define SD_MODE_UHS_SDR25       BIT(UHS_SDR25_BUS_SPEED)
 148 #define SD_MODE_UHS_SDR50       BIT(UHS_SDR50_BUS_SPEED)
 149 #define SD_MODE_UHS_SDR104      BIT(UHS_SDR104_BUS_SPEED)
 150 #define SD_MODE_UHS_DDR50       BIT(UHS_DDR50_BUS_SPEED)
 151
 152 #define OCR_BUSY                0x80000000
 153 #define OCR_HCS                 0x40000000
 154 #define OCR_S18R                0x1000000
 155 #define OCR_VOLTAGE_MASK        0x007FFF80
 156 #define OCR_ACCESS_MODE         0x60000000
 157
 158 #define MMC_ERASE_ARG           0x00000000
 159 #define MMC_SECURE_ERASE_ARG    0x80000000
 160 #define MMC_TRIM_ARG            0x00000001
 161 #define MMC_DISCARD_ARG         0x00000003
 162 #define MMC_SECURE_TRIM1_ARG    0x80000001
 163 #define MMC_SECURE_TRIM2_ARG    0x80008000
 164
 165 #define MMC_STATUS_MASK         (~0x0206BF7F)
 166 #define MMC_STATUS_SWITCH_ERROR (1 << 7)
 167 #define MMC_STATUS_RDY_FOR_DATA (1 << 8)
 168 #define MMC_STATUS_CURR_STATE   (0xf << 9)
 169 #define MMC_STATUS_ERROR        (1 << 19)
 170
 171 #define MMC_STATE_PRG           (7 << 9)
 172
 173 #define MMC_VDD_165_195         0x00000080      /* VDD voltage 1.65 - 1.95 */
 174 #define MMC_VDD_20_21           0x00000100      /* VDD voltage 2.0 ~ 2.1 */
 175 #define MMC_VDD_21_22           0x00000200      /* VDD voltage 2.1 ~ 2.2 */
 176 #define MMC_VDD_22_23           0x00000400      /* VDD voltage 2.2 ~ 2.3 */
 177 #define MMC_VDD_23_24           0x00000800      /* VDD voltage 2.3 ~ 2.4 */
 178 #define MMC_VDD_24_25           0x00001000      /* VDD voltage 2.4 ~ 2.5 */
 179 #define MMC_VDD_25_26           0x00002000      /* VDD voltage 2.5 ~ 2.6 */
 180 #define MMC_VDD_26_27           0x00004000      /* VDD voltage 2.6 ~ 2.7 */
 181 #define MMC_VDD_27_28           0x00008000      /* VDD voltage 2.7 ~ 2.8 */
 182 #define MMC_VDD_28_29           0x00010000      /* VDD voltage 2.8 ~ 2.9 */
 183 #define MMC_VDD_29_30           0x00020000      /* VDD voltage 2.9 ~ 3.0 */
 184 #define MMC_VDD_30_31           0x00040000      /* VDD voltage 3.0 ~ 3.1 */
 185 #define MMC_VDD_31_32           0x00080000      /* VDD voltage 3.1 ~ 3.2 */
 186 #define MMC_VDD_32_33           0x00100000      /* VDD voltage 3.2 ~ 3.3 */
 187 #define MMC_VDD_33_34           0x00200000      /* VDD voltage 3.3 ~ 3.4 */
 188 #define MMC_VDD_34_35           0x00400000      /* VDD voltage 3.4 ~ 3.5 */
 189 #define MMC_VDD_35_36           0x00800000      /* VDD voltage 3.5 ~ 3.6 */
 190
 191 #define MMC_SWITCH_MODE_CMD_SET         0x00 /* Change the command set */
 192 #define MMC_SWITCH_MODE_SET_BITS        0x01 /* Set bits in EXT_CSD byte
 193                                                 addressed by index which are
 194                                                 1 in value field */
 195 #define MMC_SWITCH_MODE_CLEAR_BITS      0x02 /* Clear bits in EXT_CSD byte
 196                                                 addressed by index, which are
 197                                                 1 in value field */
 198 #define MMC_SWITCH_MODE_WRITE_BYTE      0x03 /* Set target byte to value */
 199
 200 #define SD_SWITCH_CHECK         0
 201 #define SD_SWITCH_SWITCH        1
 202
 203 /*
 204  * EXT_CSD fields
 205  */
 206 #define EXT_CSD_ENH_START_ADDR          136     /* R/W */
 207 #define EXT_CSD_ENH_SIZE_MULT           140     /* R/W */
 208 #define EXT_CSD_GP_SIZE_MULT            143     /* R/W */
 209 #define EXT_CSD_PARTITION_SETTING       155     /* R/W */
 210 #define EXT_CSD_PARTITIONS_ATTRIBUTE    156     /* R/W */
 211 #define EXT_CSD_MAX_ENH_SIZE_MULT       157     /* R */
 212 #define EXT_CSD_PARTITIONING_SUPPORT    160     /* RO */
 213 #define EXT_CSD_RST_N_FUNCTION          162     /* R/W */
 214 #define EXT_CSD_BKOPS_EN                163     /* R/W & R/W/E */
 215 #define EXT_CSD_WR_REL_PARAM            166     /* R */
 216 #define EXT_CSD_WR_REL_SET              167     /* R/W */
 217 #define EXT_CSD_RPMB_MULT               168     /* RO */
 218 #define EXT_CSD_ERASE_GROUP_DEF         175     /* R/W */
 219 #define EXT_CSD_BOOT_BUS_WIDTH          177
 220 #define EXT_CSD_PART_CONF               179     /* R/W */
 221 #define EXT_CSD_BUS_WIDTH               183     /* R/W */
 222 #define EXT_CSD_HS_TIMING               185     /* R/W */
 223 #define EXT_CSD_REV                     192     /* RO */
 224 #define EXT_CSD_CARD_TYPE               196     /* RO */
 225 #define EXT_CSD_SEC_CNT                 212     /* RO, 4 bytes */
 226 #define EXT_CSD_HC_WP_GRP_SIZE          221     /* RO */
 227 #define EXT_CSD_HC_ERASE_GRP_SIZE       224     /* RO */
 228 #define EXT_CSD_BOOT_MULT               226     /* RO */
 229 #define EXT_CSD_BKOPS_SUPPORT           502     /* RO */
 230
 231 /*
 232  * EXT_CSD field definitions
 233  */
 234
 235 #define EXT_CSD_CMD_SET_NORMAL          (1 << 0)
 236 #define EXT_CSD_CMD_SET_SECURE          (1 << 1)
 237 #define EXT_CSD_CMD_SET_CPSECURE        (1 << 2)
 238
 239 #define EXT_CSD_CARD_TYPE_26    (1 << 0)        /* Card can run at 26MHz */
 240 #define EXT_CSD_CARD_TYPE_52    (1 << 1)        /* Card can run at 52MHz */
 241 #define EXT_CSD_CARD_TYPE_DDR_1_8V      (1 << 2)
 242 #define EXT_CSD_CARD_TYPE_DDR_1_2V      (1 << 3)
 243 #define EXT_CSD_CARD_TYPE_DDR_52        (EXT_CSD_CARD_TYPE_DDR_1_8V \
 244                                         | EXT_CSD_CARD_TYPE_DDR_1_2V)
 245
 246 #define EXT_CSD_CARD_TYPE_HS200_1_8V    BIT(4)  /* Card can run at 200MHz */
 247                                                 /* SDR mode @1.8V I/O */
 248 #define EXT_CSD_CARD_TYPE_HS200_1_2V    BIT(5)  /* Card can run at 200MHz */
 249                                                 /* SDR mode @1.2V I/O */
 250 #define EXT_CSD_CARD_TYPE_HS200         (EXT_CSD_CARD_TYPE_HS200_1_8V | \
 251                                          EXT_CSD_CARD_TYPE_HS200_1_2V)
 252 #define EXT_CSD_CARD_TYPE_HS400_1_8V    BIT(6)
 253 #define EXT_CSD_CARD_TYPE_HS400_1_2V    BIT(7)
 254 #define EXT_CSD_CARD_TYPE_HS400         (EXT_CSD_CARD_TYPE_HS400_1_8V | \
 255                                          EXT_CSD_CARD_TYPE_HS400_1_2V)
 256
 257 #define EXT_CSD_BUS_WIDTH_1     0       /* Card is in 1 bit mode */
 258 #define EXT_CSD_BUS_WIDTH_4     1       /* Card is in 4 bit mode */
 259 #define EXT_CSD_BUS_WIDTH_8     2       /* Card is in 8 bit mode */
 260 #define EXT_CSD_DDR_BUS_WIDTH_4 5       /* Card is in 4 bit DDR mode */
 261 #define EXT_CSD_DDR_BUS_WIDTH_8 6       /* Card is in 8 bit DDR mode */
 262 #define EXT_CSD_DDR_FLAG        BIT(2)  /* Flag for DDR mode */
 263
 264 #define EXT_CSD_TIMING_LEGACY   0       /* no high speed */
 265 #define EXT_CSD_TIMING_HS       1       /* HS */
 266 #define EXT_CSD_TIMING_HS200    2       /* HS200 */
 267 #define EXT_CSD_TIMING_HS400    3       /* HS400 */
 268
 269 #define EXT_CSD_BOOT_ACK_ENABLE                 (1 << 6)
 270 #define EXT_CSD_BOOT_PARTITION_ENABLE           (1 << 3)
 271 #define EXT_CSD_PARTITION_ACCESS_ENABLE         (1 << 0)
 272 #define EXT_CSD_PARTITION_ACCESS_DISABLE        (0 << 0)
 273
 274 #define EXT_CSD_BOOT_ACK(x)             (x << 6)
 275 #define EXT_CSD_BOOT_PART_NUM(x)        (x << 3)
 276 #define EXT_CSD_PARTITION_ACCESS(x)     (x << 0)
 277
 278 #define EXT_CSD_EXTRACT_BOOT_ACK(x)             (((x) >> 6) & 0x1)
 279 #define EXT_CSD_EXTRACT_BOOT_PART(x)            (((x) >> 3) & 0x7)
 280 #define EXT_CSD_EXTRACT_PARTITION_ACCESS(x)     ((x) & 0x7)
 281
 282 #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x)  (x << 3)
 283 #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
 284 #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
 285
 286 #define EXT_CSD_PARTITION_SETTING_COMPLETED     (1 << 0)
 287
 288 #define EXT_CSD_ENH_USR         (1 << 0)        /* user data area is enhanced */
 289 #define EXT_CSD_ENH_GP(x)       (1 << ((x)+1))  /* GP part (x+1) is enhanced */
 290
 291 #define EXT_CSD_HS_CTRL_REL     (1 << 0)        /* host controlled WR_REL_SET */
 292
 293 #define EXT_CSD_WR_DATA_REL_USR         (1 << 0)        /* user data area WR_REL */
 294 #define EXT_CSD_WR_DATA_REL_GP(x)       (1 << ((x)+1))  /* GP part (x+1) WR_REL */
 295
 296 #define R1_ILLEGAL_COMMAND              (1 << 22)
 297 #define R1_APP_CMD                      (1 << 5)
 298
 299 #define MMC_RSP_PRESENT (1 << 0)
 300 #define MMC_RSP_136     (1 << 1)                /* 136 bit response */
 301 #define MMC_RSP_CRC     (1 << 2)                /* expect valid crc */
 302 #define MMC_RSP_BUSY    (1 << 3)                /* card may send busy */
 303 #define MMC_RSP_OPCODE  (1 << 4)                /* response contains opcode */
 304
 305 #define MMC_RSP_NONE    (0)
 306 #define MMC_RSP_R1      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 307 #define MMC_RSP_R1b     (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
 308                         MMC_RSP_BUSY)
 309 #define MMC_RSP_R2      (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
 310 #define MMC_RSP_R3      (MMC_RSP_PRESENT)
 311 #define MMC_RSP_R4      (MMC_RSP_PRESENT)
 312 #define MMC_RSP_R5      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 313 #define MMC_RSP_R6      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 314 #define MMC_RSP_R7      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 315
 316 #define MMCPART_NOAVAILABLE     (0xff)
 317 #define PART_ACCESS_MASK        (0x7)
 318 #define PART_SUPPORT            (0x1)
 319 #define ENHNCD_SUPPORT          (0x2)
 320 #define PART_ENH_ATTRIB         (0x1f)
 321
 322 #define MMC_QUIRK_RETRY_SEND_CID        BIT(0)
 323 #define MMC_QUIRK_RETRY_SET_BLOCKLEN    BIT(1)
 324
 325 enum mmc_voltage {
 326         MMC_SIGNAL_VOLTAGE_000 = 0,
 327         MMC_SIGNAL_VOLTAGE_120 = 1,
 328         MMC_SIGNAL_VOLTAGE_180 = 2,
 329         MMC_SIGNAL_VOLTAGE_330 = 4,
 330 };
 331
 332 #define MMC_ALL_SIGNAL_VOLTAGE (MMC_SIGNAL_VOLTAGE_120 |\
 333                                 MMC_SIGNAL_VOLTAGE_180 |\
 334                                 MMC_SIGNAL_VOLTAGE_330)
 335
 336 /* Maximum block size for MMC */
 337 #define MMC_MAX_BLOCK_LEN       512
 338
 339 /* The number of MMC physical partitions.  These consist of:
 340  * boot partitions (2), general purpose partitions (4) in MMC v4.4.
 341  */
 342 #define MMC_NUM_BOOT_PARTITION  2
 343 #define MMC_PART_RPMB           3       /* RPMB partition number */
 344
 345 /* Driver model support */
 346
 347 /**
 348  * struct mmc_uclass_priv - Holds information about a device used by the uclass
 349  */
 350 struct mmc_uclass_priv {
 351         struct mmc *mmc;
 352 };
 353
 354 /**
 355  * mmc_get_mmc_dev() - get the MMC struct pointer for a device
 356  *
 357  * Provided that the device is already probed and ready for use, this value
 358  * will be available.
 359  *
 360  * @dev:        Device
 361  * @return associated mmc struct pointer if available, else NULL
 362  */
 363 struct mmc *mmc_get_mmc_dev(struct udevice *dev);
 364
 365 /* End of driver model support */
 366
 367 struct mmc_cid {
 368         unsigned long psn;
 369         unsigned short oid;
 370         unsigned char mid;
 371         unsigned char prv;
 372         unsigned char mdt;
 373         char pnm[7];
 374 };
 375
 376 struct mmc_cmd {
 377         ushort cmdidx;
 378         uint resp_type;
 379         uint cmdarg;
 380         uint response[4];
 381 };
 382
 383 struct mmc_data {
 384         union {
 385                 char *dest;
 386                 const char *src; /* src buffers don't get written to */
 387         };
 388         uint flags;
 389         uint blocks;
 390         uint blocksize;
 391 };
 392
 393 /* forward decl. */
 394 struct mmc;
 395
 396 #if CONFIG_IS_ENABLED(DM_MMC)
 397 struct dm_mmc_ops {
 398         /**
 399          * send_cmd() - Send a command to the MMC device
 400          *
 401          * @dev:        Device to receive the command
 402          * @cmd:        Command to send
 403          * @data:       Additional data to send/receive
 404          * @return 0 if OK, -ve on error
 405          */
 406         int (*send_cmd)(struct udevice *dev, struct mmc_cmd *cmd,
 407                         struct mmc_data *data);
 408
 409         /**
 410          * set_ios() - Set the I/O speed/width for an MMC device
 411          *
 412          * @dev:        Device to update
 413          * @return 0 if OK, -ve on error
 414          */
 415         int (*set_ios)(struct udevice *dev);
 416
 417         /**
 418          * send_init_stream() - send the initialization stream: 74 clock cycles
 419          * This is used after power up before sending the first command
 420          *
 421          * @dev:        Device to update
 422          */
 423         void (*send_init_stream)(struct udevice *dev);
 424
 425         /**
 426          * get_cd() - See whether a card is present
 427          *
 428          * @dev:        Device to check
 429          * @return 0 if not present, 1 if present, -ve on error
 430          */
 431         int (*get_cd)(struct udevice *dev);
 432
 433         /**
 434          * get_wp() - See whether a card has write-protect enabled
 435          *
 436          * @dev:        Device to check
 437          * @return 0 if write-enabled, 1 if write-protected, -ve on error
 438          */
 439         int (*get_wp)(struct udevice *dev);
 440
 441 #ifdef MMC_SUPPORTS_TUNING
 442         /**
 443          * execute_tuning() - Start the tuning process
 444          *
 445          * @dev:        Device to start the tuning
 446          * @opcode:     Command opcode to send
 447          * @return 0 if OK, -ve on error
 448          */
 449         int (*execute_tuning)(struct udevice *dev, uint opcode);
 450 #endif
 451
 452 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 453         /**
 454          * wait_dat0() - wait until dat0 is in the target state
 455          *              (CLK must be running during the wait)
 456          *
 457          * @dev:        Device to check
 458          * @state:      target state
 459          * @timeout:    timeout in us
 460          * @return 0 if dat0 is in the target state, -ve on error
 461          */
 462         int (*wait_dat0)(struct udevice *dev, int state, int timeout);
 463 #endif
 464 };
 465
 466 #define mmc_get_ops(dev)        ((struct dm_mmc_ops *)(dev)->driver->ops)
 467
 468 int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 469                     struct mmc_data *data);
 470 int dm_mmc_set_ios(struct udevice *dev);
 471 void dm_mmc_send_init_stream(struct udevice *dev);
 472 int dm_mmc_get_cd(struct udevice *dev);
 473 int dm_mmc_get_wp(struct udevice *dev);
 474 int dm_mmc_execute_tuning(struct udevice *dev, uint opcode);
 475 int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout);
 476
 477 /* Transition functions for compatibility */
 478 int mmc_set_ios(struct mmc *mmc);
 479 void mmc_send_init_stream(struct mmc *mmc);
 480 int mmc_getcd(struct mmc *mmc);
 481 int mmc_getwp(struct mmc *mmc);
 482 int mmc_execute_tuning(struct mmc *mmc, uint opcode);
 483 int mmc_wait_dat0(struct mmc *mmc, int state, int timeout);
 484
 485 #else
 486 struct mmc_ops {
 487         int (*send_cmd)(struct mmc *mmc,
 488                         struct mmc_cmd *cmd, struct mmc_data *data);
 489         int (*set_ios)(struct mmc *mmc);
 490         int (*init)(struct mmc *mmc);
 491         int (*getcd)(struct mmc *mmc);
 492         int (*getwp)(struct mmc *mmc);
 493 };
 494 #endif
 495
 496 struct mmc_config {
 497         const char *name;
 498 #if !CONFIG_IS_ENABLED(DM_MMC)
 499         const struct mmc_ops *ops;
 500 #endif
 501         uint host_caps;
 502         uint voltages;
 503         uint f_min;
 504         uint f_max;
 505         uint b_max;
 506         unsigned char part_type;
 507 };
 508
 509 struct sd_ssr {
 510         unsigned int au;                /* In sectors */
 511         unsigned int erase_timeout;     /* In milliseconds */
 512         unsigned int erase_offset;      /* In milliseconds */
 513 };
 514
 515 enum bus_mode {
 516         MMC_LEGACY,
 517         SD_LEGACY,
 518         MMC_HS,
 519         SD_HS,
 520         MMC_HS_52,
 521         MMC_DDR_52,
 522         UHS_SDR12,
 523         UHS_SDR25,
 524         UHS_SDR50,
 525         UHS_DDR50,
 526         UHS_SDR104,
 527         MMC_HS_200,
 528         MMC_HS_400,
 529         MMC_MODES_END
 530 };
 531
 532 const char *mmc_mode_name(enum bus_mode mode);
 533 void mmc_dump_capabilities(const char *text, uint caps);
 534
 535 static inline bool mmc_is_mode_ddr(enum bus_mode mode)
 536 {
 537         if (mode == MMC_DDR_52)
 538                 return true;
 539 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 540         else if (mode == UHS_DDR50)
 541                 return true;
 542 #endif
 543 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 544         else if (mode == MMC_HS_400)
 545                 return true;
 546 #endif
 547         else
 548                 return false;
 549 }
 550
 551 #define UHS_CAPS (MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) | \
 552                   MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_SDR104) | \
 553                   MMC_CAP(UHS_DDR50))
 554
 555 static inline bool supports_uhs(uint caps)
 556 {
 557 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 558         return (caps & UHS_CAPS) ? true : false;
 559 #else
 560         return false;
 561 #endif
 562 }
 563
 564 /*
 565  * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device
 566  * with mmc_get_mmc_dev().
 567  *
 568  * TODO struct mmc should be in mmc_private but it's hard to fix right now
 569  */
 570 struct mmc {
 571 #if !CONFIG_IS_ENABLED(BLK)
 572         struct list_head link;
 573 #endif
 574         const struct mmc_config *cfg;   /* provided configuration */
 575         uint version;
 576         void *priv;
 577         uint has_init;
 578         int high_capacity;
 579         bool clk_disable; /* true if the clock can be turned off */
 580         uint bus_width;
 581         uint clock;
 582         enum mmc_voltage signal_voltage;
 583         uint card_caps;
 584         uint host_caps;
 585         uint ocr;
 586         uint dsr;
 587         uint dsr_imp;
 588         uint scr[2];
 589         uint csd[4];
 590         uint cid[4];
 591         ushort rca;
 592         u8 part_support;
 593         u8 part_attr;
 594         u8 wr_rel_set;
 595         u8 part_config;
 596         uint tran_speed;
 597         uint legacy_speed; /* speed for the legacy mode provided by the card */
 598         uint read_bl_len;
 599 #if CONFIG_IS_ENABLED(MMC_WRITE)
 600         uint write_bl_len;
 601         uint erase_grp_size;    /* in 512-byte sectors */
 602 #endif
 603 #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
 604         uint hc_wp_grp_size;    /* in 512-byte sectors */
 605 #endif
 606 #if CONFIG_IS_ENABLED(MMC_WRITE)
 607         struct sd_ssr   ssr;    /* SD status register */
 608 #endif
 609         u64 capacity;
 610         u64 capacity_user;
 611         u64 capacity_boot;
 612         u64 capacity_rpmb;
 613         u64 capacity_gp[4];
 614 #ifndef CONFIG_SPL_BUILD
 615         u64 enh_user_start;
 616         u64 enh_user_size;
 617 #endif
 618 #if !CONFIG_IS_ENABLED(BLK)
 619         struct blk_desc block_dev;
 620 #endif
 621         char op_cond_pending;   /* 1 if we are waiting on an op_cond command */
 622         char init_in_progress;  /* 1 if we have done mmc_start_init() */
 623         char preinit;           /* start init as early as possible */
 624         int ddr_mode;
 625 #if CONFIG_IS_ENABLED(DM_MMC)
 626         struct udevice *dev;    /* Device for this MMC controller */
 627 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 628         struct udevice *vmmc_supply;    /* Main voltage regulator (Vcc)*/
 629         struct udevice *vqmmc_supply;   /* IO voltage regulator (Vccq)*/
 630 #endif
 631 #endif
 632         u8 *ext_csd;
 633         u32 cardtype;           /* cardtype read from the MMC */
 634         enum mmc_voltage current_voltage;
 635         enum bus_mode selected_mode; /* mode currently used */
 636         enum bus_mode best_mode; /* best mode is the supported mode with the
 637                                   * highest bandwidth. It may not always be the
 638                                   * operating mode due to limitations when
 639                                   * accessing the boot partitions
 640                                   */
 641         u32 quirks;
 642 };
 643
 644 struct mmc_hwpart_conf {
 645         struct {
 646                 uint enh_start; /* in 512-byte sectors */
 647                 uint enh_size;  /* in 512-byte sectors, if 0 no enh area */
 648                 unsigned wr_rel_change : 1;
 649                 unsigned wr_rel_set : 1;
 650         } user;
 651         struct {
 652                 uint size;      /* in 512-byte sectors */
 653                 unsigned enhanced : 1;
 654                 unsigned wr_rel_change : 1;
 655                 unsigned wr_rel_set : 1;
 656         } gp_part[4];
 657 };
 658
 659 enum mmc_hwpart_conf_mode {
 660         MMC_HWPART_CONF_CHECK,
 661         MMC_HWPART_CONF_SET,
 662         MMC_HWPART_CONF_COMPLETE,
 663 };
 664
 665 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
 666
 667 /**
 668  * mmc_bind() - Set up a new MMC device ready for probing
 669  *
 670  * A child block device is bound with the IF_TYPE_MMC interface type. This
 671  * allows the device to be used with CONFIG_BLK
 672  *
 673  * @dev:        MMC device to set up
 674  * @mmc:        MMC struct
 675  * @cfg:        MMC configuration
 676  * @return 0 if OK, -ve on error
 677  */
 678 int mmc_bind(struct udevice *dev, struct mmc *mmc,
 679              const struct mmc_config *cfg);
 680 void mmc_destroy(struct mmc *mmc);
 681
 682 /**
 683  * mmc_unbind() - Unbind a MMC device's child block device
 684  *
 685  * @dev:        MMC device
 686  * @return 0 if OK, -ve on error
 687  */
 688 int mmc_unbind(struct udevice *dev);
 689 int mmc_initialize(bd_t *bis);
 690 int mmc_init(struct mmc *mmc);
 691 int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error);
 692
 693 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
 694     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 695     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 696 int mmc_deinit(struct mmc *mmc);
 697 #endif
 698
 699 /**
 700  * mmc_of_parse() - Parse the device tree to get the capabilities of the host
 701  *
 702  * @dev:        MMC device
 703  * @cfg:        MMC configuration
 704  * @return 0 if OK, -ve on error
 705  */
 706 int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg);
 707
 708 int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
 709
 710 /**
 711  * mmc_voltage_to_mv() - Convert a mmc_voltage in mV
 712  *
 713  * @voltage:    The mmc_voltage to convert
 714  * @return the value in mV if OK, -EINVAL on error (invalid mmc_voltage value)
 715  */
 716 int mmc_voltage_to_mv(enum mmc_voltage voltage);
 717
 718 /**
 719  * mmc_set_clock() - change the bus clock
 720  * @mmc:        MMC struct
 721  * @clock:      bus frequency in Hz
 722  * @disable:    flag indicating if the clock must on or off
 723  * @return 0 if OK, -ve on error
 724  */
 725 int mmc_set_clock(struct mmc *mmc, uint clock, bool disable);
 726
 727 #define MMC_CLK_ENABLE          false
 728 #define MMC_CLK_DISABLE         true
 729
 730 struct mmc *find_mmc_device(int dev_num);
 731 int mmc_set_dev(int dev_num);
 732 void print_mmc_devices(char separator);
 733
 734 /**
 735  * get_mmc_num() - get the total MMC device number
 736  *
 737  * @return 0 if there is no MMC device, else the number of devices
 738  */
 739 int get_mmc_num(void);
 740 int mmc_switch_part(struct mmc *mmc, unsigned int part_num);
 741 int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
 742                       enum mmc_hwpart_conf_mode mode);
 743
 744 #if !CONFIG_IS_ENABLED(DM_MMC)
 745 int mmc_getcd(struct mmc *mmc);
 746 int board_mmc_getcd(struct mmc *mmc);
 747 int mmc_getwp(struct mmc *mmc);
 748 int board_mmc_getwp(struct mmc *mmc);
 749 #endif
 750
 751 int mmc_set_dsr(struct mmc *mmc, u16 val);
 752 /* Function to change the size of boot partition and rpmb partitions */
 753 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
 754                                         unsigned long rpmbsize);
 755 /* Function to modify the PARTITION_CONFIG field of EXT_CSD */
 756 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
 757 /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
 758 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
 759 /* Function to modify the RST_n_FUNCTION field of EXT_CSD */
 760 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
 761 /* Functions to read / write the RPMB partition */
 762 int mmc_rpmb_set_key(struct mmc *mmc, void *key);
 763 int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
 764 int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
 765                   unsigned short cnt, unsigned char *key);
 766 int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
 767                    unsigned short cnt, unsigned char *key);
 768
 769 /**
 770  * mmc_rpmb_route_frames() - route RPMB data frames
 771  * @mmc         Pointer to a MMC device struct
 772  * @req         Request data frames
 773  * @reqlen      Length of data frames in bytes
 774  * @rsp         Supplied buffer for response data frames
 775  * @rsplen      Length of supplied buffer for response data frames
 776  *
 777  * The RPMB data frames are routed to/from some external entity, for
 778  * example a Trusted Exectuion Environment in an arm TrustZone protected
 779  * secure world. It's expected that it's the external entity who is in
 780  * control of the RPMB key.
 781  *
 782  * Returns 0 on success, < 0 on error.
 783  */
 784 int mmc_rpmb_route_frames(struct mmc *mmc, void *req, unsigned long reqlen,
 785                           void *rsp, unsigned long rsplen);
 786
 787 #ifdef CONFIG_CMD_BKOPS_ENABLE
 788 int mmc_set_bkops_enable(struct mmc *mmc);
 789 #endif
 790
 791 /**
 792  * Start device initialization and return immediately; it does not block on
 793  * polling OCR (operation condition register) status. Useful for checking
 794  * the presence of SD/eMMC when no card detect logic is available.
 795  *
 796  * @param mmc   Pointer to a MMC device struct
 797  * @return 0 on success, <0 on error.
 798  */
 799 int mmc_get_op_cond(struct mmc *mmc);
 800
 801 /**
 802  * Start device initialization and return immediately; it does not block on
 803  * polling OCR (operation condition register) status.  Then you should call
 804  * mmc_init, which would block on polling OCR status and complete the device
 805  * initializatin.
 806  *
 807  * @param mmc   Pointer to a MMC device struct
 808  * @return 0 on success, <0 on error.
 809  */
 810 int mmc_start_init(struct mmc *mmc);
 811
 812 /**
 813  * Set preinit flag of mmc device.
 814  *
 815  * This will cause the device to be pre-inited during mmc_initialize(),
 816  * which may save boot time if the device is not accessed until later.
 817  * Some eMMC devices take 200-300ms to init, but unfortunately they
 818  * must be sent a series of commands to even get them to start preparing
 819  * for operation.
 820  *
 821  * @param mmc           Pointer to a MMC device struct
 822  * @param preinit       preinit flag value
 823  */
 824 void mmc_set_preinit(struct mmc *mmc, int preinit);
 825
 826 #ifdef CONFIG_MMC_SPI
 827 #define mmc_host_is_spi(mmc)    ((mmc)->cfg->host_caps & MMC_MODE_SPI)
 828 #else
 829 #define mmc_host_is_spi(mmc)    0
 830 #endif
 831 struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
 832
 833 void board_mmc_power_init(void);
 834 int board_mmc_init(bd_t *bis);
 835 int cpu_mmc_init(bd_t *bis);
 836 int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
 837 # ifdef CONFIG_SYS_MMC_ENV_PART
 838 extern uint mmc_get_env_part(struct mmc *mmc);
 839 # endif
 840 int mmc_get_env_dev(void);
 841
 842 /* Set block count limit because of 16 bit register limit on some hardware*/
 843 #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
 844 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
 845 #endif
 846
 847 /**
 848  * mmc_get_blk_desc() - Get the block descriptor for an MMC device
 849  *
 850  * @mmc:        MMC device
 851  * @return block device if found, else NULL
 852  */
 853 struct blk_desc *mmc_get_blk_desc(struct mmc *mmc);
 854
 855 #endif /* _MMC_H_ */