include/mmc.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2008,2010 Freescale Semiconductor, Inc
   4  * Andy Fleming
   5  *
   6  * Based (loosely) on the Linux code
   7  */
   8
   9 #ifndef _MMC_H_
  10 #define _MMC_H_
  11
  12 #include <linux/bitops.h>
  13 #include <linux/list.h>
  14 #include <linux/sizes.h>
  15 #include <linux/compiler.h>
  16 #include <linux/dma-direction.h>
  17 #include <part.h>
  18
  19 struct bd_info;
  20
  21 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
  22 #define MMC_SUPPORTS_TUNING
  23 #endif
  24 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  25 #define MMC_SUPPORTS_TUNING
  26 #endif
  27
  28 /* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */
  29 #define SD_VERSION_SD   (1U << 31)
  30 #define MMC_VERSION_MMC (1U << 30)
  31
  32 #define MAKE_SDMMC_VERSION(a, b, c)     \
  33         ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c))
  34 #define MAKE_SD_VERSION(a, b, c)        \
  35         (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c))
  36 #define MAKE_MMC_VERSION(a, b, c)       \
  37         (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c))
  38
  39 #define EXTRACT_SDMMC_MAJOR_VERSION(x)  \
  40         (((u32)(x) >> 16) & 0xff)
  41 #define EXTRACT_SDMMC_MINOR_VERSION(x)  \
  42         (((u32)(x) >> 8) & 0xff)
  43 #define EXTRACT_SDMMC_CHANGE_VERSION(x) \
  44         ((u32)(x) & 0xff)
  45
  46 #define SD_VERSION_3            MAKE_SD_VERSION(3, 0, 0)
  47 #define SD_VERSION_2            MAKE_SD_VERSION(2, 0, 0)
  48 #define SD_VERSION_1_0          MAKE_SD_VERSION(1, 0, 0)
  49 #define SD_VERSION_1_10         MAKE_SD_VERSION(1, 10, 0)
  50
  51 #define MMC_VERSION_UNKNOWN     MAKE_MMC_VERSION(0, 0, 0)
  52 #define MMC_VERSION_1_2         MAKE_MMC_VERSION(1, 2, 0)
  53 #define MMC_VERSION_1_4         MAKE_MMC_VERSION(1, 4, 0)
  54 #define MMC_VERSION_2_2         MAKE_MMC_VERSION(2, 2, 0)
  55 #define MMC_VERSION_3           MAKE_MMC_VERSION(3, 0, 0)
  56 #define MMC_VERSION_4           MAKE_MMC_VERSION(4, 0, 0)
  57 #define MMC_VERSION_4_1         MAKE_MMC_VERSION(4, 1, 0)
  58 #define MMC_VERSION_4_2         MAKE_MMC_VERSION(4, 2, 0)
  59 #define MMC_VERSION_4_3         MAKE_MMC_VERSION(4, 3, 0)
  60 #define MMC_VERSION_4_4         MAKE_MMC_VERSION(4, 4, 0)
  61 #define MMC_VERSION_4_41        MAKE_MMC_VERSION(4, 4, 1)
  62 #define MMC_VERSION_4_5         MAKE_MMC_VERSION(4, 5, 0)
  63 #define MMC_VERSION_5_0         MAKE_MMC_VERSION(5, 0, 0)
  64 #define MMC_VERSION_5_1         MAKE_MMC_VERSION(5, 1, 0)
  65
  66 #define MMC_CAP(mode)           (1 << mode)
  67 #define MMC_MODE_HS             (MMC_CAP(MMC_HS) | MMC_CAP(SD_HS))
  68 #define MMC_MODE_HS_52MHz       MMC_CAP(MMC_HS_52)
  69 #define MMC_MODE_DDR_52MHz      MMC_CAP(MMC_DDR_52)
  70 #define MMC_MODE_HS200          MMC_CAP(MMC_HS_200)
  71 #define MMC_MODE_HS400          MMC_CAP(MMC_HS_400)
  72 #define MMC_MODE_HS400_ES       MMC_CAP(MMC_HS_400_ES)
  73
  74 #define MMC_CAP_NONREMOVABLE    BIT(14)
  75 #define MMC_CAP_NEEDS_POLL      BIT(15)
  76 #define MMC_CAP_CD_ACTIVE_HIGH  BIT(16)
  77
  78 #define MMC_MODE_8BIT           BIT(30)
  79 #define MMC_MODE_4BIT           BIT(29)
  80 #define MMC_MODE_1BIT           BIT(28)
  81 #define MMC_MODE_SPI            BIT(27)
  82
  83
  84 #define SD_DATA_4BIT    0x00040000
  85
  86 #define IS_SD(x)        ((x)->version & SD_VERSION_SD)
  87 #define IS_MMC(x)       ((x)->version & MMC_VERSION_MMC)
  88
  89 #define MMC_DATA_READ           1
  90 #define MMC_DATA_WRITE          2
  91
  92 #define MMC_CMD_GO_IDLE_STATE           0
  93 #define MMC_CMD_SEND_OP_COND            1
  94 #define MMC_CMD_ALL_SEND_CID            2
  95 #define MMC_CMD_SET_RELATIVE_ADDR       3
  96 #define MMC_CMD_SET_DSR                 4
  97 #define MMC_CMD_SWITCH                  6
  98 #define MMC_CMD_SELECT_CARD             7
  99 #define MMC_CMD_SEND_EXT_CSD            8
 100 #define MMC_CMD_SEND_CSD                9
 101 #define MMC_CMD_SEND_CID                10
 102 #define MMC_CMD_STOP_TRANSMISSION       12
 103 #define MMC_CMD_SEND_STATUS             13
 104 #define MMC_CMD_SET_BLOCKLEN            16
 105 #define MMC_CMD_READ_SINGLE_BLOCK       17
 106 #define MMC_CMD_READ_MULTIPLE_BLOCK     18
 107 #define MMC_CMD_SEND_TUNING_BLOCK               19
 108 #define MMC_CMD_SEND_TUNING_BLOCK_HS200 21
 109 #define MMC_CMD_SET_BLOCK_COUNT         23
 110 #define MMC_CMD_WRITE_SINGLE_BLOCK      24
 111 #define MMC_CMD_WRITE_MULTIPLE_BLOCK    25
 112 #define MMC_CMD_ERASE_GROUP_START       35
 113 #define MMC_CMD_ERASE_GROUP_END         36
 114 #define MMC_CMD_ERASE                   38
 115 #define MMC_CMD_APP_CMD                 55
 116 #define MMC_CMD_SPI_READ_OCR            58
 117 #define MMC_CMD_SPI_CRC_ON_OFF          59
 118 #define MMC_CMD_RES_MAN                 62
 119
 120 #define MMC_CMD62_ARG1                  0xefac62ec
 121 #define MMC_CMD62_ARG2                  0xcbaea7
 122
 123
 124 #define SD_CMD_SEND_RELATIVE_ADDR       3
 125 #define SD_CMD_SWITCH_FUNC              6
 126 #define SD_CMD_SEND_IF_COND             8
 127 #define SD_CMD_SWITCH_UHS18V            11
 128
 129 #define SD_CMD_APP_SET_BUS_WIDTH        6
 130 #define SD_CMD_APP_SD_STATUS            13
 131 #define SD_CMD_ERASE_WR_BLK_START       32
 132 #define SD_CMD_ERASE_WR_BLK_END         33
 133 #define SD_CMD_APP_SEND_OP_COND         41
 134 #define SD_CMD_APP_SEND_SCR             51
 135
 136 static inline bool mmc_is_tuning_cmd(uint cmdidx)
 137 {
 138         if ((cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) ||
 139             (cmdidx == MMC_CMD_SEND_TUNING_BLOCK))
 140                 return true;
 141         return false;
 142 }
 143
 144 /* SCR definitions in different words */
 145 #define SD_HIGHSPEED_BUSY       0x00020000
 146 #define SD_HIGHSPEED_SUPPORTED  0x00020000
 147
 148 #define UHS_SDR12_BUS_SPEED     0
 149 #define HIGH_SPEED_BUS_SPEED    1
 150 #define UHS_SDR25_BUS_SPEED     1
 151 #define UHS_SDR50_BUS_SPEED     2
 152 #define UHS_SDR104_BUS_SPEED    3
 153 #define UHS_DDR50_BUS_SPEED     4
 154
 155 #define SD_MODE_UHS_SDR12       BIT(UHS_SDR12_BUS_SPEED)
 156 #define SD_MODE_UHS_SDR25       BIT(UHS_SDR25_BUS_SPEED)
 157 #define SD_MODE_UHS_SDR50       BIT(UHS_SDR50_BUS_SPEED)
 158 #define SD_MODE_UHS_SDR104      BIT(UHS_SDR104_BUS_SPEED)
 159 #define SD_MODE_UHS_DDR50       BIT(UHS_DDR50_BUS_SPEED)
 160
 161 #define OCR_BUSY                0x80000000
 162 #define OCR_HCS                 0x40000000
 163 #define OCR_S18R                0x1000000
 164 #define OCR_VOLTAGE_MASK        0x007FFF80
 165 #define OCR_ACCESS_MODE         0x60000000
 166
 167 #define MMC_ERASE_ARG           0x00000000
 168 #define MMC_SECURE_ERASE_ARG    0x80000000
 169 #define MMC_TRIM_ARG            0x00000001
 170 #define MMC_DISCARD_ARG         0x00000003
 171 #define MMC_SECURE_TRIM1_ARG    0x80000001
 172 #define MMC_SECURE_TRIM2_ARG    0x80008000
 173
 174 #define MMC_STATUS_MASK         (~0x0206BF7F)
 175 #define MMC_STATUS_SWITCH_ERROR (1 << 7)
 176 #define MMC_STATUS_RDY_FOR_DATA (1 << 8)
 177 #define MMC_STATUS_CURR_STATE   (0xf << 9)
 178 #define MMC_STATUS_ERROR        (1 << 19)
 179
 180 #define MMC_STATE_PRG           (7 << 9)
 181
 182 #define MMC_VDD_165_195         0x00000080      /* VDD voltage 1.65 - 1.95 */
 183 #define MMC_VDD_20_21           0x00000100      /* VDD voltage 2.0 ~ 2.1 */
 184 #define MMC_VDD_21_22           0x00000200      /* VDD voltage 2.1 ~ 2.2 */
 185 #define MMC_VDD_22_23           0x00000400      /* VDD voltage 2.2 ~ 2.3 */
 186 #define MMC_VDD_23_24           0x00000800      /* VDD voltage 2.3 ~ 2.4 */
 187 #define MMC_VDD_24_25           0x00001000      /* VDD voltage 2.4 ~ 2.5 */
 188 #define MMC_VDD_25_26           0x00002000      /* VDD voltage 2.5 ~ 2.6 */
 189 #define MMC_VDD_26_27           0x00004000      /* VDD voltage 2.6 ~ 2.7 */
 190 #define MMC_VDD_27_28           0x00008000      /* VDD voltage 2.7 ~ 2.8 */
 191 #define MMC_VDD_28_29           0x00010000      /* VDD voltage 2.8 ~ 2.9 */
 192 #define MMC_VDD_29_30           0x00020000      /* VDD voltage 2.9 ~ 3.0 */
 193 #define MMC_VDD_30_31           0x00040000      /* VDD voltage 3.0 ~ 3.1 */
 194 #define MMC_VDD_31_32           0x00080000      /* VDD voltage 3.1 ~ 3.2 */
 195 #define MMC_VDD_32_33           0x00100000      /* VDD voltage 3.2 ~ 3.3 */
 196 #define MMC_VDD_33_34           0x00200000      /* VDD voltage 3.3 ~ 3.4 */
 197 #define MMC_VDD_34_35           0x00400000      /* VDD voltage 3.4 ~ 3.5 */
 198 #define MMC_VDD_35_36           0x00800000      /* VDD voltage 3.5 ~ 3.6 */
 199
 200 #define MMC_SWITCH_MODE_CMD_SET         0x00 /* Change the command set */
 201 #define MMC_SWITCH_MODE_SET_BITS        0x01 /* Set bits in EXT_CSD byte
 202                                                 addressed by index which are
 203                                                 1 in value field */
 204 #define MMC_SWITCH_MODE_CLEAR_BITS      0x02 /* Clear bits in EXT_CSD byte
 205                                                 addressed by index, which are
 206                                                 1 in value field */
 207 #define MMC_SWITCH_MODE_WRITE_BYTE      0x03 /* Set target byte to value */
 208
 209 #define SD_SWITCH_CHECK         0
 210 #define SD_SWITCH_SWITCH        1
 211
 212 /*
 213  * EXT_CSD fields
 214  */
 215 #define EXT_CSD_ENH_START_ADDR          136     /* R/W */
 216 #define EXT_CSD_ENH_SIZE_MULT           140     /* R/W */
 217 #define EXT_CSD_GP_SIZE_MULT            143     /* R/W */
 218 #define EXT_CSD_PARTITION_SETTING       155     /* R/W */
 219 #define EXT_CSD_PARTITIONS_ATTRIBUTE    156     /* R/W */
 220 #define EXT_CSD_MAX_ENH_SIZE_MULT       157     /* R */
 221 #define EXT_CSD_PARTITIONING_SUPPORT    160     /* RO */
 222 #define EXT_CSD_RST_N_FUNCTION          162     /* R/W */
 223 #define EXT_CSD_BKOPS_EN                163     /* R/W & R/W/E */
 224 #define EXT_CSD_WR_REL_PARAM            166     /* R */
 225 #define EXT_CSD_WR_REL_SET              167     /* R/W */
 226 #define EXT_CSD_RPMB_MULT               168     /* RO */
 227 #define EXT_CSD_USER_WP                 171     /* R/W & R/W/C_P & R/W/E_P */
 228 #define EXT_CSD_BOOT_WP                 173     /* R/W & R/W/C_P */
 229 #define EXT_CSD_BOOT_WP_STATUS          174     /* R */
 230 #define EXT_CSD_ERASE_GROUP_DEF         175     /* R/W */
 231 #define EXT_CSD_BOOT_BUS_WIDTH          177
 232 #define EXT_CSD_PART_CONF               179     /* R/W */
 233 #define EXT_CSD_BUS_WIDTH               183     /* R/W */
 234 #define EXT_CSD_STROBE_SUPPORT          184     /* R/W */
 235 #define EXT_CSD_HS_TIMING               185     /* R/W */
 236 #define EXT_CSD_REV                     192     /* RO */
 237 #define EXT_CSD_CARD_TYPE               196     /* RO */
 238 #define EXT_CSD_PART_SWITCH_TIME        199     /* RO */
 239 #define EXT_CSD_SEC_CNT                 212     /* RO, 4 bytes */
 240 #define EXT_CSD_HC_WP_GRP_SIZE          221     /* RO */
 241 #define EXT_CSD_HC_ERASE_GRP_SIZE       224     /* RO */
 242 #define EXT_CSD_BOOT_MULT               226     /* RO */
 243 #define EXT_CSD_GENERIC_CMD6_TIME       248     /* RO */
 244 #define EXT_CSD_BKOPS_SUPPORT           502     /* RO */
 245
 246 /*
 247  * EXT_CSD field definitions
 248  */
 249
 250 #define EXT_CSD_CMD_SET_NORMAL          (1 << 0)
 251 #define EXT_CSD_CMD_SET_SECURE          (1 << 1)
 252 #define EXT_CSD_CMD_SET_CPSECURE        (1 << 2)
 253
 254 #define EXT_CSD_CARD_TYPE_26    (1 << 0)        /* Card can run at 26MHz */
 255 #define EXT_CSD_CARD_TYPE_52    (1 << 1)        /* Card can run at 52MHz */
 256 #define EXT_CSD_CARD_TYPE_DDR_1_8V      (1 << 2)
 257 #define EXT_CSD_CARD_TYPE_DDR_1_2V      (1 << 3)
 258 #define EXT_CSD_CARD_TYPE_DDR_52        (EXT_CSD_CARD_TYPE_DDR_1_8V \
 259                                         | EXT_CSD_CARD_TYPE_DDR_1_2V)
 260
 261 #define EXT_CSD_CARD_TYPE_HS200_1_8V    BIT(4)  /* Card can run at 200MHz */
 262                                                 /* SDR mode @1.8V I/O */
 263 #define EXT_CSD_CARD_TYPE_HS200_1_2V    BIT(5)  /* Card can run at 200MHz */
 264                                                 /* SDR mode @1.2V I/O */
 265 #define EXT_CSD_CARD_TYPE_HS200         (EXT_CSD_CARD_TYPE_HS200_1_8V | \
 266                                          EXT_CSD_CARD_TYPE_HS200_1_2V)
 267 #define EXT_CSD_CARD_TYPE_HS400_1_8V    BIT(6)
 268 #define EXT_CSD_CARD_TYPE_HS400_1_2V    BIT(7)
 269 #define EXT_CSD_CARD_TYPE_HS400         (EXT_CSD_CARD_TYPE_HS400_1_8V | \
 270                                          EXT_CSD_CARD_TYPE_HS400_1_2V)
 271
 272 #define EXT_CSD_BUS_WIDTH_1     0       /* Card is in 1 bit mode */
 273 #define EXT_CSD_BUS_WIDTH_4     1       /* Card is in 4 bit mode */
 274 #define EXT_CSD_BUS_WIDTH_8     2       /* Card is in 8 bit mode */
 275 #define EXT_CSD_DDR_BUS_WIDTH_4 5       /* Card is in 4 bit DDR mode */
 276 #define EXT_CSD_DDR_BUS_WIDTH_8 6       /* Card is in 8 bit DDR mode */
 277 #define EXT_CSD_DDR_FLAG        BIT(2)  /* Flag for DDR mode */
 278 #define EXT_CSD_BUS_WIDTH_STROBE BIT(7) /* Enhanced strobe mode */
 279
 280 #define EXT_CSD_TIMING_LEGACY   0       /* no high speed */
 281 #define EXT_CSD_TIMING_HS       1       /* HS */
 282 #define EXT_CSD_TIMING_HS200    2       /* HS200 */
 283 #define EXT_CSD_TIMING_HS400    3       /* HS400 */
 284 #define EXT_CSD_DRV_STR_SHIFT   4       /* Driver Strength shift */
 285
 286 #define EXT_CSD_BOOT_ACK_ENABLE                 (1 << 6)
 287 #define EXT_CSD_BOOT_PARTITION_ENABLE           (1 << 3)
 288 #define EXT_CSD_PARTITION_ACCESS_ENABLE         (1 << 0)
 289 #define EXT_CSD_PARTITION_ACCESS_DISABLE        (0 << 0)
 290
 291 #define EXT_CSD_BOOT_ACK(x)             (x << 6)
 292 #define EXT_CSD_BOOT_PART_NUM(x)        (x << 3)
 293 #define EXT_CSD_PARTITION_ACCESS(x)     (x << 0)
 294
 295 #define EXT_CSD_EXTRACT_BOOT_ACK(x)             (((x) >> 6) & 0x1)
 296 #define EXT_CSD_EXTRACT_BOOT_PART(x)            (((x) >> 3) & 0x7)
 297 #define EXT_CSD_EXTRACT_PARTITION_ACCESS(x)     ((x) & 0x7)
 298
 299 #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x)  (x << 3)
 300 #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
 301 #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
 302
 303 #define EXT_CSD_PARTITION_SETTING_COMPLETED     (1 << 0)
 304
 305 #define EXT_CSD_ENH_USR         (1 << 0)        /* user data area is enhanced */
 306 #define EXT_CSD_ENH_GP(x)       (1 << ((x)+1))  /* GP part (x+1) is enhanced */
 307
 308 #define EXT_CSD_HS_CTRL_REL     (1 << 0)        /* host controlled WR_REL_SET */
 309
 310 #define EXT_CSD_WR_DATA_REL_USR         (1 << 0)        /* user data area WR_REL */
 311 #define EXT_CSD_WR_DATA_REL_GP(x)       (1 << ((x)+1))  /* GP part (x+1) WR_REL */
 312
 313 #define R1_ILLEGAL_COMMAND              (1 << 22)
 314 #define R1_APP_CMD                      (1 << 5)
 315
 316 #define MMC_RSP_PRESENT (1 << 0)
 317 #define MMC_RSP_136     (1 << 1)                /* 136 bit response */
 318 #define MMC_RSP_CRC     (1 << 2)                /* expect valid crc */
 319 #define MMC_RSP_BUSY    (1 << 3)                /* card may send busy */
 320 #define MMC_RSP_OPCODE  (1 << 4)                /* response contains opcode */
 321
 322 #define MMC_RSP_NONE    (0)
 323 #define MMC_RSP_R1      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 324 #define MMC_RSP_R1b     (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
 325                         MMC_RSP_BUSY)
 326 #define MMC_RSP_R2      (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
 327 #define MMC_RSP_R3      (MMC_RSP_PRESENT)
 328 #define MMC_RSP_R4      (MMC_RSP_PRESENT)
 329 #define MMC_RSP_R5      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 330 #define MMC_RSP_R6      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 331 #define MMC_RSP_R7      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 332
 333 #define MMCPART_NOAVAILABLE     (0xff)
 334 #define PART_ACCESS_MASK        (0x7)
 335 #define PART_SUPPORT            (0x1)
 336 #define ENHNCD_SUPPORT          (0x2)
 337 #define PART_ENH_ATTRIB         (0x1f)
 338
 339 #define MMC_QUIRK_RETRY_SEND_CID        BIT(0)
 340 #define MMC_QUIRK_RETRY_SET_BLOCKLEN    BIT(1)
 341 #define MMC_QUIRK_RETRY_APP_CMD BIT(2)
 342
 343 enum mmc_voltage {
 344         MMC_SIGNAL_VOLTAGE_000 = 0,
 345         MMC_SIGNAL_VOLTAGE_120 = 1,
 346         MMC_SIGNAL_VOLTAGE_180 = 2,
 347         MMC_SIGNAL_VOLTAGE_330 = 4,
 348 };
 349
 350 #define MMC_ALL_SIGNAL_VOLTAGE (MMC_SIGNAL_VOLTAGE_120 |\
 351                                 MMC_SIGNAL_VOLTAGE_180 |\
 352                                 MMC_SIGNAL_VOLTAGE_330)
 353
 354 /* Maximum block size for MMC */
 355 #define MMC_MAX_BLOCK_LEN       512
 356
 357 /* The number of MMC physical partitions.  These consist of:
 358  * boot partitions (2), general purpose partitions (4) in MMC v4.4.
 359  */
 360 #define MMC_NUM_BOOT_PARTITION  2
 361 #define MMC_PART_RPMB           3       /* RPMB partition number */
 362
 363 /* Driver model support */
 364
 365 /**
 366  * struct mmc_uclass_priv - Holds information about a device used by the uclass
 367  */
 368 struct mmc_uclass_priv {
 369         struct mmc *mmc;
 370 };
 371
 372 /**
 373  * mmc_get_mmc_dev() - get the MMC struct pointer for a device
 374  *
 375  * Provided that the device is already probed and ready for use, this value
 376  * will be available.
 377  *
 378  * @dev:        Device
 379  * @return associated mmc struct pointer if available, else NULL
 380  */
 381 struct mmc *mmc_get_mmc_dev(const struct udevice *dev);
 382
 383 /* End of driver model support */
 384
 385 struct mmc_cid {
 386         unsigned long psn;
 387         unsigned short oid;
 388         unsigned char mid;
 389         unsigned char prv;
 390         unsigned char mdt;
 391         char pnm[7];
 392 };
 393
 394 struct mmc_cmd {
 395         ushort cmdidx;
 396         uint resp_type;
 397         uint cmdarg;
 398         uint response[4];
 399 };
 400
 401 struct mmc_data {
 402         union {
 403                 char *dest;
 404                 const char *src; /* src buffers don't get written to */
 405         };
 406         uint flags;
 407         uint blocks;
 408         uint blocksize;
 409 };
 410
 411 /* forward decl. */
 412 struct mmc;
 413
 414 #if CONFIG_IS_ENABLED(DM_MMC)
 415 struct dm_mmc_ops {
 416         /**
 417          * deferred_probe() - Some configurations that need to be deferred
 418          * to just before enumerating the device
 419          *
 420          * @dev:        Device to init
 421          * @return 0 if Ok, -ve if error
 422          */
 423         int (*deferred_probe)(struct udevice *dev);
 424         /**
 425          * send_cmd() - Send a command to the MMC device
 426          *
 427          * @dev:        Device to receive the command
 428          * @cmd:        Command to send
 429          * @data:       Additional data to send/receive
 430          * @return 0 if OK, -ve on error
 431          */
 432         int (*send_cmd)(struct udevice *dev, struct mmc_cmd *cmd,
 433                         struct mmc_data *data);
 434
 435         /**
 436          * set_ios() - Set the I/O speed/width for an MMC device
 437          *
 438          * @dev:        Device to update
 439          * @return 0 if OK, -ve on error
 440          */
 441         int (*set_ios)(struct udevice *dev);
 442
 443         /**
 444          * get_cd() - See whether a card is present
 445          *
 446          * @dev:        Device to check
 447          * @return 0 if not present, 1 if present, -ve on error
 448          */
 449         int (*get_cd)(struct udevice *dev);
 450
 451         /**
 452          * get_wp() - See whether a card has write-protect enabled
 453          *
 454          * @dev:        Device to check
 455          * @return 0 if write-enabled, 1 if write-protected, -ve on error
 456          */
 457         int (*get_wp)(struct udevice *dev);
 458
 459 #ifdef MMC_SUPPORTS_TUNING
 460         /**
 461          * execute_tuning() - Start the tuning process
 462          *
 463          * @dev:        Device to start the tuning
 464          * @opcode:     Command opcode to send
 465          * @return 0 if OK, -ve on error
 466          */
 467         int (*execute_tuning)(struct udevice *dev, uint opcode);
 468 #endif
 469
 470         /**
 471          * wait_dat0() - wait until dat0 is in the target state
 472          *              (CLK must be running during the wait)
 473          *
 474          * @dev:        Device to check
 475          * @state:      target state
 476          * @timeout_us: timeout in us
 477          * @return 0 if dat0 is in the target state, -ve on error
 478          */
 479         int (*wait_dat0)(struct udevice *dev, int state, int timeout_us);
 480
 481 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
 482         /* set_enhanced_strobe() - set HS400 enhanced strobe */
 483         int (*set_enhanced_strobe)(struct udevice *dev);
 484 #endif
 485
 486         /**
 487          * host_power_cycle - host specific tasks in power cycle sequence
 488          *                    Called between mmc_power_off() and
 489          *                    mmc_power_on()
 490          *
 491          * @dev:        Device to check
 492          * @return 0 if not present, 1 if present, -ve on error
 493          */
 494         int (*host_power_cycle)(struct udevice *dev);
 495
 496         /**
 497          * get_b_max - get maximum length of single transfer
 498          *             Called before reading blocks from the card,
 499          *             useful for system which have e.g. DMA limits
 500          *             on various memory ranges.
 501          *
 502          * @dev:        Device to check
 503          * @dst:        Destination buffer in memory
 504          * @blkcnt:     Total number of blocks in this transfer
 505          * @return maximum number of blocks for this transfer
 506          */
 507         int (*get_b_max)(struct udevice *dev, void *dst, lbaint_t blkcnt);
 508 };
 509
 510 #define mmc_get_ops(dev)        ((struct dm_mmc_ops *)(dev)->driver->ops)
 511
 512 int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 513                     struct mmc_data *data);
 514 int dm_mmc_set_ios(struct udevice *dev);
 515 int dm_mmc_get_cd(struct udevice *dev);
 516 int dm_mmc_get_wp(struct udevice *dev);
 517 int dm_mmc_execute_tuning(struct udevice *dev, uint opcode);
 518 int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout_us);
 519 int dm_mmc_host_power_cycle(struct udevice *dev);
 520 int dm_mmc_deferred_probe(struct udevice *dev);
 521 int dm_mmc_get_b_max(struct udevice *dev, void *dst, lbaint_t blkcnt);
 522
 523 /* Transition functions for compatibility */
 524 int mmc_set_ios(struct mmc *mmc);
 525 int mmc_getcd(struct mmc *mmc);
 526 int mmc_getwp(struct mmc *mmc);
 527 int mmc_execute_tuning(struct mmc *mmc, uint opcode);
 528 int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us);
 529 int mmc_set_enhanced_strobe(struct mmc *mmc);
 530 int mmc_host_power_cycle(struct mmc *mmc);
 531 int mmc_deferred_probe(struct mmc *mmc);
 532 int mmc_get_b_max(struct mmc *mmc, void *dst, lbaint_t blkcnt);
 533
 534 #else
 535 struct mmc_ops {
 536         int (*send_cmd)(struct mmc *mmc,
 537                         struct mmc_cmd *cmd, struct mmc_data *data);
 538         int (*set_ios)(struct mmc *mmc);
 539         int (*init)(struct mmc *mmc);
 540         int (*getcd)(struct mmc *mmc);
 541         int (*getwp)(struct mmc *mmc);
 542         int (*host_power_cycle)(struct mmc *mmc);
 543         int (*get_b_max)(struct mmc *mmc, void *dst, lbaint_t blkcnt);
 544 };
 545 #endif
 546
 547 struct mmc_config {
 548         const char *name;
 549 #if !CONFIG_IS_ENABLED(DM_MMC)
 550         const struct mmc_ops *ops;
 551 #endif
 552         uint host_caps;
 553         uint voltages;
 554         uint f_min;
 555         uint f_max;
 556         uint b_max;
 557         unsigned char part_type;
 558 };
 559
 560 struct sd_ssr {
 561         unsigned int au;                /* In sectors */
 562         unsigned int erase_timeout;     /* In milliseconds */
 563         unsigned int erase_offset;      /* In milliseconds */
 564 };
 565
 566 enum bus_mode {
 567         MMC_LEGACY,
 568         MMC_HS,
 569         SD_HS,
 570         MMC_HS_52,
 571         MMC_DDR_52,
 572         UHS_SDR12,
 573         UHS_SDR25,
 574         UHS_SDR50,
 575         UHS_DDR50,
 576         UHS_SDR104,
 577         MMC_HS_200,
 578         MMC_HS_400,
 579         MMC_HS_400_ES,
 580         MMC_MODES_END
 581 };
 582
 583 const char *mmc_mode_name(enum bus_mode mode);
 584 void mmc_dump_capabilities(const char *text, uint caps);
 585
 586 static inline bool mmc_is_mode_ddr(enum bus_mode mode)
 587 {
 588         if (mode == MMC_DDR_52)
 589                 return true;
 590 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 591         else if (mode == UHS_DDR50)
 592                 return true;
 593 #endif
 594 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 595         else if (mode == MMC_HS_400)
 596                 return true;
 597 #endif
 598 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
 599         else if (mode == MMC_HS_400_ES)
 600                 return true;
 601 #endif
 602         else
 603                 return false;
 604 }
 605
 606 #define UHS_CAPS (MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) | \
 607                   MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_SDR104) | \
 608                   MMC_CAP(UHS_DDR50))
 609
 610 static inline bool supports_uhs(uint caps)
 611 {
 612 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 613         return (caps & UHS_CAPS) ? true : false;
 614 #else
 615         return false;
 616 #endif
 617 }
 618
 619 /*
 620  * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device
 621  * with mmc_get_mmc_dev().
 622  *
 623  * TODO struct mmc should be in mmc_private but it's hard to fix right now
 624  */
 625 struct mmc {
 626 #if !CONFIG_IS_ENABLED(BLK)
 627         struct list_head link;
 628 #endif
 629         const struct mmc_config *cfg;   /* provided configuration */
 630         uint version;
 631         void *priv;
 632         uint has_init;
 633         int high_capacity;
 634         bool clk_disable; /* true if the clock can be turned off */
 635         uint bus_width;
 636         uint clock;
 637         uint saved_clock;
 638         enum mmc_voltage signal_voltage;
 639         uint card_caps;
 640         uint host_caps;
 641         uint ocr;
 642         uint dsr;
 643         uint dsr_imp;
 644         uint scr[2];
 645         uint csd[4];
 646         uint cid[4];
 647         ushort rca;
 648         u8 part_support;
 649         u8 part_attr;
 650         u8 wr_rel_set;
 651         u8 part_config;
 652         u8 gen_cmd6_time;       /* units: 10 ms */
 653         u8 part_switch_time;    /* units: 10 ms */
 654         uint tran_speed;
 655         uint legacy_speed; /* speed for the legacy mode provided by the card */
 656         uint read_bl_len;
 657 #if CONFIG_IS_ENABLED(MMC_WRITE)
 658         uint write_bl_len;
 659         uint erase_grp_size;    /* in 512-byte sectors */
 660 #endif
 661 #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
 662         uint hc_wp_grp_size;    /* in 512-byte sectors */
 663 #endif
 664 #if CONFIG_IS_ENABLED(MMC_WRITE)
 665         struct sd_ssr   ssr;    /* SD status register */
 666 #endif
 667         u64 capacity;
 668         u64 capacity_user;
 669         u64 capacity_boot;
 670         u64 capacity_rpmb;
 671         u64 capacity_gp[4];
 672 #ifndef CONFIG_SPL_BUILD
 673         u64 enh_user_start;
 674         u64 enh_user_size;
 675 #endif
 676 #if !CONFIG_IS_ENABLED(BLK)
 677         struct blk_desc block_dev;
 678 #endif
 679         char op_cond_pending;   /* 1 if we are waiting on an op_cond command */
 680         char init_in_progress;  /* 1 if we have done mmc_start_init() */
 681         char preinit;           /* start init as early as possible */
 682         int ddr_mode;
 683 #if CONFIG_IS_ENABLED(DM_MMC)
 684         struct udevice *dev;    /* Device for this MMC controller */
 685 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 686         struct udevice *vmmc_supply;    /* Main voltage regulator (Vcc)*/
 687         struct udevice *vqmmc_supply;   /* IO voltage regulator (Vccq)*/
 688 #endif
 689 #endif
 690         u8 *ext_csd;
 691         u32 cardtype;           /* cardtype read from the MMC */
 692         enum mmc_voltage current_voltage;
 693         enum bus_mode selected_mode; /* mode currently used */
 694         enum bus_mode best_mode; /* best mode is the supported mode with the
 695                                   * highest bandwidth. It may not always be the
 696                                   * operating mode due to limitations when
 697                                   * accessing the boot partitions
 698                                   */
 699         u32 quirks;
 700 };
 701
 702 struct mmc_hwpart_conf {
 703         struct {
 704                 uint enh_start; /* in 512-byte sectors */
 705                 uint enh_size;  /* in 512-byte sectors, if 0 no enh area */
 706                 unsigned wr_rel_change : 1;
 707                 unsigned wr_rel_set : 1;
 708         } user;
 709         struct {
 710                 uint size;      /* in 512-byte sectors */
 711                 unsigned enhanced : 1;
 712                 unsigned wr_rel_change : 1;
 713                 unsigned wr_rel_set : 1;
 714         } gp_part[4];
 715 };
 716
 717 enum mmc_hwpart_conf_mode {
 718         MMC_HWPART_CONF_CHECK,
 719         MMC_HWPART_CONF_SET,
 720         MMC_HWPART_CONF_COMPLETE,
 721 };
 722
 723 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
 724
 725 /**
 726  * mmc_bind() - Set up a new MMC device ready for probing
 727  *
 728  * A child block device is bound with the IF_TYPE_MMC interface type. This
 729  * allows the device to be used with CONFIG_BLK
 730  *
 731  * @dev:        MMC device to set up
 732  * @mmc:        MMC struct
 733  * @cfg:        MMC configuration
 734  * @return 0 if OK, -ve on error
 735  */
 736 int mmc_bind(struct udevice *dev, struct mmc *mmc,
 737              const struct mmc_config *cfg);
 738 void mmc_destroy(struct mmc *mmc);
 739
 740 /**
 741  * mmc_unbind() - Unbind a MMC device's child block device
 742  *
 743  * @dev:        MMC device
 744  * @return 0 if OK, -ve on error
 745  */
 746 int mmc_unbind(struct udevice *dev);
 747 int mmc_initialize(struct bd_info *bis);
 748 int mmc_init_device(int num);
 749 int mmc_init(struct mmc *mmc);
 750 int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error);
 751
 752 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
 753     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 754     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 755 int mmc_deinit(struct mmc *mmc);
 756 #endif
 757
 758 /**
 759  * mmc_of_parse() - Parse the device tree to get the capabilities of the host
 760  *
 761  * @dev:        MMC device
 762  * @cfg:        MMC configuration
 763  * @return 0 if OK, -ve on error
 764  */
 765 int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg);
 766
 767 int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
 768
 769 /**
 770  * mmc_voltage_to_mv() - Convert a mmc_voltage in mV
 771  *
 772  * @voltage:    The mmc_voltage to convert
 773  * @return the value in mV if OK, -EINVAL on error (invalid mmc_voltage value)
 774  */
 775 int mmc_voltage_to_mv(enum mmc_voltage voltage);
 776
 777 /**
 778  * mmc_set_clock() - change the bus clock
 779  * @mmc:        MMC struct
 780  * @clock:      bus frequency in Hz
 781  * @disable:    flag indicating if the clock must on or off
 782  * @return 0 if OK, -ve on error
 783  */
 784 int mmc_set_clock(struct mmc *mmc, uint clock, bool disable);
 785
 786 #define MMC_CLK_ENABLE          false
 787 #define MMC_CLK_DISABLE         true
 788
 789 struct mmc *find_mmc_device(int dev_num);
 790 int mmc_set_dev(int dev_num);
 791 void print_mmc_devices(char separator);
 792
 793 /**
 794  * get_mmc_num() - get the total MMC device number
 795  *
 796  * @return 0 if there is no MMC device, else the number of devices
 797  */
 798 int get_mmc_num(void);
 799 int mmc_switch_part(struct mmc *mmc, unsigned int part_num);
 800 int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
 801                       enum mmc_hwpart_conf_mode mode);
 802
 803 #if !CONFIG_IS_ENABLED(DM_MMC)
 804 int mmc_getcd(struct mmc *mmc);
 805 int board_mmc_getcd(struct mmc *mmc);
 806 int mmc_getwp(struct mmc *mmc);
 807 int board_mmc_getwp(struct mmc *mmc);
 808 #endif
 809
 810 int mmc_set_dsr(struct mmc *mmc, u16 val);
 811 /* Function to change the size of boot partition and rpmb partitions */
 812 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
 813                                         unsigned long rpmbsize);
 814 /* Function to modify the PARTITION_CONFIG field of EXT_CSD */
 815 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
 816 /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
 817 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
 818 /* Function to modify the RST_n_FUNCTION field of EXT_CSD */
 819 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
 820 /* Functions to read / write the RPMB partition */
 821 int mmc_rpmb_set_key(struct mmc *mmc, void *key);
 822 int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
 823 int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
 824                   unsigned short cnt, unsigned char *key);
 825 int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
 826                    unsigned short cnt, unsigned char *key);
 827
 828 /**
 829  * mmc_rpmb_route_frames() - route RPMB data frames
 830  * @mmc         Pointer to a MMC device struct
 831  * @req         Request data frames
 832  * @reqlen      Length of data frames in bytes
 833  * @rsp         Supplied buffer for response data frames
 834  * @rsplen      Length of supplied buffer for response data frames
 835  *
 836  * The RPMB data frames are routed to/from some external entity, for
 837  * example a Trusted Exectuion Environment in an arm TrustZone protected
 838  * secure world. It's expected that it's the external entity who is in
 839  * control of the RPMB key.
 840  *
 841  * Returns 0 on success, < 0 on error.
 842  */
 843 int mmc_rpmb_route_frames(struct mmc *mmc, void *req, unsigned long reqlen,
 844                           void *rsp, unsigned long rsplen);
 845
 846 #ifdef CONFIG_CMD_BKOPS_ENABLE
 847 int mmc_set_bkops_enable(struct mmc *mmc);
 848 #endif
 849
 850 /**
 851  * Start device initialization and return immediately; it does not block on
 852  * polling OCR (operation condition register) status. Useful for checking
 853  * the presence of SD/eMMC when no card detect logic is available.
 854  *
 855  * @param mmc   Pointer to a MMC device struct
 856  * @return 0 on success, <0 on error.
 857  */
 858 int mmc_get_op_cond(struct mmc *mmc);
 859
 860 /**
 861  * Start device initialization and return immediately; it does not block on
 862  * polling OCR (operation condition register) status.  Then you should call
 863  * mmc_init, which would block on polling OCR status and complete the device
 864  * initializatin.
 865  *
 866  * @param mmc   Pointer to a MMC device struct
 867  * @return 0 on success, <0 on error.
 868  */
 869 int mmc_start_init(struct mmc *mmc);
 870
 871 /**
 872  * Set preinit flag of mmc device.
 873  *
 874  * This will cause the device to be pre-inited during mmc_initialize(),
 875  * which may save boot time if the device is not accessed until later.
 876  * Some eMMC devices take 200-300ms to init, but unfortunately they
 877  * must be sent a series of commands to even get them to start preparing
 878  * for operation.
 879  *
 880  * @param mmc           Pointer to a MMC device struct
 881  * @param preinit       preinit flag value
 882  */
 883 void mmc_set_preinit(struct mmc *mmc, int preinit);
 884
 885 #ifdef CONFIG_MMC_SPI
 886 #define mmc_host_is_spi(mmc)    ((mmc)->cfg->host_caps & MMC_MODE_SPI)
 887 #else
 888 #define mmc_host_is_spi(mmc)    0
 889 #endif
 890
 891 void board_mmc_power_init(void);
 892 int board_mmc_init(struct bd_info *bis);
 893 int cpu_mmc_init(struct bd_info *bis);
 894 int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
 895 # ifdef CONFIG_SYS_MMC_ENV_PART
 896 extern uint mmc_get_env_part(struct mmc *mmc);
 897 # endif
 898 int mmc_get_env_dev(void);
 899
 900 /* Minimum partition switch timeout in units of 10-milliseconds */
 901 #define MMC_MIN_PART_SWITCH_TIME        30 /* 300 ms */
 902
 903 /* Set block count limit because of 16 bit register limit on some hardware*/
 904 #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
 905 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
 906 #endif
 907
 908 /**
 909  * mmc_get_blk_desc() - Get the block descriptor for an MMC device
 910  *
 911  * @mmc:        MMC device
 912  * @return block device if found, else NULL
 913  */
 914 struct blk_desc *mmc_get_blk_desc(struct mmc *mmc);
 915
 916 /**
 917  * mmc_send_ext_csd() - read the extended CSD register
 918  *
 919  * @mmc:        MMC device
 920  * @ext_csd     a cache aligned buffer of length MMC_MAX_BLOCK_LEN allocated by
 921  *              the caller, e.g. using
 922  *              ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN)
 923  * Return:      0 for success
 924  */
 925 int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd);
 926
 927 /**
 928  * mmc_boot_wp() - power on write protect boot partitions
 929  *
 930  * The boot partitions are write protected until the next power cycle.
 931  *
 932  * Return:      0 for success
 933  */
 934 int mmc_boot_wp(struct mmc *mmc);
 935
 936 static inline enum dma_data_direction mmc_get_dma_dir(struct mmc_data *data)
 937 {
 938         return data->flags & MMC_DATA_WRITE ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
 939 }
 940
 941 #endif /* _MMC_H_ */