include/mmc.h

   1 /*
   2  * Copyright 2008,2010 Freescale Semiconductor, Inc
   3  * Andy Fleming
   4  *
   5  * Based (loosely) on the Linux code
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef _MMC_H_
  11 #define _MMC_H_
  12
  13 #include <linux/list.h>
  14 #include <linux/compiler.h>
  15 #include <part.h>
  16
  17 #define SD_VERSION_SD   0x20000
  18 #define SD_VERSION_3    (SD_VERSION_SD | 0x300)
  19 #define SD_VERSION_2    (SD_VERSION_SD | 0x200)
  20 #define SD_VERSION_1_0  (SD_VERSION_SD | 0x100)
  21 #define SD_VERSION_1_10 (SD_VERSION_SD | 0x10a)
  22 #define MMC_VERSION_MMC         0x10000
  23 #define MMC_VERSION_UNKNOWN     (MMC_VERSION_MMC)
  24 #define MMC_VERSION_1_2         (MMC_VERSION_MMC | 0x102)
  25 #define MMC_VERSION_1_4         (MMC_VERSION_MMC | 0x104)
  26 #define MMC_VERSION_2_2         (MMC_VERSION_MMC | 0x202)
  27 #define MMC_VERSION_3           (MMC_VERSION_MMC | 0x300)
  28 #define MMC_VERSION_4           (MMC_VERSION_MMC | 0x400)
  29 #define MMC_VERSION_4_1         (MMC_VERSION_MMC | 0x401)
  30 #define MMC_VERSION_4_2         (MMC_VERSION_MMC | 0x402)
  31 #define MMC_VERSION_4_3         (MMC_VERSION_MMC | 0x403)
  32 #define MMC_VERSION_4_41        (MMC_VERSION_MMC | 0x429)
  33 #define MMC_VERSION_4_5         (MMC_VERSION_MMC | 0x405)
  34 #define MMC_VERSION_5_0         (MMC_VERSION_MMC | 0x500)
  35
  36 #define MMC_MODE_HS             (1 << 0)
  37 #define MMC_MODE_HS_52MHz       (1 << 1)
  38 #define MMC_MODE_4BIT           (1 << 2)
  39 #define MMC_MODE_8BIT           (1 << 3)
  40 #define MMC_MODE_SPI            (1 << 4)
  41 #define MMC_MODE_HC             (1 << 5)
  42 #define MMC_MODE_DDR_52MHz      (1 << 6)
  43
  44 #define SD_DATA_4BIT    0x00040000
  45
  46 #define IS_SD(x) (x->version & SD_VERSION_SD)
  47
  48 #define MMC_DATA_READ           1
  49 #define MMC_DATA_WRITE          2
  50
  51 #define NO_CARD_ERR             -16 /* No SD/MMC card inserted */
  52 #define UNUSABLE_ERR            -17 /* Unusable Card */
  53 #define COMM_ERR                -18 /* Communications Error */
  54 #define TIMEOUT                 -19
  55 #define IN_PROGRESS             -20 /* operation is in progress */
  56 #define SWITCH_ERR              -21 /* Card reports failure to switch mode */
  57
  58 #define MMC_CMD_GO_IDLE_STATE           0
  59 #define MMC_CMD_SEND_OP_COND            1
  60 #define MMC_CMD_ALL_SEND_CID            2
  61 #define MMC_CMD_SET_RELATIVE_ADDR       3
  62 #define MMC_CMD_SET_DSR                 4
  63 #define MMC_CMD_SWITCH                  6
  64 #define MMC_CMD_SELECT_CARD             7
  65 #define MMC_CMD_SEND_EXT_CSD            8
  66 #define MMC_CMD_SEND_CSD                9
  67 #define MMC_CMD_SEND_CID                10
  68 #define MMC_CMD_STOP_TRANSMISSION       12
  69 #define MMC_CMD_SEND_STATUS             13
  70 #define MMC_CMD_SET_BLOCKLEN            16
  71 #define MMC_CMD_READ_SINGLE_BLOCK       17
  72 #define MMC_CMD_READ_MULTIPLE_BLOCK     18
  73 #define MMC_CMD_SET_BLOCK_COUNT         23
  74 #define MMC_CMD_WRITE_SINGLE_BLOCK      24
  75 #define MMC_CMD_WRITE_MULTIPLE_BLOCK    25
  76 #define MMC_CMD_ERASE_GROUP_START       35
  77 #define MMC_CMD_ERASE_GROUP_END         36
  78 #define MMC_CMD_ERASE                   38
  79 #define MMC_CMD_APP_CMD                 55
  80 #define MMC_CMD_SPI_READ_OCR            58
  81 #define MMC_CMD_SPI_CRC_ON_OFF          59
  82 #define MMC_CMD_RES_MAN                 62
  83
  84 #define MMC_CMD62_ARG1                  0xefac62ec
  85 #define MMC_CMD62_ARG2                  0xcbaea7
  86
  87
  88 #define SD_CMD_SEND_RELATIVE_ADDR       3
  89 #define SD_CMD_SWITCH_FUNC              6
  90 #define SD_CMD_SEND_IF_COND             8
  91
  92 #define SD_CMD_APP_SET_BUS_WIDTH        6
  93 #define SD_CMD_ERASE_WR_BLK_START       32
  94 #define SD_CMD_ERASE_WR_BLK_END         33
  95 #define SD_CMD_APP_SEND_OP_COND         41
  96 #define SD_CMD_APP_SEND_SCR             51
  97
  98 /* SCR definitions in different words */
  99 #define SD_HIGHSPEED_BUSY       0x00020000
 100 #define SD_HIGHSPEED_SUPPORTED  0x00020000
 101
 102 #define OCR_BUSY                0x80000000
 103 #define OCR_HCS                 0x40000000
 104 #define OCR_VOLTAGE_MASK        0x007FFF80
 105 #define OCR_ACCESS_MODE         0x60000000
 106
 107 #define SECURE_ERASE            0x80000000
 108
 109 #define MMC_STATUS_MASK         (~0x0206BF7F)
 110 #define MMC_STATUS_SWITCH_ERROR (1 << 7)
 111 #define MMC_STATUS_RDY_FOR_DATA (1 << 8)
 112 #define MMC_STATUS_CURR_STATE   (0xf << 9)
 113 #define MMC_STATUS_ERROR        (1 << 19)
 114
 115 #define MMC_STATE_PRG           (7 << 9)
 116
 117 #define MMC_VDD_165_195         0x00000080      /* VDD voltage 1.65 - 1.95 */
 118 #define MMC_VDD_20_21           0x00000100      /* VDD voltage 2.0 ~ 2.1 */
 119 #define MMC_VDD_21_22           0x00000200      /* VDD voltage 2.1 ~ 2.2 */
 120 #define MMC_VDD_22_23           0x00000400      /* VDD voltage 2.2 ~ 2.3 */
 121 #define MMC_VDD_23_24           0x00000800      /* VDD voltage 2.3 ~ 2.4 */
 122 #define MMC_VDD_24_25           0x00001000      /* VDD voltage 2.4 ~ 2.5 */
 123 #define MMC_VDD_25_26           0x00002000      /* VDD voltage 2.5 ~ 2.6 */
 124 #define MMC_VDD_26_27           0x00004000      /* VDD voltage 2.6 ~ 2.7 */
 125 #define MMC_VDD_27_28           0x00008000      /* VDD voltage 2.7 ~ 2.8 */
 126 #define MMC_VDD_28_29           0x00010000      /* VDD voltage 2.8 ~ 2.9 */
 127 #define MMC_VDD_29_30           0x00020000      /* VDD voltage 2.9 ~ 3.0 */
 128 #define MMC_VDD_30_31           0x00040000      /* VDD voltage 3.0 ~ 3.1 */
 129 #define MMC_VDD_31_32           0x00080000      /* VDD voltage 3.1 ~ 3.2 */
 130 #define MMC_VDD_32_33           0x00100000      /* VDD voltage 3.2 ~ 3.3 */
 131 #define MMC_VDD_33_34           0x00200000      /* VDD voltage 3.3 ~ 3.4 */
 132 #define MMC_VDD_34_35           0x00400000      /* VDD voltage 3.4 ~ 3.5 */
 133 #define MMC_VDD_35_36           0x00800000      /* VDD voltage 3.5 ~ 3.6 */
 134
 135 #define MMC_SWITCH_MODE_CMD_SET         0x00 /* Change the command set */
 136 #define MMC_SWITCH_MODE_SET_BITS        0x01 /* Set bits in EXT_CSD byte
 137                                                 addressed by index which are
 138                                                 1 in value field */
 139 #define MMC_SWITCH_MODE_CLEAR_BITS      0x02 /* Clear bits in EXT_CSD byte
 140                                                 addressed by index, which are
 141                                                 1 in value field */
 142 #define MMC_SWITCH_MODE_WRITE_BYTE      0x03 /* Set target byte to value */
 143
 144 #define SD_SWITCH_CHECK         0
 145 #define SD_SWITCH_SWITCH        1
 146
 147 /*
 148  * EXT_CSD fields
 149  */
 150 #define EXT_CSD_GP_SIZE_MULT            143     /* R/W */
 151 #define EXT_CSD_PARTITION_SETTING       155     /* R/W */
 152 #define EXT_CSD_PARTITIONS_ATTRIBUTE    156     /* R/W */
 153 #define EXT_CSD_PARTITIONING_SUPPORT    160     /* RO */
 154 #define EXT_CSD_RST_N_FUNCTION          162     /* R/W */
 155 #define EXT_CSD_RPMB_MULT               168     /* RO */
 156 #define EXT_CSD_ERASE_GROUP_DEF         175     /* R/W */
 157 #define EXT_CSD_BOOT_BUS_WIDTH          177
 158 #define EXT_CSD_PART_CONF               179     /* R/W */
 159 #define EXT_CSD_BUS_WIDTH               183     /* R/W */
 160 #define EXT_CSD_HS_TIMING               185     /* R/W */
 161 #define EXT_CSD_REV                     192     /* RO */
 162 #define EXT_CSD_CARD_TYPE               196     /* RO */
 163 #define EXT_CSD_SEC_CNT                 212     /* RO, 4 bytes */
 164 #define EXT_CSD_HC_WP_GRP_SIZE          221     /* RO */
 165 #define EXT_CSD_HC_ERASE_GRP_SIZE       224     /* RO */
 166 #define EXT_CSD_BOOT_MULT               226     /* RO */
 167
 168 /*
 169  * EXT_CSD field definitions
 170  */
 171
 172 #define EXT_CSD_CMD_SET_NORMAL          (1 << 0)
 173 #define EXT_CSD_CMD_SET_SECURE          (1 << 1)
 174 #define EXT_CSD_CMD_SET_CPSECURE        (1 << 2)
 175
 176 #define EXT_CSD_CARD_TYPE_26    (1 << 0)        /* Card can run at 26MHz */
 177 #define EXT_CSD_CARD_TYPE_52    (1 << 1)        /* Card can run at 52MHz */
 178 #define EXT_CSD_CARD_TYPE_DDR_1_8V      (1 << 2)
 179 #define EXT_CSD_CARD_TYPE_DDR_1_2V      (1 << 3)
 180 #define EXT_CSD_CARD_TYPE_DDR_52        (EXT_CSD_CARD_TYPE_DDR_1_8V \
 181                                         | EXT_CSD_CARD_TYPE_DDR_1_2V)
 182
 183 #define EXT_CSD_BUS_WIDTH_1     0       /* Card is in 1 bit mode */
 184 #define EXT_CSD_BUS_WIDTH_4     1       /* Card is in 4 bit mode */
 185 #define EXT_CSD_BUS_WIDTH_8     2       /* Card is in 8 bit mode */
 186 #define EXT_CSD_DDR_BUS_WIDTH_4 5       /* Card is in 4 bit DDR mode */
 187 #define EXT_CSD_DDR_BUS_WIDTH_8 6       /* Card is in 8 bit DDR mode */
 188
 189 #define EXT_CSD_BOOT_ACK_ENABLE                 (1 << 6)
 190 #define EXT_CSD_BOOT_PARTITION_ENABLE           (1 << 3)
 191 #define EXT_CSD_PARTITION_ACCESS_ENABLE         (1 << 0)
 192 #define EXT_CSD_PARTITION_ACCESS_DISABLE        (0 << 0)
 193
 194 #define EXT_CSD_BOOT_ACK(x)             (x << 6)
 195 #define EXT_CSD_BOOT_PART_NUM(x)        (x << 3)
 196 #define EXT_CSD_PARTITION_ACCESS(x)     (x << 0)
 197
 198 #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x)  (x << 3)
 199 #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
 200 #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
 201
 202 #define EXT_CSD_PARTITION_SETTING_COMPLETED     (1 << 0)
 203
 204 #define R1_ILLEGAL_COMMAND              (1 << 22)
 205 #define R1_APP_CMD                      (1 << 5)
 206
 207 #define MMC_RSP_PRESENT (1 << 0)
 208 #define MMC_RSP_136     (1 << 1)                /* 136 bit response */
 209 #define MMC_RSP_CRC     (1 << 2)                /* expect valid crc */
 210 #define MMC_RSP_BUSY    (1 << 3)                /* card may send busy */
 211 #define MMC_RSP_OPCODE  (1 << 4)                /* response contains opcode */
 212
 213 #define MMC_RSP_NONE    (0)
 214 #define MMC_RSP_R1      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 215 #define MMC_RSP_R1b     (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
 216                         MMC_RSP_BUSY)
 217 #define MMC_RSP_R2      (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
 218 #define MMC_RSP_R3      (MMC_RSP_PRESENT)
 219 #define MMC_RSP_R4      (MMC_RSP_PRESENT)
 220 #define MMC_RSP_R5      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 221 #define MMC_RSP_R6      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 222 #define MMC_RSP_R7      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 223
 224 #define MMCPART_NOAVAILABLE     (0xff)
 225 #define PART_ACCESS_MASK        (0x7)
 226 #define PART_SUPPORT            (0x1)
 227 #define PART_ENH_ATTRIB         (0x1f)
 228
 229 /* Maximum block size for MMC */
 230 #define MMC_MAX_BLOCK_LEN       512
 231
 232 /* The number of MMC physical partitions.  These consist of:
 233  * boot partitions (2), general purpose partitions (4) in MMC v4.4.
 234  */
 235 #define MMC_NUM_BOOT_PARTITION  2
 236 #define MMC_PART_RPMB           3       /* RPMB partition number */
 237
 238 struct mmc_cid {
 239         unsigned long psn;
 240         unsigned short oid;
 241         unsigned char mid;
 242         unsigned char prv;
 243         unsigned char mdt;
 244         char pnm[7];
 245 };
 246
 247 struct mmc_cmd {
 248         ushort cmdidx;
 249         uint resp_type;
 250         uint cmdarg;
 251         uint response[4];
 252 };
 253
 254 struct mmc_data {
 255         union {
 256                 char *dest;
 257                 const char *src; /* src buffers don't get written to */
 258         };
 259         uint flags;
 260         uint blocks;
 261         uint blocksize;
 262 };
 263
 264 /* forward decl. */
 265 struct mmc;
 266
 267 struct mmc_ops {
 268         int (*send_cmd)(struct mmc *mmc,
 269                         struct mmc_cmd *cmd, struct mmc_data *data);
 270         void (*set_ios)(struct mmc *mmc);
 271         int (*init)(struct mmc *mmc);
 272         int (*getcd)(struct mmc *mmc);
 273         int (*getwp)(struct mmc *mmc);
 274 };
 275
 276 struct mmc_config {
 277         const char *name;
 278         const struct mmc_ops *ops;
 279         uint host_caps;
 280         uint voltages;
 281         uint f_min;
 282         uint f_max;
 283         uint b_max;
 284         unsigned char part_type;
 285 };
 286
 287 /* TODO struct mmc should be in mmc_private but it's hard to fix right now */
 288 struct mmc {
 289         struct list_head link;
 290         const struct mmc_config *cfg;   /* provided configuration */
 291         uint version;
 292         void *priv;
 293         uint has_init;
 294         int high_capacity;
 295         uint bus_width;
 296         uint clock;
 297         uint card_caps;
 298         uint ocr;
 299         uint dsr;
 300         uint dsr_imp;
 301         uint scr[2];
 302         uint csd[4];
 303         uint cid[4];
 304         ushort rca;
 305         char part_config;
 306         char part_num;
 307         uint tran_speed;
 308         uint read_bl_len;
 309         uint write_bl_len;
 310         uint erase_grp_size;
 311         u64 capacity;
 312         u64 capacity_user;
 313         u64 capacity_boot;
 314         u64 capacity_rpmb;
 315         u64 capacity_gp[4];
 316         block_dev_desc_t block_dev;
 317         char op_cond_pending;   /* 1 if we are waiting on an op_cond command */
 318         char init_in_progress;  /* 1 if we have done mmc_start_init() */
 319         char preinit;           /* start init as early as possible */
 320         uint op_cond_response;  /* the response byte from the last op_cond */
 321         int ddr_mode;
 322 };
 323
 324 int mmc_register(struct mmc *mmc);
 325 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
 326 void mmc_destroy(struct mmc *mmc);
 327 int mmc_initialize(bd_t *bis);
 328 int mmc_init(struct mmc *mmc);
 329 int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
 330 void mmc_set_clock(struct mmc *mmc, uint clock);
 331 struct mmc *find_mmc_device(int dev_num);
 332 int mmc_set_dev(int dev_num);
 333 void print_mmc_devices(char separator);
 334 int get_mmc_num(void);
 335 int mmc_switch_part(int dev_num, unsigned int part_num);
 336 int mmc_getcd(struct mmc *mmc);
 337 int board_mmc_getcd(struct mmc *mmc);
 338 int mmc_getwp(struct mmc *mmc);
 339 int board_mmc_getwp(struct mmc *mmc);
 340 int mmc_set_dsr(struct mmc *mmc, u16 val);
 341 /* Function to change the size of boot partition and rpmb partitions */
 342 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
 343                                         unsigned long rpmbsize);
 344 /* Function to modify the PARTITION_CONFIG field of EXT_CSD */
 345 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
 346 /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
 347 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
 348 /* Function to modify the RST_n_FUNCTION field of EXT_CSD */
 349 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
 350 /* Functions to read / write the RPMB partition */
 351 int mmc_rpmb_set_key(struct mmc *mmc, void *key);
 352 int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
 353 int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
 354                   unsigned short cnt, unsigned char *key);
 355 int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
 356                    unsigned short cnt, unsigned char *key);
 357 /**
 358  * Start device initialization and return immediately; it does not block on
 359  * polling OCR (operation condition register) status.  Then you should call
 360  * mmc_init, which would block on polling OCR status and complete the device
 361  * initializatin.
 362  *
 363  * @param mmc   Pointer to a MMC device struct
 364  * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error.
 365  */
 366 int mmc_start_init(struct mmc *mmc);
 367
 368 /**
 369  * Set preinit flag of mmc device.
 370  *
 371  * This will cause the device to be pre-inited during mmc_initialize(),
 372  * which may save boot time if the device is not accessed until later.
 373  * Some eMMC devices take 200-300ms to init, but unfortunately they
 374  * must be sent a series of commands to even get them to start preparing
 375  * for operation.
 376  *
 377  * @param mmc           Pointer to a MMC device struct
 378  * @param preinit       preinit flag value
 379  */
 380 void mmc_set_preinit(struct mmc *mmc, int preinit);
 381
 382 #ifdef CONFIG_GENERIC_MMC
 383 #ifdef CONFIG_MMC_SPI
 384 #define mmc_host_is_spi(mmc)    ((mmc)->cfg->host_caps & MMC_MODE_SPI)
 385 #else
 386 #define mmc_host_is_spi(mmc)    0
 387 #endif
 388 struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
 389 #else
 390 int mmc_legacy_init(int verbose);
 391 #endif
 392
 393 void board_mmc_power_init(void);
 394 int board_mmc_init(bd_t *bis);
 395 int cpu_mmc_init(bd_t *bis);
 396 int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
 397
 398 /* Set block count limit because of 16 bit register limit on some hardware*/
 399 #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
 400 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
 401 #endif
 402
 403 #endif /* _MMC_H_ */