include/mmc.h

   1 /*
   2  * Copyright 2008,2010 Freescale Semiconductor, Inc
   3  * Andy Fleming
   4  *
   5  * Based (loosely) on the Linux code
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef _MMC_H_
  11 #define _MMC_H_
  12
  13 #include <linux/list.h>
  14 #include <linux/compiler.h>
  15 #include <part.h>
  16
  17 #define SD_VERSION_SD   0x20000
  18 #define SD_VERSION_3    (SD_VERSION_SD | 0x300)
  19 #define SD_VERSION_2    (SD_VERSION_SD | 0x200)
  20 #define SD_VERSION_1_0  (SD_VERSION_SD | 0x100)
  21 #define SD_VERSION_1_10 (SD_VERSION_SD | 0x10a)
  22 #define MMC_VERSION_MMC         0x10000
  23 #define MMC_VERSION_UNKNOWN     (MMC_VERSION_MMC)
  24 #define MMC_VERSION_1_2         (MMC_VERSION_MMC | 0x102)
  25 #define MMC_VERSION_1_4         (MMC_VERSION_MMC | 0x104)
  26 #define MMC_VERSION_2_2         (MMC_VERSION_MMC | 0x202)
  27 #define MMC_VERSION_3           (MMC_VERSION_MMC | 0x300)
  28 #define MMC_VERSION_4           (MMC_VERSION_MMC | 0x400)
  29 #define MMC_VERSION_4_1         (MMC_VERSION_MMC | 0x401)
  30 #define MMC_VERSION_4_2         (MMC_VERSION_MMC | 0x402)
  31 #define MMC_VERSION_4_3         (MMC_VERSION_MMC | 0x403)
  32 #define MMC_VERSION_4_41        (MMC_VERSION_MMC | 0x429)
  33 #define MMC_VERSION_4_5         (MMC_VERSION_MMC | 0x405)
  34 #define MMC_VERSION_5_0         (MMC_VERSION_MMC | 0x500)
  35
  36 #define MMC_MODE_HS             (1 << 0)
  37 #define MMC_MODE_HS_52MHz       (1 << 1)
  38 #define MMC_MODE_4BIT           (1 << 2)
  39 #define MMC_MODE_8BIT           (1 << 3)
  40 #define MMC_MODE_SPI            (1 << 4)
  41 #define MMC_MODE_HC             (1 << 5)
  42 #define MMC_MODE_DDR_52MHz      (1 << 6)
  43
  44 #define SD_DATA_4BIT    0x00040000
  45
  46 #define IS_SD(x) (x->version & SD_VERSION_SD)
  47
  48 #define MMC_DATA_READ           1
  49 #define MMC_DATA_WRITE          2
  50
  51 #define NO_CARD_ERR             -16 /* No SD/MMC card inserted */
  52 #define UNUSABLE_ERR            -17 /* Unusable Card */
  53 #define COMM_ERR                -18 /* Communications Error */
  54 #define TIMEOUT                 -19
  55 #define IN_PROGRESS             -20 /* operation is in progress */
  56 #define SWITCH_ERR              -21 /* Card reports failure to switch mode */
  57
  58 #define MMC_CMD_GO_IDLE_STATE           0
  59 #define MMC_CMD_SEND_OP_COND            1
  60 #define MMC_CMD_ALL_SEND_CID            2
  61 #define MMC_CMD_SET_RELATIVE_ADDR       3
  62 #define MMC_CMD_SET_DSR                 4
  63 #define MMC_CMD_SWITCH                  6
  64 #define MMC_CMD_SELECT_CARD             7
  65 #define MMC_CMD_SEND_EXT_CSD            8
  66 #define MMC_CMD_SEND_CSD                9
  67 #define MMC_CMD_SEND_CID                10
  68 #define MMC_CMD_STOP_TRANSMISSION       12
  69 #define MMC_CMD_SEND_STATUS             13
  70 #define MMC_CMD_SET_BLOCKLEN            16
  71 #define MMC_CMD_READ_SINGLE_BLOCK       17
  72 #define MMC_CMD_READ_MULTIPLE_BLOCK     18
  73 #define MMC_CMD_SET_BLOCK_COUNT         23
  74 #define MMC_CMD_WRITE_SINGLE_BLOCK      24
  75 #define MMC_CMD_WRITE_MULTIPLE_BLOCK    25
  76 #define MMC_CMD_ERASE_GROUP_START       35
  77 #define MMC_CMD_ERASE_GROUP_END         36
  78 #define MMC_CMD_ERASE                   38
  79 #define MMC_CMD_APP_CMD                 55
  80 #define MMC_CMD_SPI_READ_OCR            58
  81 #define MMC_CMD_SPI_CRC_ON_OFF          59
  82 #define MMC_CMD_RES_MAN                 62
  83
  84 #define MMC_CMD62_ARG1                  0xefac62ec
  85 #define MMC_CMD62_ARG2                  0xcbaea7
  86
  87
  88 #define SD_CMD_SEND_RELATIVE_ADDR       3
  89 #define SD_CMD_SWITCH_FUNC              6
  90 #define SD_CMD_SEND_IF_COND             8
  91
  92 #define SD_CMD_APP_SET_BUS_WIDTH        6
  93 #define SD_CMD_ERASE_WR_BLK_START       32
  94 #define SD_CMD_ERASE_WR_BLK_END         33
  95 #define SD_CMD_APP_SEND_OP_COND         41
  96 #define SD_CMD_APP_SEND_SCR             51
  97
  98 /* SCR definitions in different words */
  99 #define SD_HIGHSPEED_BUSY       0x00020000
 100 #define SD_HIGHSPEED_SUPPORTED  0x00020000
 101
 102 #define OCR_BUSY                0x80000000
 103 #define OCR_HCS                 0x40000000
 104 #define OCR_VOLTAGE_MASK        0x007FFF80
 105 #define OCR_ACCESS_MODE         0x60000000
 106
 107 #define SECURE_ERASE            0x80000000
 108
 109 #define MMC_STATUS_MASK         (~0x0206BF7F)
 110 #define MMC_STATUS_SWITCH_ERROR (1 << 7)
 111 #define MMC_STATUS_RDY_FOR_DATA (1 << 8)
 112 #define MMC_STATUS_CURR_STATE   (0xf << 9)
 113 #define MMC_STATUS_ERROR        (1 << 19)
 114
 115 #define MMC_STATE_PRG           (7 << 9)
 116
 117 #define MMC_VDD_165_195         0x00000080      /* VDD voltage 1.65 - 1.95 */
 118 #define MMC_VDD_20_21           0x00000100      /* VDD voltage 2.0 ~ 2.1 */
 119 #define MMC_VDD_21_22           0x00000200      /* VDD voltage 2.1 ~ 2.2 */
 120 #define MMC_VDD_22_23           0x00000400      /* VDD voltage 2.2 ~ 2.3 */
 121 #define MMC_VDD_23_24           0x00000800      /* VDD voltage 2.3 ~ 2.4 */
 122 #define MMC_VDD_24_25           0x00001000      /* VDD voltage 2.4 ~ 2.5 */
 123 #define MMC_VDD_25_26           0x00002000      /* VDD voltage 2.5 ~ 2.6 */
 124 #define MMC_VDD_26_27           0x00004000      /* VDD voltage 2.6 ~ 2.7 */
 125 #define MMC_VDD_27_28           0x00008000      /* VDD voltage 2.7 ~ 2.8 */
 126 #define MMC_VDD_28_29           0x00010000      /* VDD voltage 2.8 ~ 2.9 */
 127 #define MMC_VDD_29_30           0x00020000      /* VDD voltage 2.9 ~ 3.0 */
 128 #define MMC_VDD_30_31           0x00040000      /* VDD voltage 3.0 ~ 3.1 */
 129 #define MMC_VDD_31_32           0x00080000      /* VDD voltage 3.1 ~ 3.2 */
 130 #define MMC_VDD_32_33           0x00100000      /* VDD voltage 3.2 ~ 3.3 */
 131 #define MMC_VDD_33_34           0x00200000      /* VDD voltage 3.3 ~ 3.4 */
 132 #define MMC_VDD_34_35           0x00400000      /* VDD voltage 3.4 ~ 3.5 */
 133 #define MMC_VDD_35_36           0x00800000      /* VDD voltage 3.5 ~ 3.6 */
 134
 135 #define MMC_SWITCH_MODE_CMD_SET         0x00 /* Change the command set */
 136 #define MMC_SWITCH_MODE_SET_BITS        0x01 /* Set bits in EXT_CSD byte
 137                                                 addressed by index which are
 138                                                 1 in value field */
 139 #define MMC_SWITCH_MODE_CLEAR_BITS      0x02 /* Clear bits in EXT_CSD byte
 140                                                 addressed by index, which are
 141                                                 1 in value field */
 142 #define MMC_SWITCH_MODE_WRITE_BYTE      0x03 /* Set target byte to value */
 143
 144 #define SD_SWITCH_CHECK         0
 145 #define SD_SWITCH_SWITCH        1
 146
 147 /*
 148  * EXT_CSD fields
 149  */
 150 #define EXT_CSD_ENH_START_ADDR          136     /* R/W */
 151 #define EXT_CSD_ENH_SIZE_MULT           140     /* R/W */
 152 #define EXT_CSD_GP_SIZE_MULT            143     /* R/W */
 153 #define EXT_CSD_PARTITION_SETTING       155     /* R/W */
 154 #define EXT_CSD_PARTITIONS_ATTRIBUTE    156     /* R/W */
 155 #define EXT_CSD_MAX_ENH_SIZE_MULT       157     /* R */
 156 #define EXT_CSD_PARTITIONING_SUPPORT    160     /* RO */
 157 #define EXT_CSD_RST_N_FUNCTION          162     /* R/W */
 158 #define EXT_CSD_WR_REL_PARAM            166     /* R */
 159 #define EXT_CSD_WR_REL_SET              167     /* R/W */
 160 #define EXT_CSD_RPMB_MULT               168     /* RO */
 161 #define EXT_CSD_ERASE_GROUP_DEF         175     /* R/W */
 162 #define EXT_CSD_BOOT_BUS_WIDTH          177
 163 #define EXT_CSD_PART_CONF               179     /* R/W */
 164 #define EXT_CSD_BUS_WIDTH               183     /* R/W */
 165 #define EXT_CSD_HS_TIMING               185     /* R/W */
 166 #define EXT_CSD_REV                     192     /* RO */
 167 #define EXT_CSD_CARD_TYPE               196     /* RO */
 168 #define EXT_CSD_SEC_CNT                 212     /* RO, 4 bytes */
 169 #define EXT_CSD_HC_WP_GRP_SIZE          221     /* RO */
 170 #define EXT_CSD_HC_ERASE_GRP_SIZE       224     /* RO */
 171 #define EXT_CSD_BOOT_MULT               226     /* RO */
 172
 173 /*
 174  * EXT_CSD field definitions
 175  */
 176
 177 #define EXT_CSD_CMD_SET_NORMAL          (1 << 0)
 178 #define EXT_CSD_CMD_SET_SECURE          (1 << 1)
 179 #define EXT_CSD_CMD_SET_CPSECURE        (1 << 2)
 180
 181 #define EXT_CSD_CARD_TYPE_26    (1 << 0)        /* Card can run at 26MHz */
 182 #define EXT_CSD_CARD_TYPE_52    (1 << 1)        /* Card can run at 52MHz */
 183 #define EXT_CSD_CARD_TYPE_DDR_1_8V      (1 << 2)
 184 #define EXT_CSD_CARD_TYPE_DDR_1_2V      (1 << 3)
 185 #define EXT_CSD_CARD_TYPE_DDR_52        (EXT_CSD_CARD_TYPE_DDR_1_8V \
 186                                         | EXT_CSD_CARD_TYPE_DDR_1_2V)
 187
 188 #define EXT_CSD_BUS_WIDTH_1     0       /* Card is in 1 bit mode */
 189 #define EXT_CSD_BUS_WIDTH_4     1       /* Card is in 4 bit mode */
 190 #define EXT_CSD_BUS_WIDTH_8     2       /* Card is in 8 bit mode */
 191 #define EXT_CSD_DDR_BUS_WIDTH_4 5       /* Card is in 4 bit DDR mode */
 192 #define EXT_CSD_DDR_BUS_WIDTH_8 6       /* Card is in 8 bit DDR mode */
 193
 194 #define EXT_CSD_BOOT_ACK_ENABLE                 (1 << 6)
 195 #define EXT_CSD_BOOT_PARTITION_ENABLE           (1 << 3)
 196 #define EXT_CSD_PARTITION_ACCESS_ENABLE         (1 << 0)
 197 #define EXT_CSD_PARTITION_ACCESS_DISABLE        (0 << 0)
 198
 199 #define EXT_CSD_BOOT_ACK(x)             (x << 6)
 200 #define EXT_CSD_BOOT_PART_NUM(x)        (x << 3)
 201 #define EXT_CSD_PARTITION_ACCESS(x)     (x << 0)
 202
 203 #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x)  (x << 3)
 204 #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
 205 #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
 206
 207 #define EXT_CSD_PARTITION_SETTING_COMPLETED     (1 << 0)
 208
 209 #define EXT_CSD_ENH_USR         (1 << 0)        /* user data area is enhanced */
 210 #define EXT_CSD_ENH_GP(x)       (1 << ((x)+1))  /* GP part (x+1) is enhanced */
 211
 212 #define EXT_CSD_HS_CTRL_REL     (1 << 0)        /* host controlled WR_REL_SET */
 213
 214 #define EXT_CSD_WR_DATA_REL_USR         (1 << 0)        /* user data area WR_REL */
 215 #define EXT_CSD_WR_DATA_REL_GP(x)       (1 << ((x)+1))  /* GP part (x+1) WR_REL */
 216
 217 #define R1_ILLEGAL_COMMAND              (1 << 22)
 218 #define R1_APP_CMD                      (1 << 5)
 219
 220 #define MMC_RSP_PRESENT (1 << 0)
 221 #define MMC_RSP_136     (1 << 1)                /* 136 bit response */
 222 #define MMC_RSP_CRC     (1 << 2)                /* expect valid crc */
 223 #define MMC_RSP_BUSY    (1 << 3)                /* card may send busy */
 224 #define MMC_RSP_OPCODE  (1 << 4)                /* response contains opcode */
 225
 226 #define MMC_RSP_NONE    (0)
 227 #define MMC_RSP_R1      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 228 #define MMC_RSP_R1b     (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
 229                         MMC_RSP_BUSY)
 230 #define MMC_RSP_R2      (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
 231 #define MMC_RSP_R3      (MMC_RSP_PRESENT)
 232 #define MMC_RSP_R4      (MMC_RSP_PRESENT)
 233 #define MMC_RSP_R5      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 234 #define MMC_RSP_R6      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 235 #define MMC_RSP_R7      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 236
 237 #define MMCPART_NOAVAILABLE     (0xff)
 238 #define PART_ACCESS_MASK        (0x7)
 239 #define PART_SUPPORT            (0x1)
 240 #define ENHNCD_SUPPORT          (0x2)
 241 #define PART_ENH_ATTRIB         (0x1f)
 242
 243 /* Maximum block size for MMC */
 244 #define MMC_MAX_BLOCK_LEN       512
 245
 246 /* The number of MMC physical partitions.  These consist of:
 247  * boot partitions (2), general purpose partitions (4) in MMC v4.4.
 248  */
 249 #define MMC_NUM_BOOT_PARTITION  2
 250 #define MMC_PART_RPMB           3       /* RPMB partition number */
 251
 252 struct mmc_cid {
 253         unsigned long psn;
 254         unsigned short oid;
 255         unsigned char mid;
 256         unsigned char prv;
 257         unsigned char mdt;
 258         char pnm[7];
 259 };
 260
 261 struct mmc_cmd {
 262         ushort cmdidx;
 263         uint resp_type;
 264         uint cmdarg;
 265         uint response[4];
 266 };
 267
 268 struct mmc_data {
 269         union {
 270                 char *dest;
 271                 const char *src; /* src buffers don't get written to */
 272         };
 273         uint flags;
 274         uint blocks;
 275         uint blocksize;
 276 };
 277
 278 /* forward decl. */
 279 struct mmc;
 280
 281 struct mmc_ops {
 282         int (*send_cmd)(struct mmc *mmc,
 283                         struct mmc_cmd *cmd, struct mmc_data *data);
 284         void (*set_ios)(struct mmc *mmc);
 285         int (*init)(struct mmc *mmc);
 286         int (*getcd)(struct mmc *mmc);
 287         int (*getwp)(struct mmc *mmc);
 288 };
 289
 290 struct mmc_config {
 291         const char *name;
 292         const struct mmc_ops *ops;
 293         uint host_caps;
 294         uint voltages;
 295         uint f_min;
 296         uint f_max;
 297         uint b_max;
 298         unsigned char part_type;
 299 };
 300
 301 /* TODO struct mmc should be in mmc_private but it's hard to fix right now */
 302 struct mmc {
 303         struct list_head link;
 304         const struct mmc_config *cfg;   /* provided configuration */
 305         uint version;
 306         void *priv;
 307         uint has_init;
 308         int high_capacity;
 309         uint bus_width;
 310         uint clock;
 311         uint card_caps;
 312         uint ocr;
 313         uint dsr;
 314         uint dsr_imp;
 315         uint scr[2];
 316         uint csd[4];
 317         uint cid[4];
 318         ushort rca;
 319         u8 part_support;
 320         u8 part_attr;
 321         u8 wr_rel_set;
 322         char part_config;
 323         char part_num;
 324         uint tran_speed;
 325         uint read_bl_len;
 326         uint write_bl_len;
 327         uint erase_grp_size;    /* in 512-byte sectors */
 328         uint hc_wp_grp_size;    /* in 512-byte sectors */
 329         u64 capacity;
 330         u64 capacity_user;
 331         u64 capacity_boot;
 332         u64 capacity_rpmb;
 333         u64 capacity_gp[4];
 334         u64 enh_user_start;
 335         u64 enh_user_size;
 336         block_dev_desc_t block_dev;
 337         char op_cond_pending;   /* 1 if we are waiting on an op_cond command */
 338         char init_in_progress;  /* 1 if we have done mmc_start_init() */
 339         char preinit;           /* start init as early as possible */
 340         uint op_cond_response;  /* the response byte from the last op_cond */
 341         int ddr_mode;
 342 };
 343
 344 struct mmc_hwpart_conf {
 345         struct {
 346                 uint enh_start; /* in 512-byte sectors */
 347                 uint enh_size;  /* in 512-byte sectors, if 0 no enh area */
 348                 unsigned wr_rel_change : 1;
 349                 unsigned wr_rel_set : 1;
 350         } user;
 351         struct {
 352                 uint size;      /* in 512-byte sectors */
 353                 unsigned enhanced : 1;
 354                 unsigned wr_rel_change : 1;
 355                 unsigned wr_rel_set : 1;
 356         } gp_part[4];
 357 };
 358
 359 enum mmc_hwpart_conf_mode {
 360         MMC_HWPART_CONF_CHECK,
 361         MMC_HWPART_CONF_SET,
 362         MMC_HWPART_CONF_COMPLETE,
 363 };
 364
 365 int mmc_register(struct mmc *mmc);
 366 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
 367 void mmc_destroy(struct mmc *mmc);
 368 int mmc_initialize(bd_t *bis);
 369 int mmc_init(struct mmc *mmc);
 370 int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
 371 void mmc_set_clock(struct mmc *mmc, uint clock);
 372 struct mmc *find_mmc_device(int dev_num);
 373 int mmc_set_dev(int dev_num);
 374 void print_mmc_devices(char separator);
 375 int get_mmc_num(void);
 376 int mmc_switch_part(int dev_num, unsigned int part_num);
 377 int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
 378                       enum mmc_hwpart_conf_mode mode);
 379 int mmc_getcd(struct mmc *mmc);
 380 int board_mmc_getcd(struct mmc *mmc);
 381 int mmc_getwp(struct mmc *mmc);
 382 int board_mmc_getwp(struct mmc *mmc);
 383 int mmc_set_dsr(struct mmc *mmc, u16 val);
 384 /* Function to change the size of boot partition and rpmb partitions */
 385 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
 386                                         unsigned long rpmbsize);
 387 /* Function to modify the PARTITION_CONFIG field of EXT_CSD */
 388 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
 389 /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
 390 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
 391 /* Function to modify the RST_n_FUNCTION field of EXT_CSD */
 392 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
 393 /* Functions to read / write the RPMB partition */
 394 int mmc_rpmb_set_key(struct mmc *mmc, void *key);
 395 int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
 396 int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
 397                   unsigned short cnt, unsigned char *key);
 398 int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
 399                    unsigned short cnt, unsigned char *key);
 400 /**
 401  * Start device initialization and return immediately; it does not block on
 402  * polling OCR (operation condition register) status.  Then you should call
 403  * mmc_init, which would block on polling OCR status and complete the device
 404  * initializatin.
 405  *
 406  * @param mmc   Pointer to a MMC device struct
 407  * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error.
 408  */
 409 int mmc_start_init(struct mmc *mmc);
 410
 411 /**
 412  * Set preinit flag of mmc device.
 413  *
 414  * This will cause the device to be pre-inited during mmc_initialize(),
 415  * which may save boot time if the device is not accessed until later.
 416  * Some eMMC devices take 200-300ms to init, but unfortunately they
 417  * must be sent a series of commands to even get them to start preparing
 418  * for operation.
 419  *
 420  * @param mmc           Pointer to a MMC device struct
 421  * @param preinit       preinit flag value
 422  */
 423 void mmc_set_preinit(struct mmc *mmc, int preinit);
 424
 425 #ifdef CONFIG_GENERIC_MMC
 426 #ifdef CONFIG_MMC_SPI
 427 #define mmc_host_is_spi(mmc)    ((mmc)->cfg->host_caps & MMC_MODE_SPI)
 428 #else
 429 #define mmc_host_is_spi(mmc)    0
 430 #endif
 431 struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
 432 #else
 433 int mmc_legacy_init(int verbose);
 434 #endif
 435
 436 void board_mmc_power_init(void);
 437 int board_mmc_init(bd_t *bis);
 438 int cpu_mmc_init(bd_t *bis);
 439 int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
 440
 441 struct pci_device_id;
 442
 443 /**
 444  * pci_mmc_init() - set up PCI MMC devices
 445  *
 446  * This finds all the matching PCI IDs and sets them up as MMC devices.
 447  *
 448  * @name:               Name to use for devices
 449  * @mmc_supported:      PCI IDs to search for
 450  * @num_ids:            Number of elements in @mmc_supported
 451  */
 452 int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported,
 453                  int num_ids);
 454
 455 /* Set block count limit because of 16 bit register limit on some hardware*/
 456 #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
 457 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
 458 #endif
 459
 460 #endif /* _MMC_H_ */