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git.ipfire.org Git - people/ms/u-boot.git/blob - include/mpc5xxx.h
2 * include/asm-ppc/mpc5xxx.h
4 * Prototypes, etc. for the Motorola MGT5xxx/MPC5xxx
7 * 2003 (c) MontaVista, Software, Inc.
8 * Author: Dale Farnsworth <dfarnsworth@mvista.com>
10 * 2003 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de.
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #ifndef __ASMPPC_MPC5XXX_H
31 #define __ASMPPC_MPC5XXX_H
33 #include <asm/types.h>
36 #if defined(CONFIG_MPC5200)
37 #define CPU_ID_STR "MPC5200"
38 #elif defined(CONFIG_MGT5100)
39 #define CPU_ID_STR "MGT5100"
42 /* Exception offsets (PowerPC standard) */
43 #define EXC_OFF_SYS_RESET 0x0100
44 #define _START_OFFSET EXC_OFF_SYS_RESET
46 /* useful macros for manipulating CSx_START/STOP */
47 #if defined(CONFIG_MGT5100)
48 #define START_REG(start) ((start) >> 15)
49 #define STOP_REG(start, size) (((start) + (size) - 1) >> 15)
50 #elif defined(CONFIG_MPC5200)
51 #define START_REG(start) ((start) >> 16)
52 #define STOP_REG(start, size) (((start) + (size) - 1) >> 16)
55 /* Internal memory map */
57 #define MPC5XXX_CS0_START (CONFIG_SYS_MBAR + 0x0004)
58 #define MPC5XXX_CS0_STOP (CONFIG_SYS_MBAR + 0x0008)
59 #define MPC5XXX_CS1_START (CONFIG_SYS_MBAR + 0x000c)
60 #define MPC5XXX_CS1_STOP (CONFIG_SYS_MBAR + 0x0010)
61 #define MPC5XXX_CS2_START (CONFIG_SYS_MBAR + 0x0014)
62 #define MPC5XXX_CS2_STOP (CONFIG_SYS_MBAR + 0x0018)
63 #define MPC5XXX_CS3_START (CONFIG_SYS_MBAR + 0x001c)
64 #define MPC5XXX_CS3_STOP (CONFIG_SYS_MBAR + 0x0020)
65 #define MPC5XXX_CS4_START (CONFIG_SYS_MBAR + 0x0024)
66 #define MPC5XXX_CS4_STOP (CONFIG_SYS_MBAR + 0x0028)
67 #define MPC5XXX_CS5_START (CONFIG_SYS_MBAR + 0x002c)
68 #define MPC5XXX_CS5_STOP (CONFIG_SYS_MBAR + 0x0030)
69 #define MPC5XXX_BOOTCS_START (CONFIG_SYS_MBAR + 0x004c)
70 #define MPC5XXX_BOOTCS_STOP (CONFIG_SYS_MBAR + 0x0050)
71 #define MPC5XXX_ADDECR (CONFIG_SYS_MBAR + 0x0054)
73 #if defined(CONFIG_MGT5100)
74 #define MPC5XXX_SDRAM_START (CONFIG_SYS_MBAR + 0x0034)
75 #define MPC5XXX_SDRAM_STOP (CONFIG_SYS_MBAR + 0x0038)
76 #define MPC5XXX_PCI1_START (CONFIG_SYS_MBAR + 0x003c)
77 #define MPC5XXX_PCI1_STOP (CONFIG_SYS_MBAR + 0x0040)
78 #define MPC5XXX_PCI2_START (CONFIG_SYS_MBAR + 0x0044)
79 #define MPC5XXX_PCI2_STOP (CONFIG_SYS_MBAR + 0x0048)
80 #elif defined(CONFIG_MPC5200)
81 #define MPC5XXX_CS6_START (CONFIG_SYS_MBAR + 0x0058)
82 #define MPC5XXX_CS6_STOP (CONFIG_SYS_MBAR + 0x005c)
83 #define MPC5XXX_CS7_START (CONFIG_SYS_MBAR + 0x0060)
84 #define MPC5XXX_CS7_STOP (CONFIG_SYS_MBAR + 0x0064)
85 #define MPC5XXX_SDRAM_CS0CFG (CONFIG_SYS_MBAR + 0x0034)
86 #define MPC5XXX_SDRAM_CS1CFG (CONFIG_SYS_MBAR + 0x0038)
89 #define MPC5XXX_SDRAM (CONFIG_SYS_MBAR + 0x0100)
90 #define MPC5XXX_CDM (CONFIG_SYS_MBAR + 0x0200)
91 #define MPC5XXX_LPB (CONFIG_SYS_MBAR + 0x0300)
92 #define MPC5XXX_ICTL (CONFIG_SYS_MBAR + 0x0500)
93 #define MPC5XXX_GPT (CONFIG_SYS_MBAR + 0x0600)
94 #define MPC5XXX_GPIO (CONFIG_SYS_MBAR + 0x0b00)
95 #define MPC5XXX_WU_GPIO (CONFIG_SYS_MBAR + 0x0c00)
96 #define MPC5XXX_PCI (CONFIG_SYS_MBAR + 0x0d00)
97 #define MPC5XXX_SPI (CONFIG_SYS_MBAR + 0x0f00)
98 #define MPC5XXX_USB (CONFIG_SYS_MBAR + 0x1000)
99 #define MPC5XXX_SDMA (CONFIG_SYS_MBAR + 0x1200)
100 #define MPC5XXX_XLBARB (CONFIG_SYS_MBAR + 0x1f00)
102 #if defined(CONFIG_MGT5100)
103 #define MPC5XXX_PSC1 (CONFIG_SYS_MBAR + 0x2000)
104 #define MPC5XXX_PSC2 (CONFIG_SYS_MBAR + 0x2400)
105 #define MPC5XXX_PSC3 (CONFIG_SYS_MBAR + 0x2800)
106 #elif defined(CONFIG_MPC5200)
107 #define MPC5XXX_PSC1 (CONFIG_SYS_MBAR + 0x2000)
108 #define MPC5XXX_PSC2 (CONFIG_SYS_MBAR + 0x2200)
109 #define MPC5XXX_PSC3 (CONFIG_SYS_MBAR + 0x2400)
110 #define MPC5XXX_PSC4 (CONFIG_SYS_MBAR + 0x2600)
111 #define MPC5XXX_PSC5 (CONFIG_SYS_MBAR + 0x2800)
112 #define MPC5XXX_PSC6 (CONFIG_SYS_MBAR + 0x2c00)
115 #define MPC5XXX_FEC (CONFIG_SYS_MBAR + 0x3000)
116 #define MPC5XXX_ATA (CONFIG_SYS_MBAR + 0x3A00)
118 #define MPC5XXX_I2C1 (CONFIG_SYS_MBAR + 0x3D00)
119 #define MPC5XXX_I2C2 (CONFIG_SYS_MBAR + 0x3D40)
121 #if defined(CONFIG_MGT5100)
122 #define MPC5XXX_SRAM (CONFIG_SYS_MBAR + 0x4000)
123 #define MPC5XXX_SRAM_SIZE (8*1024)
124 #elif defined(CONFIG_MPC5200)
125 #define MPC5XXX_SRAM (CONFIG_SYS_MBAR + 0x8000)
126 #define MPC5XXX_SRAM_SIZE (16*1024)
129 /* SDRAM Controller */
130 #define MPC5XXX_SDRAM_MODE (MPC5XXX_SDRAM + 0x0000)
131 #define MPC5XXX_SDRAM_CTRL (MPC5XXX_SDRAM + 0x0004)
132 #define MPC5XXX_SDRAM_CONFIG1 (MPC5XXX_SDRAM + 0x0008)
133 #define MPC5XXX_SDRAM_CONFIG2 (MPC5XXX_SDRAM + 0x000c)
134 #if defined(CONFIG_MGT5100)
135 #define MPC5XXX_SDRAM_XLBSEL (MPC5XXX_SDRAM + 0x0010)
137 #define MPC5XXX_SDRAM_SDELAY (MPC5XXX_SDRAM + 0x0090)
139 /* Clock Distribution Module */
140 #define MPC5XXX_CDM_JTAGID (MPC5XXX_CDM + 0x0000)
141 #define MPC5XXX_CDM_PORCFG (MPC5XXX_CDM + 0x0004)
142 #define MPC5XXX_CDM_BRDCRMB (MPC5XXX_CDM + 0x0008)
143 #define MPC5XXX_CDM_CFG (MPC5XXX_CDM + 0x000c)
144 #define MPC5XXX_CDM_48_FDC (MPC5XXX_CDM + 0x0010)
145 #define MPC5XXX_CDM_CLK_ENA (MPC5XXX_CDM + 0x0014)
146 #define MPC5XXX_CDM_SRESET (MPC5XXX_CDM + 0x0020)
148 /* Local Plus Bus interface */
149 #define MPC5XXX_CS0_CFG (MPC5XXX_LPB + 0x0000)
150 #define MPC5XXX_CS1_CFG (MPC5XXX_LPB + 0x0004)
151 #define MPC5XXX_CS2_CFG (MPC5XXX_LPB + 0x0008)
152 #define MPC5XXX_CS3_CFG (MPC5XXX_LPB + 0x000c)
153 #define MPC5XXX_CS4_CFG (MPC5XXX_LPB + 0x0010)
154 #define MPC5XXX_CS5_CFG (MPC5XXX_LPB + 0x0014)
155 #define MPC5XXX_BOOTCS_CFG MPC5XXX_CS0_CFG
156 #define MPC5XXX_CS_CTRL (MPC5XXX_LPB + 0x0018)
157 #define MPC5XXX_CS_STATUS (MPC5XXX_LPB + 0x001c)
158 #if defined(CONFIG_MPC5200)
159 #define MPC5XXX_CS6_CFG (MPC5XXX_LPB + 0x0020)
160 #define MPC5XXX_CS7_CFG (MPC5XXX_LPB + 0x0024)
161 #define MPC5XXX_CS_BURST (MPC5XXX_LPB + 0x0028)
162 #define MPC5XXX_CS_DEADCYCLE (MPC5XXX_LPB + 0x002c)
165 #if defined(CONFIG_MPC5200)
166 /* XLB Arbiter registers */
167 #define MPC5XXX_XLBARB_CFG (MPC5XXX_XLBARB + 0x40)
168 #define MPC5XXX_XLBARB_MPRIEN (MPC5XXX_XLBARB + 0x64)
169 #define MPC5XXX_XLBARB_MPRIVAL (MPC5XXX_XLBARB + 0x68)
173 #define MPC5XXX_GPS_PORT_CONFIG (MPC5XXX_GPIO + 0x0000)
175 /* Standard GPIO registers (simple, output only and simple interrupt */
176 #define MPC5XXX_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004)
177 #define MPC5XXX_GPIO_ODE (MPC5XXX_GPIO + 0x0008)
178 #define MPC5XXX_GPIO_DIR (MPC5XXX_GPIO + 0x000c)
179 #define MPC5XXX_GPIO_DATA_O (MPC5XXX_GPIO + 0x0010)
180 #define MPC5XXX_GPIO_DATA_I (MPC5XXX_GPIO + 0x0014)
181 #define MPC5XXX_GPIO_OO_ENABLE (MPC5XXX_GPIO + 0x0018)
182 #define MPC5XXX_GPIO_OO_DATA (MPC5XXX_GPIO + 0x001C)
183 #define MPC5XXX_GPIO_SI_ENABLE (MPC5XXX_GPIO + 0x0020)
184 #define MPC5XXX_GPIO_SI_ODE (MPC5XXX_GPIO + 0x0024)
185 #define MPC5XXX_GPIO_SI_DIR (MPC5XXX_GPIO + 0x0028)
186 #define MPC5XXX_GPIO_SI_DATA (MPC5XXX_GPIO + 0x002C)
187 #define MPC5XXX_GPIO_SI_IEN (MPC5XXX_GPIO + 0x0030)
188 #define MPC5XXX_GPIO_SI_ITYPE (MPC5XXX_GPIO + 0x0034)
189 #define MPC5XXX_GPIO_SI_MEN (MPC5XXX_GPIO + 0x0038)
190 #define MPC5XXX_GPIO_SI_STATUS (MPC5XXX_GPIO + 0x003C)
192 /* WakeUp GPIO registers */
193 #define MPC5XXX_WU_GPIO_ENABLE (MPC5XXX_WU_GPIO + 0x0000)
194 #define MPC5XXX_WU_GPIO_ODE (MPC5XXX_WU_GPIO + 0x0004)
195 #define MPC5XXX_WU_GPIO_DIR (MPC5XXX_WU_GPIO + 0x0008)
196 #define MPC5XXX_WU_GPIO_DATA_O (MPC5XXX_WU_GPIO + 0x000c)
197 #define MPC5XXX_WU_GPIO_DATA_I (MPC5XXX_WU_GPIO + 0x0020)
200 #define GPIO_WKUP_7 0x80000000UL
201 #define GPIO_PSC6_0 0x10000000UL
202 #define GPIO_PSC3_9 0x04000000UL
203 #define GPIO_PSC1_4 0x01000000UL
205 #define MPC5XXX_GPIO_SIMPLE_PSC6_3 0x20000000UL
206 #define MPC5XXX_GPIO_SIMPLE_PSC6_2 0x10000000UL
207 #define MPC5XXX_GPIO_SIMPLE_PSC3_7 0x00002000UL
208 #define MPC5XXX_GPIO_SIMPLE_PSC3_6 0x00001000UL
209 #define MPC5XXX_GPIO_SIMPLE_PSC3_3 0x00000800UL
210 #define MPC5XXX_GPIO_SIMPLE_PSC3_2 0x00000400UL
211 #define MPC5XXX_GPIO_SIMPLE_PSC3_1 0x00000200UL
212 #define MPC5XXX_GPIO_SIMPLE_PSC3_0 0x00000100UL
213 #define MPC5XXX_GPIO_SIMPLE_PSC2_3 0x00000080UL
214 #define MPC5XXX_GPIO_SIMPLE_PSC2_2 0x00000040UL
215 #define MPC5XXX_GPIO_SIMPLE_PSC2_1 0x00000020UL
216 #define MPC5XXX_GPIO_SIMPLE_PSC2_0 0x00000010UL
217 #define MPC5XXX_GPIO_SIMPLE_PSC1_3 0x00000008UL
218 #define MPC5XXX_GPIO_SIMPLE_PSC1_2 0x00000004UL
219 #define MPC5XXX_GPIO_SIMPLE_PSC1_1 0x00000002UL
220 #define MPC5XXX_GPIO_SIMPLE_PSC1_0 0x00000001UL
222 #define MPC5XXX_GPIO_SINT_ETH_16 0x80
223 #define MPC5XXX_GPIO_SINT_ETH_15 0x40
224 #define MPC5XXX_GPIO_SINT_ETH_14 0x20
225 #define MPC5XXX_GPIO_SINT_ETH_13 0x10
226 #define MPC5XXX_GPIO_SINT_USB1_9 0x08
227 #define MPC5XXX_GPIO_SINT_PSC3_8 0x04
228 #define MPC5XXX_GPIO_SINT_PSC3_5 0x02
229 #define MPC5XXX_GPIO_SINT_PSC3_4 0x01
231 #define MPC5XXX_GPIO_WKUP_7 0x80
232 #define MPC5XXX_GPIO_WKUP_6 0x40
233 #define MPC5XXX_GPIO_WKUP_PSC6_1 0x20
234 #define MPC5XXX_GPIO_WKUP_PSC6_0 0x10
235 #define MPC5XXX_GPIO_WKUP_ETH17 0x08
236 #define MPC5XXX_GPIO_WKUP_PSC3_9 0x04
237 #define MPC5XXX_GPIO_WKUP_PSC2_4 0x02
238 #define MPC5XXX_GPIO_WKUP_PSC1_4 0x01
241 #define MPC5XXX_PCI_CMD (MPC5XXX_PCI + 0x04)
242 #define MPC5XXX_PCI_CFG (MPC5XXX_PCI + 0x0c)
243 #define MPC5XXX_PCI_BAR0 (MPC5XXX_PCI + 0x10)
244 #define MPC5XXX_PCI_BAR1 (MPC5XXX_PCI + 0x14)
245 #if defined(CONFIG_MGT5100)
246 #define MPC5XXX_PCI_CTRL (MPC5XXX_PCI + 0x68)
247 #define MPC5XXX_PCI_VALMSKR (MPC5XXX_PCI + 0x6c)
248 #define MPC5XXX_PCI_VALMSKW (MPC5XXX_PCI + 0x70)
249 #define MPC5XXX_PCI_SUBW1 (MPC5XXX_PCI + 0x74)
250 #define MPC5XXX_PCI_SUBW2 (MPC5XXX_PCI + 0x78)
251 #define MPC5XXX_PCI_WINCOMMAND (MPC5XXX_PCI + 0x7c)
252 #elif defined(CONFIG_MPC5200)
253 #define MPC5XXX_PCI_GSCR (MPC5XXX_PCI + 0x60)
254 #define MPC5XXX_PCI_TBATR0 (MPC5XXX_PCI + 0x64)
255 #define MPC5XXX_PCI_TBATR1 (MPC5XXX_PCI + 0x68)
256 #define MPC5XXX_PCI_TCR (MPC5XXX_PCI + 0x6c)
257 #define MPC5XXX_PCI_IW0BTAR (MPC5XXX_PCI + 0x70)
258 #define MPC5XXX_PCI_IW1BTAR (MPC5XXX_PCI + 0x74)
259 #define MPC5XXX_PCI_IW2BTAR (MPC5XXX_PCI + 0x78)
260 #define MPC5XXX_PCI_IWCR (MPC5XXX_PCI + 0x80)
261 #define MPC5XXX_PCI_ICR (MPC5XXX_PCI + 0x84)
262 #define MPC5XXX_PCI_ISR (MPC5XXX_PCI + 0x88)
263 #define MPC5XXX_PCI_ARB (MPC5XXX_PCI + 0x8c)
264 #define MPC5XXX_PCI_CAR (MPC5XXX_PCI + 0xf8)
267 /* Interrupt Controller registers */
268 #define MPC5XXX_ICTL_PER_MASK (MPC5XXX_ICTL + 0x0000)
269 #define MPC5XXX_ICTL_PER_PRIO1 (MPC5XXX_ICTL + 0x0004)
270 #define MPC5XXX_ICTL_PER_PRIO2 (MPC5XXX_ICTL + 0x0008)
271 #define MPC5XXX_ICTL_PER_PRIO3 (MPC5XXX_ICTL + 0x000c)
272 #define MPC5XXX_ICTL_EXT (MPC5XXX_ICTL + 0x0010)
273 #define MPC5XXX_ICTL_CRIT (MPC5XXX_ICTL + 0x0014)
274 #define MPC5XXX_ICTL_MAIN_PRIO1 (MPC5XXX_ICTL + 0x0018)
275 #define MPC5XXX_ICTL_MAIN_PRIO2 (MPC5XXX_ICTL + 0x001c)
276 #define MPC5XXX_ICTL_STS (MPC5XXX_ICTL + 0x0024)
277 #define MPC5XXX_ICTL_CRIT_STS (MPC5XXX_ICTL + 0x0028)
278 #define MPC5XXX_ICTL_MAIN_STS (MPC5XXX_ICTL + 0x002c)
279 #define MPC5XXX_ICTL_PER_STS (MPC5XXX_ICTL + 0x0030)
280 #define MPC5XXX_ICTL_BUS_STS (MPC5XXX_ICTL + 0x0038)
284 /* IRQ mapping - these are our logical IRQ numbers */
285 #define MPC5XXX_CRIT_IRQ_NUM 4
286 #define MPC5XXX_MAIN_IRQ_NUM 17
287 #define MPC5XXX_SDMA_IRQ_NUM 17
288 #define MPC5XXX_PERP_IRQ_NUM 23
290 #define MPC5XXX_CRIT_IRQ_BASE 1
291 #define MPC5XXX_MAIN_IRQ_BASE (MPC5XXX_CRIT_IRQ_BASE + MPC5XXX_CRIT_IRQ_NUM)
292 #define MPC5XXX_SDMA_IRQ_BASE (MPC5XXX_MAIN_IRQ_BASE + MPC5XXX_MAIN_IRQ_NUM)
293 #define MPC5XXX_PERP_IRQ_BASE (MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM)
295 #define MPC5XXX_IRQ0 (MPC5XXX_CRIT_IRQ_BASE + 0)
296 #define MPC5XXX_SLICE_TIMER_0_IRQ (MPC5XXX_CRIT_IRQ_BASE + 1)
297 #define MPC5XXX_HI_INT_IRQ (MPC5XXX_CRIT_IRQ_BASE + 2)
298 #define MPC5XXX_CCS_IRQ (MPC5XXX_CRIT_IRQ_BASE + 3)
300 #define MPC5XXX_IRQ1 (MPC5XXX_MAIN_IRQ_BASE + 1)
301 #define MPC5XXX_IRQ2 (MPC5XXX_MAIN_IRQ_BASE + 2)
302 #define MPC5XXX_IRQ3 (MPC5XXX_MAIN_IRQ_BASE + 3)
303 #define MPC5XXX_RTC_PINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 5)
304 #define MPC5XXX_RTC_SINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 6)
305 #define MPC5XXX_RTC_GPIO_STD_IRQ (MPC5XXX_MAIN_IRQ_BASE + 7)
306 #define MPC5XXX_RTC_GPIO_WKUP_IRQ (MPC5XXX_MAIN_IRQ_BASE + 8)
307 #define MPC5XXX_TMR0_IRQ (MPC5XXX_MAIN_IRQ_BASE + 9)
308 #define MPC5XXX_TMR1_IRQ (MPC5XXX_MAIN_IRQ_BASE + 10)
309 #define MPC5XXX_TMR2_IRQ (MPC5XXX_MAIN_IRQ_BASE + 11)
310 #define MPC5XXX_TMR3_IRQ (MPC5XXX_MAIN_IRQ_BASE + 12)
311 #define MPC5XXX_TMR4_IRQ (MPC5XXX_MAIN_IRQ_BASE + 13)
312 #define MPC5XXX_TMR5_IRQ (MPC5XXX_MAIN_IRQ_BASE + 14)
313 #define MPC5XXX_TMR6_IRQ (MPC5XXX_MAIN_IRQ_BASE + 15)
314 #define MPC5XXX_TMR7_IRQ (MPC5XXX_MAIN_IRQ_BASE + 16)
316 #define MPC5XXX_SDMA_IRQ (MPC5XXX_PERP_IRQ_BASE + 0)
317 #define MPC5XXX_PSC1_IRQ (MPC5XXX_PERP_IRQ_BASE + 1)
318 #define MPC5XXX_PSC2_IRQ (MPC5XXX_PERP_IRQ_BASE + 2)
319 #define MPC5XXX_PSC3_IRQ (MPC5XXX_PERP_IRQ_BASE + 3)
320 #define MPC5XXX_PSC6_IRQ (MPC5XXX_PERP_IRQ_BASE + 4)
321 #define MPC5XXX_IRDA_IRQ (MPC5XXX_PERP_IRQ_BASE + 4)
322 #define MPC5XXX_FEC_IRQ (MPC5XXX_PERP_IRQ_BASE + 5)
323 #define MPC5XXX_USB_IRQ (MPC5XXX_PERP_IRQ_BASE + 6)
324 #define MPC5XXX_ATA_IRQ (MPC5XXX_PERP_IRQ_BASE + 7)
325 #define MPC5XXX_PCI_CNTRL_IRQ (MPC5XXX_PERP_IRQ_BASE + 8)
326 #define MPC5XXX_PCI_SCIRX_IRQ (MPC5XXX_PERP_IRQ_BASE + 9)
327 #define MPC5XXX_PCI_SCITX_IRQ (MPC5XXX_PERP_IRQ_BASE + 10)
328 #define MPC5XXX_PSC4_IRQ (MPC5XXX_PERP_IRQ_BASE + 11)
329 #define MPC5XXX_PSC5_IRQ (MPC5XXX_PERP_IRQ_BASE + 12)
330 #define MPC5XXX_SPI_MODF_IRQ (MPC5XXX_PERP_IRQ_BASE + 13)
331 #define MPC5XXX_SPI_SPIF_IRQ (MPC5XXX_PERP_IRQ_BASE + 14)
332 #define MPC5XXX_I2C1_IRQ (MPC5XXX_PERP_IRQ_BASE + 15)
333 #define MPC5XXX_I2C2_IRQ (MPC5XXX_PERP_IRQ_BASE + 16)
334 #define MPC5XXX_MSCAN1_IRQ (MPC5XXX_PERP_IRQ_BASE + 17)
335 #define MPC5XXX_MSCAN2_IRQ (MPC5XXX_PERP_IRQ_BASE + 18)
336 #define MPC5XXX_IR_RX_IRQ (MPC5XXX_PERP_IRQ_BASE + 19)
337 #define MPC5XXX_IR_TX_IRQ (MPC5XXX_PERP_IRQ_BASE + 20)
338 #define MPC5XXX_XLB_ARB_IRQ (MPC5XXX_PERP_IRQ_BASE + 21)
339 #define MPC5XXX_BDLC_IRQ (MPC5XXX_PERP_IRQ_BASE + 22)
341 /* General Purpose Timers registers */
342 #define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0)
343 #define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4)
344 #define MPC5XXX_GPT0_STATUS (MPC5XXX_GPT + 0x0C)
345 #define MPC5XXX_GPT1_ENABLE (MPC5XXX_GPT + 0x10)
346 #define MPC5XXX_GPT1_COUNTER (MPC5XXX_GPT + 0x14)
347 #define MPC5XXX_GPT1_STATUS (MPC5XXX_GPT + 0x1C)
348 #define MPC5XXX_GPT2_ENABLE (MPC5XXX_GPT + 0x20)
349 #define MPC5XXX_GPT2_COUNTER (MPC5XXX_GPT + 0x24)
350 #define MPC5XXX_GPT2_STATUS (MPC5XXX_GPT + 0x2C)
351 #define MPC5XXX_GPT3_ENABLE (MPC5XXX_GPT + 0x30)
352 #define MPC5XXX_GPT3_COUNTER (MPC5XXX_GPT + 0x34)
353 #define MPC5XXX_GPT3_STATUS (MPC5XXX_GPT + 0x3C)
354 #define MPC5XXX_GPT4_ENABLE (MPC5XXX_GPT + 0x40)
355 #define MPC5XXX_GPT4_COUNTER (MPC5XXX_GPT + 0x44)
356 #define MPC5XXX_GPT4_STATUS (MPC5XXX_GPT + 0x4C)
357 #define MPC5XXX_GPT5_ENABLE (MPC5XXX_GPT + 0x50)
358 #define MPC5XXX_GPT5_STATUS (MPC5XXX_GPT + 0x5C)
359 #define MPC5XXX_GPT5_COUNTER (MPC5XXX_GPT + 0x54)
360 #define MPC5XXX_GPT6_ENABLE (MPC5XXX_GPT + 0x60)
361 #define MPC5XXX_GPT6_COUNTER (MPC5XXX_GPT + 0x64)
362 #define MPC5XXX_GPT6_STATUS (MPC5XXX_GPT + 0x6C)
363 #define MPC5XXX_GPT7_ENABLE (MPC5XXX_GPT + 0x70)
364 #define MPC5XXX_GPT7_COUNTER (MPC5XXX_GPT + 0x74)
365 #define MPC5XXX_GPT7_STATUS (MPC5XXX_GPT + 0x7C)
367 #define MPC5XXX_GPT_GPIO_PIN(status) ((0x00000100 & (status)) >> 8)
369 #define MPC5XXX_GPT7_PWMCFG (MPC5XXX_GPT + 0x78)
372 #define MPC5XXX_ATA_HOST_CONFIG (MPC5XXX_ATA + 0x0000)
373 #define MPC5XXX_ATA_PIO1 (MPC5XXX_ATA + 0x0008)
374 #define MPC5XXX_ATA_PIO2 (MPC5XXX_ATA + 0x000C)
375 #define MPC5XXX_ATA_SHARE_COUNT (MPC5XXX_ATA + 0x002C)
377 /* I2Cn control register bits */
382 #define I2C_TXAK 0x08
383 #define I2C_RSTA 0x04
384 #define I2C_INIT_MASK (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA)
386 /* I2Cn status register bits */
393 #define I2C_RXAK 0x01
395 /* SPI control register 1 bits */
396 #define SPI_CR_LSBFE 0x01
397 #define SPI_CR_SSOE 0x02
398 #define SPI_CR_CPHA 0x04
399 #define SPI_CR_CPOL 0x08
400 #define SPI_CR_MSTR 0x10
401 #define SPI_CR_SWOM 0x20
402 #define SPI_CR_SPE 0x40
403 #define SPI_CR_SPIE 0x80
405 /* SPI status register bits */
406 #define SPI_SR_MODF 0x10
407 #define SPI_SR_WCOL 0x40
408 #define SPI_SR_SPIF 0x80
410 /* SPI port data register bits */
411 #define SPI_PDR_SS 0x08
413 /* Programmable Serial Controller (PSC) status register bits */
414 #define PSC_SR_CDE 0x0080
415 #define PSC_SR_RXRDY 0x0100
416 #define PSC_SR_RXFULL 0x0200
417 #define PSC_SR_TXRDY 0x0400
418 #define PSC_SR_TXEMP 0x0800
419 #define PSC_SR_OE 0x1000
420 #define PSC_SR_PE 0x2000
421 #define PSC_SR_FE 0x4000
422 #define PSC_SR_RB 0x8000
424 /* PSC Command values */
425 #define PSC_RX_ENABLE 0x0001
426 #define PSC_RX_DISABLE 0x0002
427 #define PSC_TX_ENABLE 0x0004
428 #define PSC_TX_DISABLE 0x0008
429 #define PSC_SEL_MODE_REG_1 0x0010
430 #define PSC_RST_RX 0x0020
431 #define PSC_RST_TX 0x0030
432 #define PSC_RST_ERR_STAT 0x0040
433 #define PSC_RST_BRK_CHG_INT 0x0050
434 #define PSC_START_BRK 0x0060
435 #define PSC_STOP_BRK 0x0070
437 /* PSC Rx FIFO status bits */
438 #define PSC_RX_FIFO_ERR 0x0040
439 #define PSC_RX_FIFO_UF 0x0020
440 #define PSC_RX_FIFO_OF 0x0010
441 #define PSC_RX_FIFO_FR 0x0008
442 #define PSC_RX_FIFO_FULL 0x0004
443 #define PSC_RX_FIFO_ALARM 0x0002
444 #define PSC_RX_FIFO_EMPTY 0x0001
446 /* PSC interrupt mask bits */
447 #define PSC_IMR_TXRDY 0x0100
448 #define PSC_IMR_RXRDY 0x0200
449 #define PSC_IMR_DB 0x0400
450 #define PSC_IMR_IPC 0x8000
452 /* PSC input port change bits */
453 #define PSC_IPCR_CTS 0x01
454 #define PSC_IPCR_DCD 0x02
456 /* PSC mode fields */
457 #define PSC_MODE_5_BITS 0x00
458 #define PSC_MODE_6_BITS 0x01
459 #define PSC_MODE_7_BITS 0x02
460 #define PSC_MODE_8_BITS 0x03
461 #define PSC_MODE_PAREVEN 0x00
462 #define PSC_MODE_PARODD 0x04
463 #define PSC_MODE_PARFORCE 0x08
464 #define PSC_MODE_PARNONE 0x10
465 #define PSC_MODE_ERR 0x20
466 #define PSC_MODE_FFULL 0x40
467 #define PSC_MODE_RXRTS 0x80
469 #define PSC_MODE_ONE_STOP_5_BITS 0x00
470 #define PSC_MODE_ONE_STOP 0x07
471 #define PSC_MODE_TWO_STOP 0x0f
473 /* ATA config fields */
474 #define MPC5xxx_ATA_HOSTCONF_SMR 0x80000000UL /* State machine
476 #define MPC5xxx_ATA_HOSTCONF_FR 0x40000000UL /* FIFO Reset */
477 #define MPC5xxx_ATA_HOSTCONF_IE 0x02000000UL /* Enable interrupt
479 #define MPC5xxx_ATA_HOSTCONF_IORDY 0x01000000UL /* Drive supports
483 /* Memory map registers */
484 struct mpc5xxx_mmap_ctl
{
486 volatile u32 cs0_start
; /* 0x0004 */
487 volatile u32 cs0_stop
;
488 volatile u32 cs1_start
; /* 0x000c */
489 volatile u32 cs1_stop
;
490 volatile u32 cs2_start
; /* 0x0014 */
491 volatile u32 cs2_stop
;
492 volatile u32 cs3_start
; /* 0x001c */
493 volatile u32 cs3_stop
;
494 volatile u32 cs4_start
; /* 0x0024 */
495 volatile u32 cs4_stop
;
496 volatile u32 cs5_start
; /* 0x002c */
497 volatile u32 cs5_stop
;
498 #if defined(CONFIG_MGT5100)
499 volatile u32 sdram_start
; /* 0x0034 */
500 volatile u32 sdram_stop
; /* 0x0038 */
501 volatile u32 pci1_start
; /* 0x003c */
502 volatile u32 pci1_stop
; /* 0x0040 */
503 volatile u32 pci2_start
; /* 0x0044 */
504 volatile u32 pci2_stop
; /* 0x0048 */
505 #elif defined(CONFIG_MPC5200)
506 volatile u32 sdram0
; /* 0x0034 */
507 volatile u32 sdram1
; /* 0x0038 */
508 volatile u32 dummy1
[4]; /* 0x003c */
510 volatile u32 boot_start
; /* 0x004c */
511 volatile u32 boot_stop
;
512 #if defined(CONFIG_MGT5100)
513 volatile u32 addecr
; /* 0x0054 */
514 #elif defined(CONFIG_MPC5200)
515 volatile u32 ipbi_ws_ctrl
; /* 0x0054 */
517 #if defined(CONFIG_MPC5200)
518 volatile u32 cs6_start
; /* 0x0058 */
519 volatile u32 cs6_stop
;
520 volatile u32 cs7_start
; /* 0x0060 */
521 volatile u32 cs7_stop
;
525 /* Clock distribution module */
527 volatile u32 jtagid
; /* 0x0000 */
529 volatile u32 brdcrmb
; /* 0x0008 */
531 volatile u32 fourtyeight_fdc
;/* 0x0010 */
532 volatile u32 clock_enable
;
533 volatile u32 system_osc
; /* 0x0018 */
535 volatile u32 sreset
; /* 0x0020 */
536 volatile u32 pll_status
;
537 volatile u32 psc1_mccr
; /* 0x0028 */
538 volatile u32 psc2_mccr
;
539 volatile u32 psc3_mccr
; /* 0x0030 */
540 volatile u32 psc6_mccr
;
543 /* SDRAM controller */
544 struct mpc5xxx_sdram
{
547 volatile u32 config1
;
548 volatile u32 config2
;
549 #if defined(CONFIG_MGT5100)
551 volatile u32 dummy
[31];
553 volatile u32 dummy
[32];
559 volatile u32 cs0_cfg
;
560 volatile u32 cs1_cfg
;
561 volatile u32 cs2_cfg
;
562 volatile u32 cs3_cfg
;
563 volatile u32 cs4_cfg
;
564 volatile u32 cs5_cfg
;
565 volatile u32 cs_ctrl
;
566 volatile u32 cs_status
;
567 #if defined(CONFIG_MPC5200)
568 volatile u32 cs6_cfg
;
569 volatile u32 cs7_cfg
;
570 volatile u32 cs_burst
;
571 volatile u32 cs_deadcycle
;
577 volatile u8 mode
; /* PSC + 0x00 */
578 volatile u8 reserved0
[3];
579 union { /* PSC + 0x04 */
581 volatile u16 clock_select
;
583 #define psc_status sr_csr.status
584 #define psc_clock_select sr_csr.clock_select
585 volatile u16 reserved1
;
586 volatile u8 command
; /* PSC + 0x08 */
587 volatile u8 reserved2
[3];
588 union { /* PSC + 0x0c */
589 volatile u8 buffer_8
;
590 volatile u16 buffer_16
;
591 volatile u32 buffer_32
;
593 #define psc_buffer_8 buffer.buffer_8
594 #define psc_buffer_16 buffer.buffer_16
595 #define psc_buffer_32 buffer.buffer_32
596 union { /* PSC + 0x10 */
600 #define psc_ipcr ipcr_acr.ipcr
601 #define psc_acr ipcr_acr.acr
602 volatile u8 reserved3
[3];
603 union { /* PSC + 0x14 */
607 #define psc_isr isr_imr.isr
608 #define psc_imr isr_imr.imr
609 volatile u16 reserved4
;
610 volatile u8 ctur
; /* PSC + 0x18 */
611 volatile u8 reserved5
[3];
612 volatile u8 ctlr
; /* PSC + 0x1c */
613 volatile u8 reserved6
[3];
614 volatile u16 ccr
; /* PSC + 0x20 */
615 volatile u8 reserved7
[14];
616 volatile u8 ivr
; /* PSC + 0x30 */
617 volatile u8 reserved8
[3];
618 volatile u8 ip
; /* PSC + 0x34 */
619 volatile u8 reserved9
[3];
620 volatile u8 op1
; /* PSC + 0x38 */
621 volatile u8 reserved10
[3];
622 volatile u8 op0
; /* PSC + 0x3c */
623 volatile u8 reserved11
[3];
624 volatile u32 sicr
; /* PSC + 0x40 */
625 volatile u8 ircr1
; /* PSC + 0x44 */
626 volatile u8 reserved12
[3];
627 volatile u8 ircr2
; /* PSC + 0x44 */
628 volatile u8 reserved13
[3];
629 volatile u8 irsdr
; /* PSC + 0x4c */
630 volatile u8 reserved14
[3];
631 volatile u8 irmdr
; /* PSC + 0x50 */
632 volatile u8 reserved15
[3];
633 volatile u8 irfdr
; /* PSC + 0x54 */
634 volatile u8 reserved16
[3];
635 volatile u16 rfnum
; /* PSC + 0x58 */
636 volatile u16 reserved17
;
637 volatile u16 tfnum
; /* PSC + 0x5c */
638 volatile u16 reserved18
;
639 volatile u32 rfdata
; /* PSC + 0x60 */
640 volatile u16 rfstat
; /* PSC + 0x64 */
641 volatile u16 reserved20
;
642 volatile u8 rfcntl
; /* PSC + 0x68 */
643 volatile u8 reserved21
[5];
644 volatile u16 rfalarm
; /* PSC + 0x6e */
645 volatile u16 reserved22
;
646 volatile u16 rfrptr
; /* PSC + 0x72 */
647 volatile u16 reserved23
;
648 volatile u16 rfwptr
; /* PSC + 0x76 */
649 volatile u16 reserved24
;
650 volatile u16 rflrfptr
; /* PSC + 0x7a */
651 volatile u16 reserved25
;
652 volatile u16 rflwfptr
; /* PSC + 0x7e */
653 volatile u32 tfdata
; /* PSC + 0x80 */
654 volatile u16 tfstat
; /* PSC + 0x84 */
655 volatile u16 reserved26
;
656 volatile u8 tfcntl
; /* PSC + 0x88 */
657 volatile u8 reserved27
[5];
658 volatile u16 tfalarm
; /* PSC + 0x8e */
659 volatile u16 reserved28
;
660 volatile u16 tfrptr
; /* PSC + 0x92 */
661 volatile u16 reserved29
;
662 volatile u16 tfwptr
; /* PSC + 0x96 */
663 volatile u16 reserved30
;
664 volatile u16 tflrfptr
; /* PSC + 0x9a */
665 volatile u16 reserved31
;
666 volatile u16 tflwfptr
; /* PSC + 0x9e */
669 struct mpc5xxx_intr
{
670 volatile u32 per_mask
; /* INTR + 0x00 */
671 volatile u32 per_pri1
; /* INTR + 0x04 */
672 volatile u32 per_pri2
; /* INTR + 0x08 */
673 volatile u32 per_pri3
; /* INTR + 0x0c */
674 volatile u32 ctrl
; /* INTR + 0x10 */
675 volatile u32 main_mask
; /* INTR + 0x14 */
676 volatile u32 main_pri1
; /* INTR + 0x18 */
677 volatile u32 main_pri2
; /* INTR + 0x1c */
678 volatile u32 reserved1
; /* INTR + 0x20 */
679 volatile u32 enc_status
; /* INTR + 0x24 */
680 volatile u32 crit_status
; /* INTR + 0x28 */
681 volatile u32 main_status
; /* INTR + 0x2c */
682 volatile u32 per_status
; /* INTR + 0x30 */
683 volatile u32 reserved2
; /* INTR + 0x34 */
684 volatile u32 per_error
; /* INTR + 0x38 */
687 struct mpc5xxx_gpio
{
688 volatile u32 port_config
; /* GPIO + 0x00 */
689 volatile u32 simple_gpioe
; /* GPIO + 0x04 */
690 volatile u32 simple_ode
; /* GPIO + 0x08 */
691 volatile u32 simple_ddr
; /* GPIO + 0x0c */
692 volatile u32 simple_dvo
; /* GPIO + 0x10 */
693 volatile u32 simple_ival
; /* GPIO + 0x14 */
694 volatile u8 outo_gpioe
; /* GPIO + 0x18 */
695 volatile u8 reserved1
[3]; /* GPIO + 0x19 */
696 volatile u8 outo_dvo
; /* GPIO + 0x1c */
697 volatile u8 reserved2
[3]; /* GPIO + 0x1d */
698 volatile u8 sint_gpioe
; /* GPIO + 0x20 */
699 volatile u8 reserved3
[3]; /* GPIO + 0x21 */
700 volatile u8 sint_ode
; /* GPIO + 0x24 */
701 volatile u8 reserved4
[3]; /* GPIO + 0x25 */
702 volatile u8 sint_ddr
; /* GPIO + 0x28 */
703 volatile u8 reserved5
[3]; /* GPIO + 0x29 */
704 volatile u8 sint_dvo
; /* GPIO + 0x2c */
705 volatile u8 reserved6
[3]; /* GPIO + 0x2d */
706 volatile u8 sint_inten
; /* GPIO + 0x30 */
707 volatile u8 reserved7
[3]; /* GPIO + 0x31 */
708 volatile u16 sint_itype
; /* GPIO + 0x34 */
709 volatile u16 reserved8
; /* GPIO + 0x36 */
710 volatile u8 gpio_control
; /* GPIO + 0x38 */
711 volatile u8 reserved9
[3]; /* GPIO + 0x39 */
712 volatile u8 sint_istat
; /* GPIO + 0x3c */
713 volatile u8 sint_ival
; /* GPIO + 0x3d */
714 volatile u8 bus_errs
; /* GPIO + 0x3e */
715 volatile u8 reserved10
; /* GPIO + 0x3f */
718 struct mpc5xxx_wu_gpio
{
719 volatile u8 enable
; /* WU_GPIO + 0x00 */
720 volatile u8 reserved1
[3]; /* WU_GPIO + 0x01 */
721 volatile u8 ode
; /* WU_GPIO + 0x04 */
722 volatile u8 reserved2
[3]; /* WU_GPIO + 0x05 */
723 volatile u8 ddr
; /* WU_GPIO + 0x08 */
724 volatile u8 reserved3
[3]; /* WU_GPIO + 0x09 */
725 volatile u8 dvo
; /* WU_GPIO + 0x0c */
726 volatile u8 reserved4
[3]; /* WU_GPIO + 0x0d */
727 volatile u8 inten
; /* WU_GPIO + 0x10 */
728 volatile u8 reserved5
[3]; /* WU_GPIO + 0x11 */
729 volatile u8 iinten
; /* WU_GPIO + 0x14 */
730 volatile u8 reserved6
[3]; /* WU_GPIO + 0x15 */
731 volatile u16 itype
; /* WU_GPIO + 0x18 */
732 volatile u8 reserved7
[2]; /* WU_GPIO + 0x1a */
733 volatile u8 master_enable
; /* WU_GPIO + 0x1c */
734 volatile u8 reserved8
[3]; /* WU_GPIO + 0x1d */
735 volatile u8 ival
; /* WU_GPIO + 0x20 */
736 volatile u8 reserved9
[3]; /* WU_GPIO + 0x21 */
737 volatile u8 status
; /* WU_GPIO + 0x24 */
738 volatile u8 reserved10
[3]; /* WU_GPIO + 0x25 */
741 struct mpc5xxx_sdma
{
742 volatile u32 taskBar
; /* SDMA + 0x00 */
743 volatile u32 currentPointer
; /* SDMA + 0x04 */
744 volatile u32 endPointer
; /* SDMA + 0x08 */
745 volatile u32 variablePointer
; /* SDMA + 0x0c */
747 volatile u8 IntVect1
; /* SDMA + 0x10 */
748 volatile u8 IntVect2
; /* SDMA + 0x11 */
749 volatile u16 PtdCntrl
; /* SDMA + 0x12 */
751 volatile u32 IntPend
; /* SDMA + 0x14 */
752 volatile u32 IntMask
; /* SDMA + 0x18 */
754 volatile u16 tcr_0
; /* SDMA + 0x1c */
755 volatile u16 tcr_1
; /* SDMA + 0x1e */
756 volatile u16 tcr_2
; /* SDMA + 0x20 */
757 volatile u16 tcr_3
; /* SDMA + 0x22 */
758 volatile u16 tcr_4
; /* SDMA + 0x24 */
759 volatile u16 tcr_5
; /* SDMA + 0x26 */
760 volatile u16 tcr_6
; /* SDMA + 0x28 */
761 volatile u16 tcr_7
; /* SDMA + 0x2a */
762 volatile u16 tcr_8
; /* SDMA + 0x2c */
763 volatile u16 tcr_9
; /* SDMA + 0x2e */
764 volatile u16 tcr_a
; /* SDMA + 0x30 */
765 volatile u16 tcr_b
; /* SDMA + 0x32 */
766 volatile u16 tcr_c
; /* SDMA + 0x34 */
767 volatile u16 tcr_d
; /* SDMA + 0x36 */
768 volatile u16 tcr_e
; /* SDMA + 0x38 */
769 volatile u16 tcr_f
; /* SDMA + 0x3a */
771 volatile u8 IPR0
; /* SDMA + 0x3c */
772 volatile u8 IPR1
; /* SDMA + 0x3d */
773 volatile u8 IPR2
; /* SDMA + 0x3e */
774 volatile u8 IPR3
; /* SDMA + 0x3f */
775 volatile u8 IPR4
; /* SDMA + 0x40 */
776 volatile u8 IPR5
; /* SDMA + 0x41 */
777 volatile u8 IPR6
; /* SDMA + 0x42 */
778 volatile u8 IPR7
; /* SDMA + 0x43 */
779 volatile u8 IPR8
; /* SDMA + 0x44 */
780 volatile u8 IPR9
; /* SDMA + 0x45 */
781 volatile u8 IPR10
; /* SDMA + 0x46 */
782 volatile u8 IPR11
; /* SDMA + 0x47 */
783 volatile u8 IPR12
; /* SDMA + 0x48 */
784 volatile u8 IPR13
; /* SDMA + 0x49 */
785 volatile u8 IPR14
; /* SDMA + 0x4a */
786 volatile u8 IPR15
; /* SDMA + 0x4b */
787 volatile u8 IPR16
; /* SDMA + 0x4c */
788 volatile u8 IPR17
; /* SDMA + 0x4d */
789 volatile u8 IPR18
; /* SDMA + 0x4e */
790 volatile u8 IPR19
; /* SDMA + 0x4f */
791 volatile u8 IPR20
; /* SDMA + 0x50 */
792 volatile u8 IPR21
; /* SDMA + 0x51 */
793 volatile u8 IPR22
; /* SDMA + 0x52 */
794 volatile u8 IPR23
; /* SDMA + 0x53 */
795 volatile u8 IPR24
; /* SDMA + 0x54 */
796 volatile u8 IPR25
; /* SDMA + 0x55 */
797 volatile u8 IPR26
; /* SDMA + 0x56 */
798 volatile u8 IPR27
; /* SDMA + 0x57 */
799 volatile u8 IPR28
; /* SDMA + 0x58 */
800 volatile u8 IPR29
; /* SDMA + 0x59 */
801 volatile u8 IPR30
; /* SDMA + 0x5a */
802 volatile u8 IPR31
; /* SDMA + 0x5b */
804 volatile u32 res1
; /* SDMA + 0x5c */
805 volatile u32 res2
; /* SDMA + 0x60 */
806 volatile u32 res3
; /* SDMA + 0x64 */
807 volatile u32 MDEDebug
; /* SDMA + 0x68 */
808 volatile u32 ADSDebug
; /* SDMA + 0x6c */
809 volatile u32 Value1
; /* SDMA + 0x70 */
810 volatile u32 Value2
; /* SDMA + 0x74 */
811 volatile u32 Control
; /* SDMA + 0x78 */
812 volatile u32 Status
; /* SDMA + 0x7c */
813 volatile u32 EU00
; /* SDMA + 0x80 */
814 volatile u32 EU01
; /* SDMA + 0x84 */
815 volatile u32 EU02
; /* SDMA + 0x88 */
816 volatile u32 EU03
; /* SDMA + 0x8c */
817 volatile u32 EU04
; /* SDMA + 0x90 */
818 volatile u32 EU05
; /* SDMA + 0x94 */
819 volatile u32 EU06
; /* SDMA + 0x98 */
820 volatile u32 EU07
; /* SDMA + 0x9c */
821 volatile u32 EU10
; /* SDMA + 0xa0 */
822 volatile u32 EU11
; /* SDMA + 0xa4 */
823 volatile u32 EU12
; /* SDMA + 0xa8 */
824 volatile u32 EU13
; /* SDMA + 0xac */
825 volatile u32 EU14
; /* SDMA + 0xb0 */
826 volatile u32 EU15
; /* SDMA + 0xb4 */
827 volatile u32 EU16
; /* SDMA + 0xb8 */
828 volatile u32 EU17
; /* SDMA + 0xbc */
829 volatile u32 EU20
; /* SDMA + 0xc0 */
830 volatile u32 EU21
; /* SDMA + 0xc4 */
831 volatile u32 EU22
; /* SDMA + 0xc8 */
832 volatile u32 EU23
; /* SDMA + 0xcc */
833 volatile u32 EU24
; /* SDMA + 0xd0 */
834 volatile u32 EU25
; /* SDMA + 0xd4 */
835 volatile u32 EU26
; /* SDMA + 0xd8 */
836 volatile u32 EU27
; /* SDMA + 0xdc */
837 volatile u32 EU30
; /* SDMA + 0xe0 */
838 volatile u32 EU31
; /* SDMA + 0xe4 */
839 volatile u32 EU32
; /* SDMA + 0xe8 */
840 volatile u32 EU33
; /* SDMA + 0xec */
841 volatile u32 EU34
; /* SDMA + 0xf0 */
842 volatile u32 EU35
; /* SDMA + 0xf4 */
843 volatile u32 EU36
; /* SDMA + 0xf8 */
844 volatile u32 EU37
; /* SDMA + 0xfc */
848 volatile u32 madr
; /* I2Cn + 0x00 */
849 volatile u32 mfdr
; /* I2Cn + 0x04 */
850 volatile u32 mcr
; /* I2Cn + 0x08 */
851 volatile u32 msr
; /* I2Cn + 0x0C */
852 volatile u32 mdr
; /* I2Cn + 0x10 */
856 volatile u8 cr1
; /* SPI + 0x0F00 */
857 volatile u8 cr2
; /* SPI + 0x0F01 */
858 volatile u8 reserved1
[2];
859 volatile u8 brr
; /* SPI + 0x0F04 */
860 volatile u8 sr
; /* SPI + 0x0F05 */
861 volatile u8 reserved2
[3];
862 volatile u8 dr
; /* SPI + 0x0F09 */
863 volatile u8 reserved3
[3];
864 volatile u8 pdr
; /* SPI + 0x0F0D */
865 volatile u8 reserved4
[2];
866 volatile u8 ddr
; /* SPI + 0x0F10 */
871 volatile u32 emsr
; /* GPT + Timer# * 0x10 + 0x00 */
872 volatile u32 cir
; /* GPT + Timer# * 0x10 + 0x04 */
873 volatile u32 pwmcr
; /* GPT + Timer# * 0x10 + 0x08 */
874 volatile u32 sr
; /* GPT + Timer# * 0x10 + 0x0c */
877 struct mpc5xxx_gpt_0_7
{
878 struct mpc5xxx_gpt gpt0
;
879 struct mpc5xxx_gpt gpt1
;
880 struct mpc5xxx_gpt gpt2
;
881 struct mpc5xxx_gpt gpt3
;
882 struct mpc5xxx_gpt gpt4
;
883 struct mpc5xxx_gpt gpt5
;
884 struct mpc5xxx_gpt gpt6
;
885 struct mpc5xxx_gpt gpt7
;
888 struct mscan_buffer
{
889 volatile u8 idr
[0x8]; /* 0x00 */
890 volatile u8 dsr
[0x10]; /* 0x08 */
891 volatile u8 dlr
; /* 0x18 */
892 volatile u8 tbpr
; /* 0x19 */ /* This register is not applicable for receive buffers */
893 volatile u16 rsrv1
; /* 0x1A */
894 volatile u8 tsrh
; /* 0x1C */
895 volatile u8 tsrl
; /* 0x1D */
896 volatile u16 rsrv2
; /* 0x1E */
899 struct mpc5xxx_mscan
{
900 volatile u8 canctl0
; /* MSCAN + 0x00 */
901 volatile u8 canctl1
; /* MSCAN + 0x01 */
902 volatile u16 rsrv1
; /* MSCAN + 0x02 */
903 volatile u8 canbtr0
; /* MSCAN + 0x04 */
904 volatile u8 canbtr1
; /* MSCAN + 0x05 */
905 volatile u16 rsrv2
; /* MSCAN + 0x06 */
906 volatile u8 canrflg
; /* MSCAN + 0x08 */
907 volatile u8 canrier
; /* MSCAN + 0x09 */
908 volatile u16 rsrv3
; /* MSCAN + 0x0A */
909 volatile u8 cantflg
; /* MSCAN + 0x0C */
910 volatile u8 cantier
; /* MSCAN + 0x0D */
911 volatile u16 rsrv4
; /* MSCAN + 0x0E */
912 volatile u8 cantarq
; /* MSCAN + 0x10 */
913 volatile u8 cantaak
; /* MSCAN + 0x11 */
914 volatile u16 rsrv5
; /* MSCAN + 0x12 */
915 volatile u8 cantbsel
; /* MSCAN + 0x14 */
916 volatile u8 canidac
; /* MSCAN + 0x15 */
917 volatile u16 rsrv6
[3]; /* MSCAN + 0x16 */
918 volatile u8 canrxerr
; /* MSCAN + 0x1C */
919 volatile u8 cantxerr
; /* MSCAN + 0x1D */
920 volatile u16 rsrv7
; /* MSCAN + 0x1E */
921 volatile u8 canidar0
; /* MSCAN + 0x20 */
922 volatile u8 canidar1
; /* MSCAN + 0x21 */
923 volatile u16 rsrv8
; /* MSCAN + 0x22 */
924 volatile u8 canidar2
; /* MSCAN + 0x24 */
925 volatile u8 canidar3
; /* MSCAN + 0x25 */
926 volatile u16 rsrv9
; /* MSCAN + 0x26 */
927 volatile u8 canidmr0
; /* MSCAN + 0x28 */
928 volatile u8 canidmr1
; /* MSCAN + 0x29 */
929 volatile u16 rsrv10
; /* MSCAN + 0x2A */
930 volatile u8 canidmr2
; /* MSCAN + 0x2C */
931 volatile u8 canidmr3
; /* MSCAN + 0x2D */
932 volatile u16 rsrv11
; /* MSCAN + 0x2E */
933 volatile u8 canidar4
; /* MSCAN + 0x30 */
934 volatile u8 canidar5
; /* MSCAN + 0x31 */
935 volatile u16 rsrv12
; /* MSCAN + 0x32 */
936 volatile u8 canidar6
; /* MSCAN + 0x34 */
937 volatile u8 canidar7
; /* MSCAN + 0x35 */
938 volatile u16 rsrv13
; /* MSCAN + 0x36 */
939 volatile u8 canidmr4
; /* MSCAN + 0x38 */
940 volatile u8 canidmr5
; /* MSCAN + 0x39 */
941 volatile u16 rsrv14
; /* MSCAN + 0x3A */
942 volatile u8 canidmr6
; /* MSCAN + 0x3C */
943 volatile u8 canidmr7
; /* MSCAN + 0x3D */
944 volatile u16 rsrv15
; /* MSCAN + 0x3E */
946 struct mscan_buffer canrxfg
; /* MSCAN + 0x40 */ /* Foreground receive buffer */
947 struct mscan_buffer cantxfg
; /* MSCAN + 0x60 */ /* Foreground transmit buffer */
950 /* function prototypes */
951 void loadtask(int basetask
, int tasks
);
953 #endif /* __ASSEMBLY__ */
955 #endif /* __ASMPPC_MPC5XXX_H */