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1 /*
2 * (C) Copyright 2000, 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 /*
25 * mpc8260.h
26 *
27 * MPC8255 / MPC8260 specific definitions
28 */
29
30 #ifndef __MPC8260_H__
31 #define __MPC8260_H__
32
33 #ifdef CONFIG_MPC8255
34 #define CPU_ID_STR "MPC8255"
35 #endif
36 #ifndef CPU_ID_STR
37 #if defined(CONFIG_MPC8272_FAMILY)
38 #define CPU_ID_STR "MPC8272"
39 #else
40 #define CPU_ID_STR "MPC8260"
41 #endif
42 #endif /* !CPU_ID_STR */
43
44 /*-----------------------------------------------------------------------
45 * Exception offsets (PowerPC standard)
46 */
47 #define EXC_OFF_SYS_RESET 0x0100 /* System reset */
48
49
50 /*-----------------------------------------------------------------------
51 * BCR - Bus Configuration Register 4-25
52 */
53 #define BCR_EBM 0x80000000 /* External Bus Mode */
54 #define BCR_APD_MSK 0x70000000 /* Address Phase Delay Mask */
55 #define BCR_L2C 0x08000000 /* Secondary Cache Controller */
56 #define BCR_L2D_MSK 0x07000000 /* L2 Cache Hit Delay Mask */
57 #define BCR_PLDP 0x00800000 /* Pipeline Maximum Depth */
58 #define BCR_EAV 0x00400000 /* Enable Address Visibility */
59 #define BCR_ETM 0x00080000 /* Compatibility Mode Enable */
60 #define BCR_LETM 0x00040000 /* LocalBus Compatibility Mode Enable*/
61 #define BCR_EPAR 0x00020000 /* Even Parity */
62 #define BCR_LEPAR 0x00010000 /* Local Bus Even Parity */
63 #define BCR_NPQM0 0x00008000 /* Non PowerQUICC-II Master 0 */
64 #define BCR_NPQM1 0x00004000 /* Non PowerQUICC-II Master 1 */
65 #define BCR_NPQM2 0x00002000 /* Non PowerQUICC-II Master 2 */
66 #define BCR_EXDD 0x00000400 /* External Master Delay Disable*/
67 #define BCR_ISPS 0x00000010 /* Internal Space Port Size */
68
69 /*-----------------------------------------------------------------------
70 * PPC_ACR - 60x Bus Arbiter Configuration Register 4-28
71 */
72 #define PPC_ACR_DBGD 0x20 /* Data Bus Grant Delay */
73 #define PPC_ACR_EARB 0x10 /* External Arbitration */
74 #define PPC_ACR_PRKM_MSK 0x0f /* Parking Master */
75
76 #define PPC_ACR_PRKM_CPMH 0x00 /* CPM high request level */
77 #define PPC_ACR_PRKM_CPMM 0x01 /* CPM middle request level */
78 #define PPC_ACR_PRKM_CPML 0x02 /* CPM low request level */
79 #define PPC_ACR_PRKM_CORE 0x06 /* Internal Core */
80 #define PPC_ACR_PRKM_EXT1 0x07 /* External Master 1 */
81 #define PPC_ACR_PRKM_EXT2 0x08 /* External Master 2 */
82 #define PPC_ACR_PRKM_EXT3 0x09 /* External Master 3 */
83
84 /*-----------------------------------------------------------------------
85 * PPC_ALRH/PPC_ALRL - 60x Bus Arbitration-Level Registers 4-28
86 */
87 #define PPC_ALRH_PF0_MSK 0xf0000000 /* Priority Field 0 Mask */
88 #define PPC_ALRH_PF1_MSK 0x0f000000 /* Priority Field 1 Mask */
89 #define PPC_ALRH_PF2_MSK 0x00f00000 /* Priority Field 2 Mask */
90 #define PPC_ALRH_PF3_MSK 0x000f0000 /* Priority Field 3 Mask */
91 #define PPC_ALRH_PF4_MSK 0x0000f000 /* Priority Field 4 Mask */
92 #define PPC_ALRH_PF5_MSK 0x00000f00 /* Priority Field 5 Mask */
93 #define PPC_ALRH_PF6_MSK 0x000000f0 /* Priority Field 6 Mask */
94 #define PPC_ALRH_PF7_MSK 0x0000000f /* Priority Field 7 Mask */
95 #define PPC_ALRL_PF8_MSK 0xf0000000 /* Priority Field 8 Mask */
96 #define PPC_ALRL_PF9_MSK 0x0f000000 /* Priority Field 9 Mask */
97 #define PPC_ALRL_PF10_MSK 0x00f00000 /* Priority Field 10 Mask */
98 #define PPC_ALRL_PF11_MSK 0x000f0000 /* Priority Field 11 Mask */
99 #define PPC_ALRL_PF12_MSK 0x0000f000 /* Priority Field 12 Mask */
100 #define PPC_ALRL_PF13_MSK 0x00000f00 /* Priority Field 13 Mask */
101 #define PPC_ALRL_PF14_MSK 0x000000f0 /* Priority Field 14 Mask */
102 #define PPC_ALRL_PF15_MSK 0x0000000f /* Priority Field 15 Mask */
103
104 /*-----------------------------------------------------------------------
105 * LCL_ACR - Local Bus Arbiter Configuration Register 4-29
106 */
107 #define LCL_ACR_DBGD 0x20 /* Data Bus Grant Delay */
108 #define LCL_ACR_PRKM_MSK 0x0f /* Parking Master */
109
110 #define LCL_ACR_PRKM_CPMH 0x00 /* CPM high request level */
111 #define LCL_ACR_PRKM_CPMM 0x01 /* CPM middle request level */
112 #define LCL_ACR_PRKM_CPML 0x02 /* CPM low request level */
113 #define LCL_ACR_PRKM_HOST 0x03 /* Host Bridge */
114
115 /*-----------------------------------------------------------------------
116 * LCL_ALRH/LCL_ALRL - Local Bus Arbitration Level Registers 4-30
117 */
118 #define LCL_ALRH_PF0_MSK 0xf0000000 /* Priority Field 0 Mask */
119 #define LCL_ALRH_PF1_MSK 0x0f000000 /* Priority Field 1 Mask */
120 #define LCL_ALRH_PF2_MSK 0x00f00000 /* Priority Field 2 Mask */
121 #define LCL_ALRH_PF3_MSK 0x000f0000 /* Priority Field 3 Mask */
122 #define LCL_ALRH_PF4_MSK 0x0000f000 /* Priority Field 4 Mask */
123 #define LCL_ALRH_PF5_MSK 0x00000f00 /* Priority Field 5 Mask */
124 #define LCL_ALRH_PF6_MSK 0x000000f0 /* Priority Field 6 Mask */
125 #define LCL_ALRH_PF7_MSK 0x0000000f /* Priority Field 7 Mask */
126 #define LCL_ALRL_PF8_MSK 0xf0000000 /* Priority Field 8 Mask */
127 #define LCL_ALRL_PF9_MSK 0x0f000000 /* Priority Field 9 Mask */
128 #define LCL_ALRL_PF10_MSK 0x00f00000 /* Priority Field 10 Mask */
129 #define LCL_ALRL_PF11_MSK 0x000f0000 /* Priority Field 11 Mask */
130 #define LCL_ALRL_PF12_MSK 0x0000f000 /* Priority Field 12 Mask */
131 #define LCL_ALRL_PF13_MSK 0x00000f00 /* Priority Field 13 Mask */
132 #define LCL_ALRL_PF14_MSK 0x000000f0 /* Priority Field 14 Mask */
133 #define LCL_ALRL_PF15_MSK 0x0000000f /* Priority Field 15 Mask */
134
135 /*-----------------------------------------------------------------------
136 * SIUMCR - SIU Module Configuration Register 4-31
137 */
138 #define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */
139 #define SIUMCR_ESE 0x40000000 /* External Snoop Enable */
140 #define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */
141 #define SIUMCR_CDIS 0x10000000 /* Core Disable */
142 #define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/
143 #define SIUMCR_DPPC01 0x04000000 /* - " - */
144 #define SIUMCR_DPPC10 0x08000000 /* - " - */
145 #define SIUMCR_DPPC11 0x0c000000 /* - " - */
146 #define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */
147 #define SIUMCR_L2CPC01 0x01000000 /* - " - */
148 #define SIUMCR_L2CPC10 0x02000000 /* - " - */
149 #define SIUMCR_L2CPC11 0x03000000 /* - " - */
150 #define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */
151 #define SIUMCR_LBPC01 0x00400000 /* - " - */
152 #define SIUMCR_LBPC10 0x00800000 /* - " - */
153 #define SIUMCR_LBPC11 0x00c00000 /* - " - */
154 #define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/
155 #define SIUMCR_APPC01 0x00100000 /* - " - */
156 #define SIUMCR_APPC10 0x00200000 /* - " - */
157 #define SIUMCR_APPC11 0x00300000 /* - " - */
158 #define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */
159 #define SIUMCR_CS10PC01 0x00040000 /* - " - */
160 #define SIUMCR_CS10PC10 0x00080000 /* - " - */
161 #define SIUMCR_CS10PC11 0x000c0000 /* - " - */
162 #define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */
163 #define SIUMCR_BCTLC01 0x00010000 /* - " - */
164 #define SIUMCR_BCTLC10 0x00020000 /* - " - */
165 #define SIUMCR_BCTLC11 0x00030000 /* - " - */
166 #define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */
167 #define SIUMCR_MMR01 0x00004000 /* - " - */
168 #define SIUMCR_MMR10 0x00008000 /* - " - */
169 #define SIUMCR_MMR11 0x0000c000 /* - " - */
170 #define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/
171
172 /*-----------------------------------------------------------------------
173 * IMMR - Internal Memory Map Register 4-34
174 */
175 #define IMMR_ISB_MSK 0xfffe0000 /* Internal Space base */
176 #define IMMR_PARTNUM_MSK 0x0000ff00 /* Part number */
177 #define IMMR_MASKNUM_MSK 0x000000ff /* Mask number */
178
179 /*-----------------------------------------------------------------------
180 * SYPCR - System Protection Control Register 4-35
181 */
182 #define SYPCR_SWTC 0xffff0000 /* Software Watchdog Timer Count*/
183 #define SYPCR_BMT 0x0000ff00 /* Bus Monitor Timing */
184 #define SYPCR_PBME 0x00000080 /* 60x Bus Monitor Enable */
185 #define SYPCR_LBME 0x00000040 /* Local Bus Monitor Enable */
186 #define SYPCR_SWE 0x00000004 /* Software Watchdog Enable */
187 #define SYPCR_SWRI 0x00000002 /* Software Watchdog Reset/Int Select*/
188 #define SYPCR_SWP 0x00000001 /* Software Watchdog Prescale */
189
190 /*-----------------------------------------------------------------------
191 * TMCNTSC - Time Counter Status and Control Register 4-40
192 */
193 #define TMCNTSC_SEC 0x0080 /* Once Per Second Interrupt */
194 #define TMCNTSC_ALR 0x0040 /* Alarm Interrupt */
195 #define TMCNTSC_SIE 0x0008 /* Second Interrupt Enable */
196 #define TMCNTSC_ALE 0x0004 /* Alarm Interrupt Enable */
197 #define TMCNTSC_TCF 0x0002 /* Time Counter Frequency */
198 #define TMCNTSC_TCE 0x0001 /* Time Counter Enable */
199
200 /*-----------------------------------------------------------------------
201 * PISCR - Periodic Interrupt Status and Control Register 4-42
202 */
203 #if 0 /* already defined in asm/immap_8260.h */
204 #define PISCR_PS 0x0080 /* Periodic Interrupt Status */
205 #define PISCR_PIE 0x0004 /* Periodic Interrupt Enable */
206 #define PISCR_PTF 0x0002 /* Periodic Timer Frequency */
207 #define PISCR_PTE 0x0001 /* Periodic Timer Enable */
208 #endif
209
210 /*-----------------------------------------------------------------------
211 * RSR - Reset Status Register 5-4
212 */
213 #define RSR_JTRS 0x00000020 /* JTAG Reset Status */
214 #define RSR_CSRS 0x00000010 /* Check Stop Reset Status */
215 #define RSR_SWRS 0x00000008 /* Software Watchdog Reset Status*/
216 #define RSR_BMRS 0x00000004 /* Bus Monitor Reset Status */
217 #define RSR_ESRS 0x00000002 /* External Soft Reset Status */
218 #define RSR_EHRS 0x00000001 /* External Hard Reset Status */
219
220 #define RSR_ALLBITS (RSR_JTRS|RSR_CSRS|RSR_SWRS|RSR_BMRS|RSR_ESRS|RSR_EHRS)
221
222 /*-----------------------------------------------------------------------
223 * RMR - Reset Mode Register 5-5
224 */
225 #define RMR_CSRE 0x00000001 /* Checkstop Reset Enable */
226
227 /*-----------------------------------------------------------------------
228 * Hard Reset Configuration Word 5-8
229 */
230 #define HRCW_EARB 0x80000000 /* External Arbitration */
231 #define HRCW_EXMC 0x40000000 /* External Memory Controller */
232 #define HRCW_CDIS 0x20000000 /* Core Disable */
233 #define HRCW_EBM 0x10000000 /* External Bus Mode */
234 #define HRCW_BPS00 0x00000000 /* Boot Port Size */
235 #define HRCW_BPS01 0x04000000 /* - " - */
236 #define HRCW_BPS10 0x08000000 /* - " - */
237 #define HRCW_BPS11 0x0c000000 /* - " - */
238 #define HRCW_CIP 0x02000000 /* Core Initial Prefix */
239 #define HRCW_ISPS 0x01000000 /* Internal Space Port Size */
240 #define HRCW_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */
241 #define HRCW_L2CPC01 0x00400000 /* - " - */
242 #define HRCW_L2CPC10 0x00800000 /* - " - */
243 #define HRCW_L2CPC11 0x00c00000 /* - " - */
244 #define HRCW_DPPC00 0x00000000 /* Data Parity Pin Configuration*/
245 #define HRCW_DPPC01 0x00100000 /* - " - */
246 #define HRCW_DPPC10 0x00200000 /* - " - */
247 #define HRCW_DPPC11 0x00300000 /* - " - */
248 #define HRCW_reserved1 0x00080000 /* reserved */
249 #define HRCW_ISB000 0x00000000 /* Initial Internal Space Base */
250 #define HRCW_ISB001 0x00010000 /* - " - */
251 #define HRCW_ISB010 0x00020000 /* - " - */
252 #define HRCW_ISB011 0x00030000 /* - " - */
253 #define HRCW_ISB100 0x00040000 /* - " - */
254 #define HRCW_ISB101 0x00050000 /* - " - */
255 #define HRCW_ISB110 0x00060000 /* - " - */
256 #define HRCW_ISB111 0x00070000 /* - " - */
257 #define HRCW_BMS 0x00008000 /* Boot Memory Space */
258 #define HRCW_BBD 0x00004000 /* Bus Busy Disable */
259 #define HRCW_MMR00 0x00000000 /* Mask Masters Requests */
260 #define HRCW_MMR01 0x00001000 /* - " - */
261 #define HRCW_MMR10 0x00002000 /* - " - */
262 #define HRCW_MMR11 0x00003000 /* - " - */
263 #define HRCW_LBPC00 0x00000000 /* Local Bus Pin Configuration */
264 #define HRCW_LBPC01 0x00000400 /* - " - */
265 #define HRCW_LBPC10 0x00000800 /* - " - */
266 #define HRCW_LBPC11 0x00000c00 /* - " - */
267 #define HRCW_APPC00 0x00000000 /* Address Parity Pin Configuration*/
268 #define HRCW_APPC01 0x00000100 /* - " - */
269 #define HRCW_APPC10 0x00000200 /* - " - */
270 #define HRCW_APPC11 0x00000300 /* - " - */
271 #define HRCW_CS10PC00 0x00000000 /* CS10 Pin Configuration */
272 #define HRCW_CS10PC01 0x00000040 /* - " - */
273 #define HRCW_CS10PC10 0x00000080 /* - " - */
274 #define HRCW_CS10PC11 0x000000c0 /* - " - */
275 #define HRCW_MODCK_H0000 0x00000000 /* High-order bits of MODCK Bus */
276 #define HRCW_MODCK_H0001 0x00000001 /* - " - */
277 #define HRCW_MODCK_H0010 0x00000002 /* - " - */
278 #define HRCW_MODCK_H0011 0x00000003 /* - " - */
279 #define HRCW_MODCK_H0100 0x00000004 /* - " - */
280 #define HRCW_MODCK_H0101 0x00000005 /* - " - */
281 #define HRCW_MODCK_H0110 0x00000006 /* - " - */
282 #define HRCW_MODCK_H0111 0x00000007 /* - " - */
283 #define HRCW_MODCK_H1000 0x00000008 /* - " - */
284 #define HRCW_MODCK_H1001 0x00000009 /* - " - */
285 #define HRCW_MODCK_H1010 0x0000000a /* - " - */
286 #define HRCW_MODCK_H1011 0x0000000b /* - " - */
287 #define HRCW_MODCK_H1100 0x0000000c /* - " - */
288 #define HRCW_MODCK_H1101 0x0000000d /* - " - */
289 #define HRCW_MODCK_H1110 0x0000000e /* - " - */
290 #define HRCW_MODCK_H1111 0x0000000f /* - " - */
291
292 /*-----------------------------------------------------------------------
293 * SCCR - System Clock Control Register 9-8
294 */
295 #define SCCR_PCI_MODE 0x00000100 /* PCI Mode */
296 #define SCCR_PCI_MODCK 0x00000080 /* Value of PCI_MODCK pin */
297 #define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */
298 #define SCCR_PCIDF_SHIFT 3
299 #define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */
300 #define SCCR_DFBRG_MSK 0x00000003 /* Division factor of BRGCLK Mask */
301 #define SCCR_DFBRG_SHIFT 0
302
303 #define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */
304 #define SCCR_DFBRG01 0x00000001 /* BRGCLK division by 16 (normal op.)*/
305 #define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */
306 #define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 128 */
307
308 /*-----------------------------------------------------------------------
309 * SCMR - System Clock Mode Register 9-9
310 */
311 #define SCMR_CORECNF_MSK 0x1f000000 /* Core Configuration Mask */
312 #define SCMR_CORECNF_SHIFT 24
313 #define SCMR_BUSDF_MSK 0x00f00000 /* 60x Bus Division Factor Mask */
314 #define SCMR_BUSDF_SHIFT 20
315 #define SCMR_CPMDF_MSK 0x000f0000 /* CPM Division Factor Mask */
316 #define SCMR_CPMDF_SHIFT 16
317 #define SCMR_PLLDF 0x00001000 /* PLL Pre-divider Value */
318 #define SCMR_PLLMF_MSK 0x00000fff /* PLL Multiplication Factor Mask*/
319 #define SCMR_PLLMF_MSKH7 0x0000000f /* for HiP7 processors */
320 #define SCMR_PLLMF_SHIFT 0
321
322
323 /*-----------------------------------------------------------------------
324 * MxMR - Machine A/B/C Mode Registers 10-13
325 */
326 #define MxMR_BSEL 0x80000000 /* Bus Select */
327 #define MxMR_RFEN 0x40000000 /* Refresh Enable */
328 #define MxMR_OP_MSK 0x30000000 /* Command Opcode Mask */
329 #define MxMR_AMx_MSK 0x07000000 /* Addess Multiplex Size Mask */
330 #define MxMR_DSx_MSK 0x00c00000 /* Disable Timer Period Mask */
331 #define MxMR_G0CLx_MSK 0x00380000 /* General Line 0 Control Mask */
332 #define MxMR_GPL_x4DIS 0x00040000 /* GPL_A4 Ouput Line Disable */
333 #define MxMR_RLFx_MSK 0x0003c000 /* Read Loop Field Mask */
334 #define MxMR_WLFx_MSK 0x00003c00 /* Write Loop Field Mask */
335 #define MxMR_TLFx_MSK 0x000003c0 /* Refresh Loop Field Mask */
336 #define MxMR_MAD_MSK 0x0000003f /* Machine Address Mask */
337
338 #define MxMR_OP_NORM 0x00000000 /* Normal Operation */
339 #define MxMR_OP_WARR 0x10000000 /* Write to Array */
340 #define MxMR_OP_RARR 0x20000000 /* Read from Array */
341 #define MxMR_OP_RUNP 0x30000000 /* Run Pattern */
342
343 #define MxMR_AMx_TYPE_0 0x00000000 /* Addess Multiplexing Type 0 */
344 #define MxMR_AMx_TYPE_1 0x01000000 /* Addess Multiplexing Type 1 */
345 #define MxMR_AMx_TYPE_2 0x02000000 /* Addess Multiplexing Type 2 */
346 #define MxMR_AMx_TYPE_3 0x03000000 /* Addess Multiplexing Type 3 */
347 #define MxMR_AMx_TYPE_4 0x04000000 /* Addess Multiplexing Type 4 */
348 #define MxMR_AMx_TYPE_5 0x05000000 /* Addess Multiplexing Type 5 */
349
350 #define MxMR_DSx_1_CYCL 0x00000000 /* 1 cycle Disable Period */
351 #define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */
352 #define MxMR_DSx_3_CYCL 0x00800000 /* 3 cycle Disable Period */
353 #define MxMR_DSx_4_CYCL 0x00c00000 /* 4 cycle Disable Period */
354
355 #define MxMR_G0CLx_A12 0x00000000 /* General Line 0 : A12 */
356 #define MxMR_G0CLx_A11 0x00080000 /* General Line 0 : A11 */
357 #define MxMR_G0CLx_A10 0x00100000 /* General Line 0 : A10 */
358 #define MxMR_G0CLx_A9 0x00180000 /* General Line 0 : A9 */
359 #define MxMR_G0CLx_A8 0x00200000 /* General Line 0 : A8 */
360 #define MxMR_G0CLx_A7 0x00280000 /* General Line 0 : A7 */
361 #define MxMR_G0CLx_A6 0x00300000 /* General Line 0 : A6 */
362 #define MxMR_G0CLx_A5 0x00380000 /* General Line 0 : A5 */
363
364 #define MxMR_RLFx_1X 0x00004000 /* Read Loop is executed 1 time */
365 #define MxMR_RLFx_2X 0x00008000 /* Read Loop is executed 2 times*/
366 #define MxMR_RLFx_3X 0x0000c000 /* Read Loop is executed 3 times*/
367 #define MxMR_RLFx_4X 0x00010000 /* Read Loop is executed 4 times*/
368 #define MxMR_RLFx_5X 0x00014000 /* Read Loop is executed 5 times*/
369 #define MxMR_RLFx_6X 0x00018000 /* Read Loop is executed 6 times*/
370 #define MxMR_RLFx_7X 0x0001c000 /* Read Loop is executed 7 times*/
371 #define MxMR_RLFx_8X 0x00020000 /* Read Loop is executed 8 times*/
372 #define MxMR_RLFx_9X 0x00024000 /* Read Loop is executed 9 times*/
373 #define MxMR_RLFx_10X 0x00028000 /* Read Loop is executed 10 times*/
374 #define MxMR_RLFx_11X 0x0002c000 /* Read Loop is executed 11 times*/
375 #define MxMR_RLFx_12X 0x00030000 /* Read Loop is executed 12 times*/
376 #define MxMR_RLFx_13X 0x00034000 /* Read Loop is executed 13 times*/
377 #define MxMR_RLFx_14X 0x00038000 /* Read Loop is executed 14 times*/
378 #define MxMR_RLFx_15X 0x0003c000 /* Read Loop is executed 15 times*/
379 #define MxMR_RLFx_16X 0x00000000 /* Read Loop is executed 16 times*/
380
381 #define MxMR_WLFx_1X 0x00000400 /* Write Loop is executed 1 time*/
382 #define MxMR_WLFx_2X 0x00000800 /* Write Loop is executed 2 times*/
383 #define MxMR_WLFx_3X 0x00000c00 /* Write Loop is executed 3 times*/
384 #define MxMR_WLFx_4X 0x00001000 /* Write Loop is executed 4 times*/
385 #define MxMR_WLFx_5X 0x00001400 /* Write Loop is executed 5 times*/
386 #define MxMR_WLFx_6X 0x00001800 /* Write Loop is executed 6 times*/
387 #define MxMR_WLFx_7X 0x00001c00 /* Write Loop is executed 7 times*/
388 #define MxMR_WLFx_8X 0x00002000 /* Write Loop is executed 8 times*/
389 #define MxMR_WLFx_9X 0x00002400 /* Write Loop is executed 9 times*/
390 #define MxMR_WLFx_10X 0x00002800 /* Write Loop is executed 10 times*/
391 #define MxMR_WLFx_11X 0x00002c00 /* Write Loop is executed 11 times*/
392 #define MxMR_WLFx_12X 0x00003000 /* Write Loop is executed 12 times*/
393 #define MxMR_WLFx_13X 0x00003400 /* Write Loop is executed 13 times*/
394 #define MxMR_WLFx_14X 0x00003800 /* Write Loop is executed 14 times*/
395 #define MxMR_WLFx_15X 0x00003c00 /* Write Loop is executed 15 times*/
396 #define MxMR_WLFx_16X 0x00000000 /* Write Loop is executed 16 times*/
397
398 #define MxMR_TLFx_1X 0x00000040 /* Timer Loop is executed 1 time*/
399 #define MxMR_TLFx_2X 0x00000080 /* Timer Loop is executed 2 times*/
400 #define MxMR_TLFx_3X 0x000000c0 /* Timer Loop is executed 3 times*/
401 #define MxMR_TLFx_4X 0x00000100 /* Timer Loop is executed 4 times*/
402 #define MxMR_TLFx_5X 0x00000140 /* Timer Loop is executed 5 times*/
403 #define MxMR_TLFx_6X 0x00000180 /* Timer Loop is executed 6 times*/
404 #define MxMR_TLFx_7X 0x000001c0 /* Timer Loop is executed 7 times*/
405 #define MxMR_TLFx_8X 0x00000200 /* Timer Loop is executed 8 times*/
406 #define MxMR_TLFx_9X 0x00000240 /* Timer Loop is executed 9 times*/
407 #define MxMR_TLFx_10X 0x00000280 /* Timer Loop is executed 10 times*/
408 #define MxMR_TLFx_11X 0x000002c0 /* Timer Loop is executed 11 times*/
409 #define MxMR_TLFx_12X 0x00000300 /* Timer Loop is executed 12 times*/
410 #define MxMR_TLFx_13X 0x00000340 /* Timer Loop is executed 13 times*/
411 #define MxMR_TLFx_14X 0x00000380 /* Timer Loop is executed 14 times*/
412 #define MxMR_TLFx_15X 0x000003c0 /* Timer Loop is executed 15 times*/
413 #define MxMR_TLFx_16X 0x00000000 /* Timer Loop is executed 16 times*/
414
415
416 /*-----------------------------------------------------------------------
417 * BRx - Memory Controller: Base Register 10-14
418 */
419 #define BRx_BA_MSK 0xffff8000 /* Base Address Mask */
420 #define BRx_PS_MSK 0x00001800 /* Port Size Mask */
421 #define BRx_DECC_MSK 0x00000600 /* Data Error Correct+Check Mask*/
422 #define BRx_WP 0x00000100 /* Write Protect */
423 #define BRx_MS_MSK 0x000000e0 /* Machine Select Mask */
424 #define BRx_EMEMC 0x00000010 /* External MEMC Enable */
425 #define BRx_ATOM_MSK 0x0000000c /* Atomic Operation Mask */
426 #define BRx_DR 0x00000002 /* Data Pipelining */
427 #define BRx_V 0x00000001 /* Bank Valid */
428
429 #define BRx_PS_64 0x00000000 /* 64 bit port size (60x bus only)*/
430 #define BRx_PS_8 0x00000800 /* 8 bit port size */
431 #define BRx_PS_16 0x00001000 /* 16 bit port size */
432 #define BRx_PS_32 0x00001800 /* 32 bit port size */
433
434 #define BRx_DECC_NONE 0x00000000 /* Data Errors Checking Disabled*/
435 #define BRx_DECC_NORMAL 0x00000200 /* Normal Parity Checking */
436 #define BRx_DECC_RMWPC 0x00000400 /* Read-Modify-Write Parity Checking*/
437 #define BRx_DECC_ECC 0x00000600 /* ECC Correction and Checking */
438
439 #define BRx_MS_GPCM_P 0x00000000 /* G.P.C.M. 60x Bus Machine Select*/
440 #define BRx_MS_GPCM_L 0x00000020 /* G.P.C.M. Local Bus Machine Select*/
441 #define BRx_MS_SDRAM_P 0x00000040 /* SDRAM 60x Bus Machine Select */
442 #define BRx_MS_SDRAM_L 0x00000060 /* SDRAM Local Bus Machine Select*/
443 #define BRx_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */
444 #define BRx_MS_UPMB 0x000000a0 /* U.P.M.B Machine Select */
445 #define BRx_MS_UPMC 0x000000c0 /* U.P.M.C Machine Select */
446
447 #define BRx_ATOM_RAWA 0x00000004 /* Read-After-Write-Atomic */
448 #define BRx_ATOM_WARA 0x00000008 /* Write-After-Read-Atomic */
449
450 /*-----------------------------------------------------------------------
451 * ORx - Memory Controller: Option Register - SDRAM Mode 10-16
452 */
453 #define ORxS_SDAM_MSK 0xfff00000 /* SDRAM Address Mask Mask */
454 #define ORxS_LSDAM_MSK 0x000f8000 /* Lower SDRAM Address Mask Mask*/
455 #define ORxS_BPD_MSK 0x00006000 /* Banks Per Device Mask */
456 #define ORxS_ROWST_MSK 0x00001e00 /* Row Start Address Bit Mask */
457 #define ORxS_NUMR_MSK 0x000001c0 /* Number of Row Addr Lines Mask*/
458 #define ORxS_PMSEL 0x00000020 /* Page Mode Select */
459 #define ORxS_IBID 0x00000010 /* Internal Bank Interleaving Disable*/
460
461 #define ORxS_BPD_2 0x00000000 /* 2 Banks Per Device */
462 #define ORxS_BPD_4 0x00002000 /* 4 Banks Per Device */
463 #define ORxS_BPD_8 0x00004000 /* 8 Banks Per Device */
464
465 /* ROWST values for xSDMR[PBI] = 0 */
466 #define ORxS_ROWST_PBI0_A7 0x00000400 /* Row Start Address Bit is A7 */
467 #define ORxS_ROWST_PBI0_A8 0x00000800 /* Row Start Address Bit is A8 */
468 #define ORxS_ROWST_PBI0_A9 0x00000c00 /* Row Start Address Bit is A9 */
469 #define ORxS_ROWST_PBI0_A10 0x00001000 /* Row Start Address Bit is A10 */
470 #define ORxS_ROWST_PBI0_A11 0x00001400 /* Row Start Address Bit is A11 */
471 #define ORxS_ROWST_PBI0_A12 0x00001800 /* Row Start Address Bit is A12 */
472 #define ORxS_ROWST_PBI0_A13 0x00001c00 /* Row Start Address Bit is A13 */
473
474 /* ROWST values for xSDMR[PBI] = 1 */
475 #define ORxS_ROWST_PBI1_A0 0x00000000 /* Row Start Address Bit is A0 */
476 #define ORxS_ROWST_PBI1_A1 0x00000200 /* Row Start Address Bit is A1 */
477 #define ORxS_ROWST_PBI1_A2 0x00000400 /* Row Start Address Bit is A2 */
478 #define ORxS_ROWST_PBI1_A3 0x00000600 /* Row Start Address Bit is A3 */
479 #define ORxS_ROWST_PBI1_A4 0x00000800 /* Row Start Address Bit is A4 */
480 #define ORxS_ROWST_PBI1_A5 0x00000a00 /* Row Start Address Bit is A5 */
481 #define ORxS_ROWST_PBI1_A6 0x00000c00 /* Row Start Address Bit is A6 */
482 #define ORxS_ROWST_PBI1_A7 0x00000e00 /* Row Start Address Bit is A7 */
483 #define ORxS_ROWST_PBI1_A8 0x00001000 /* Row Start Address Bit is A8 */
484 #define ORxS_ROWST_PBI1_A9 0x00001200 /* Row Start Address Bit is A9 */
485 #define ORxS_ROWST_PBI1_A10 0x00001400 /* Row Start Address Bit is A10 */
486 #define ORxS_ROWST_PBI1_A11 0x00001600 /* Row Start Address Bit is A11 */
487 #define ORxS_ROWST_PBI1_A12 0x00001800 /* Row Start Address Bit is A12 */
488
489 #define ORxS_NUMR_9 0x00000000 /* 9 Row Address Lines */
490 #define ORxS_NUMR_10 0x00000040 /* 10 Row Address Lines */
491 #define ORxS_NUMR_11 0x00000080 /* 11 Row Address Lines */
492 #define ORxS_NUMR_12 0x000000c0 /* 12 Row Address Lines */
493 #define ORxS_NUMR_13 0x00000100 /* 13 Row Address Lines */
494 #define ORxS_NUMR_14 0x00000140 /* 14 Row Address Lines */
495 #define ORxS_NUMR_15 0x00000180 /* 15 Row Address Lines */
496 #define ORxS_NUMR_16 0x000001c0 /* 16 Row Address Lines */
497
498 /* helper to determine the AM for a given size (SDRAM mode) */
499 #define ORxS_SIZE_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */
500
501 /*-----------------------------------------------------------------------
502 * ORx - Memory Controller: Option Register - GPCM Mode 10-18
503 */
504 #define ORxG_AM_MSK 0xffff8000 /* Address Mask Mask */
505 #define ORxG_BCTLD 0x00001000 /* Data Buffer Control Disable */
506 #define ORxG_CSNT 0x00000800 /* Chip Select Negation Time */
507 #define ORxG_ACS_MSK 0x00000600 /* Address to Chip Select Setup mask*/
508 #define ORxG_SCY_MSK 0x000000f0 /* Cycle Lenght in Clocks */
509 #define ORxG_SETA 0x00000008 /* External Access Termination */
510 #define ORxG_TRLX 0x00000004 /* Timing Relaxed */
511 #define ORxG_EHTR 0x00000002 /* Extended Hold Time on Read */
512
513 #define ORxG_ACS_DIV1 0x00000000 /* CS is output at the same time*/
514 #define ORxG_ACS_DIV4 0x00000400 /* CS is output 1/4 a clock later*/
515 #define ORxG_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later*/
516
517 #define ORxG_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */
518 #define ORxG_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */
519 #define ORxG_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */
520 #define ORxG_SCY_3_CLK 0x00000030 /* 3 clock cycles wait states */
521 #define ORxG_SCY_4_CLK 0x00000040 /* 4 clock cycles wait states */
522 #define ORxG_SCY_5_CLK 0x00000050 /* 5 clock cycles wait states */
523 #define ORxG_SCY_6_CLK 0x00000060 /* 6 clock cycles wait states */
524 #define ORxG_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */
525 #define ORxG_SCY_8_CLK 0x00000080 /* 8 clock cycles wait states */
526 #define ORxG_SCY_9_CLK 0x00000090 /* 9 clock cycles wait states */
527 #define ORxG_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */
528 #define ORxG_SCY_11_CLK 0x000000b0 /* 11 clock cycles wait states */
529 #define ORxG_SCY_12_CLK 0x000000c0 /* 12 clock cycles wait states */
530 #define ORxG_SCY_13_CLK 0x000000d0 /* 13 clock cycles wait states */
531 #define ORxG_SCY_14_CLK 0x000000e0 /* 14 clock cycles wait states */
532 #define ORxG_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */
533
534 /*-----------------------------------------------------------------------
535 * ORx - Memory Controller: Option Register - UPM Mode 10-20
536 */
537 #define ORxU_AM_MSK 0xffff8000 /* Address Mask Mask */
538 #define ORxU_BCTLD 0x00001000 /* Data Buffer Control Disable */
539 #define ORxU_BI 0x00000100 /* Burst Inhibit */
540 #define ORxU_EHTR_MSK 0x00000006 /* Extended Hold Time on Read Mask*/
541
542 #define ORxU_EHTR_NORM 0x00000000 /* Normal Timing */
543 #define ORxU_EHTR_1IDLE 0x00000002 /* One Idle Clock Cycle Inserted*/
544 #define ORxU_EHTR_4IDLE 0x00000004 /* Four Idle Clock Cycles Inserted*/
545 #define ORxU_EHTR_8IDLE 0x00000006 /* Eight Idle Clock Cycles Inserted*/
546
547
548 /* helpers to convert values into an OR address mask (GPCM mode) */
549 #define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */
550 #define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20)
551
552
553 /*-----------------------------------------------------------------------
554 * PSDMR - 60x SDRAM Mode Register 10-21
555 */
556 #define PSDMR_PBI 0x80000000 /* Page-based Interleaving */
557 #define PSDMR_RFEN 0x40000000 /* Refresh Enable */
558 #define PSDMR_OP_MSK 0x38000000 /* SDRAM Operation Mask */
559 #define PSDMR_SDAM_MSK 0x07000000 /* SDRAM Address Multiplex Mask */
560 #define PSDMR_BSMA_MSK 0x00e00000 /* Bank Select Muxd Addr Line Mask*/
561 #define PSDMR_SDA10_MSK 0x001c0000 /* A10 Control Mask */
562 #define PSDMR_RFRC_MSK 0x00038000 /* Refresh Recovery Mask */
563 #define PSDMR_PRETOACT_MSK 0x00007000 /* Precharge to Activate Intvl Mask*/
564 #define PSDMR_ACTTORW_MSK 0x00000e00 /* Activate to Read/Write Intvl Mask*/
565 #define PSDMR_BL 0x00000100 /* Burst Length */
566 #define PSDMR_LDOTOPRE_MSK 0x000000c0 /* Last Data Out to Precharge Mask*/
567 #define PSDMR_WRC_MSK 0x00000030 /* Write Recovery Time Mask */
568 #define PSDMR_EAMUX 0x00000008 /* External Address Multiplexing*/
569 #define PSDMR_BUFCMD 0x00000004 /* SDRAM ctl lines asrtd for 2 cycles*/
570 #define PSDMR_CL_MSK 0x00000003 /* CAS Latency Mask */
571
572 #define PSDMR_OP_NORM 0x00000000 /* Normal Operation */
573 #define PSDMR_OP_CBRR 0x08000000 /* CBR Refresh */
574 #define PSDMR_OP_SELFR 0x10000000 /* Self Refresh */
575 #define PSDMR_OP_MRW 0x18000000 /* Mode Register Write */
576 #define PSDMR_OP_PREB 0x20000000 /* Precharge Bank */
577 #define PSDMR_OP_PREA 0x28000000 /* Precharge All Banks */
578 #define PSDMR_OP_ACTB 0x30000000 /* Activate Bank */
579 #define PSDMR_OP_RW 0x38000000 /* Read/Write */
580
581 #define PSDMR_SDAM_A13_IS_A5 0x00000000 /* SDRAM Address Multiplex A13 is A5 */
582 #define PSDMR_SDAM_A14_IS_A5 0x01000000 /* SDRAM Address Multiplex A14 is A5 */
583 #define PSDMR_SDAM_A15_IS_A5 0x02000000 /* SDRAM Address Multiplex A15 is A5 */
584 #define PSDMR_SDAM_A16_IS_A5 0x03000000 /* SDRAM Address Multiplex A16 is A5 */
585 #define PSDMR_SDAM_A17_IS_A5 0x04000000 /* SDRAM Address Multiplex A17 is A5 */
586 #define PSDMR_SDAM_A18_IS_A5 0x05000000 /* SDRAM Address Multiplex A18 is A5 */
587
588 #define PSDMR_BSMA_A12_A14 0x00000000 /* A12 - A14 */
589 #define PSDMR_BSMA_A13_A15 0x00200000 /* A13 - A15 */
590 #define PSDMR_BSMA_A14_A16 0x00400000 /* A14 - A16 */
591 #define PSDMR_BSMA_A15_A17 0x00600000 /* A15 - A17 */
592 #define PSDMR_BSMA_A16_A18 0x00800000 /* A16 - A18 */
593 #define PSDMR_BSMA_A17_A19 0x00a00000 /* A17 - A19 */
594 #define PSDMR_BSMA_A18_A20 0x00c00000 /* A18 - A20 */
595 #define PSDMR_BSMA_A19_A21 0x00e00000 /* A19 - A21 */
596
597 /* SDA10 values for xSDMR[PBI] = 0 */
598 #define PSDMR_SDA10_PBI0_A12 0x00000000 /* "A10" Control is A12 */
599 #define PSDMR_SDA10_PBI0_A11 0x00040000 /* "A10" Control is A11 */
600 #define PSDMR_SDA10_PBI0_A10 0x00080000 /* "A10" Control is A10 */
601 #define PSDMR_SDA10_PBI0_A9 0x000c0000 /* "A10" Control is A9 */
602 #define PSDMR_SDA10_PBI0_A8 0x00100000 /* "A10" Control is A8 */
603 #define PSDMR_SDA10_PBI0_A7 0x00140000 /* "A10" Control is A7 */
604 #define PSDMR_SDA10_PBI0_A6 0x00180000 /* "A10" Control is A6 */
605 #define PSDMR_SDA10_PBI0_A5 0x001c0000 /* "A10" Control is A5 */
606
607 /* SDA10 values for xSDMR[PBI] = 1 */
608 #define PSDMR_SDA10_PBI1_A10 0x00000000 /* "A10" Control is A10 */
609 #define PSDMR_SDA10_PBI1_A9 0x00040000 /* "A10" Control is A9 */
610 #define PSDMR_SDA10_PBI1_A8 0x00080000 /* "A10" Control is A8 */
611 #define PSDMR_SDA10_PBI1_A7 0x000c0000 /* "A10" Control is A7 */
612 #define PSDMR_SDA10_PBI1_A6 0x00100000 /* "A10" Control is A6 */
613 #define PSDMR_SDA10_PBI1_A5 0x00140000 /* "A10" Control is A5 */
614 #define PSDMR_SDA10_PBI1_A4 0x00180000 /* "A10" Control is A4 */
615 #define PSDMR_SDA10_PBI1_A3 0x001c0000 /* "A10" Control is A3 */
616
617 #define PSDMR_RFRC_3_CLK 0x00008000 /* 3 Clocks */
618 #define PSDMR_RFRC_4_CLK 0x00010000 /* 4 Clocks */
619 #define PSDMR_RFRC_5_CLK 0x00018000 /* 5 Clocks */
620 #define PSDMR_RFRC_6_CLK 0x00020000 /* 6 Clocks */
621 #define PSDMR_RFRC_7_CLK 0x00028000 /* 7 Clocks */
622 #define PSDMR_RFRC_8_CLK 0x00030000 /* 8 Clocks */
623 #define PSDMR_RFRC_16_CLK 0x00038000 /* 16 Clocks */
624
625 #define PSDMR_PRETOACT_8W 0x00000000 /* 8 Clock-cycle Wait States */
626 #define PSDMR_PRETOACT_1W 0x00001000 /* 1 Clock-cycle Wait States */
627 #define PSDMR_PRETOACT_2W 0x00002000 /* 2 Clock-cycle Wait States */
628 #define PSDMR_PRETOACT_3W 0x00003000 /* 3 Clock-cycle Wait States */
629 #define PSDMR_PRETOACT_4W 0x00004000 /* 4 Clock-cycle Wait States */
630 #define PSDMR_PRETOACT_5W 0x00005000 /* 5 Clock-cycle Wait States */
631 #define PSDMR_PRETOACT_6W 0x00006000 /* 6 Clock-cycle Wait States */
632 #define PSDMR_PRETOACT_7W 0x00007000 /* 7 Clock-cycle Wait States */
633
634 #define PSDMR_ACTTORW_8W 0x00000000 /* 8 Clock-cycle Wait States */
635 #define PSDMR_ACTTORW_1W 0x00000200 /* 1 Clock-cycle Wait States */
636 #define PSDMR_ACTTORW_2W 0x00000400 /* 2 Clock-cycle Wait States */
637 #define PSDMR_ACTTORW_3W 0x00000600 /* 3 Clock-cycle Wait States */
638 #define PSDMR_ACTTORW_4W 0x00000800 /* 4 Clock-cycle Wait States */
639 #define PSDMR_ACTTORW_5W 0x00000a00 /* 5 Clock-cycle Wait States */
640 #define PSDMR_ACTTORW_6W 0x00000c00 /* 6 Clock-cycle Wait States */
641 #define PSDMR_ACTTORW_7W 0x00000e00 /* 7 Clock-cycle Wait States */
642
643 #define PSDMR_LDOTOPRE_0C 0x00000000 /* 0 Clock Cycles */
644 #define PSDMR_LDOTOPRE_1C 0x00000040 /* 1 Clock Cycles */
645 #define PSDMR_LDOTOPRE_2C 0x00000080 /* 2 Clock Cycles */
646
647 #define PSDMR_WRC_4C 0x00000000 /* 4 Clock Cycles */
648 #define PSDMR_WRC_1C 0x00000010 /* 1 Clock Cycles */
649 #define PSDMR_WRC_2C 0x00000020 /* 2 Clock Cycles */
650 #define PSDMR_WRC_3C 0x00000030 /* 3 Clock Cycles */
651
652 #define PSDMR_CL_1 0x00000001 /* CAS Latency = 1 */
653 #define PSDMR_CL_2 0x00000002 /* CAS Latency = 2 */
654 #define PSDMR_CL_3 0x00000003 /* CAS Latency = 3 */
655
656 /*-----------------------------------------------------------------------
657 * LSDMR - Local Bus SDRAM Mode Register 10-24
658 */
659
660 /*
661 * No definitions here - the LSDMR has the same fields as the PSDMR.
662 */
663
664 /*-----------------------------------------------------------------------
665 * MPTPR - Memory Refresh Timer Prescaler Register 10-32
666 * See User's Manual Errata for the changed definition (matches the
667 * 8xx now). The wrong prescaler definition causes excessive refreshes
668 * (typically "divide by 2" when "divide by 32" is intended) which will
669 * cause unnecessary memory subsystem slowdown.
670 */
671 #define MPTPR_PTP_MSK 0xff00 /* Periodic Timers Prescaler Mask */
672 #define MPTPR_PTP_DIV2 0x2000 /* BRGCLK divided by 2 */
673 #define MPTPR_PTP_DIV4 0x1000 /* BRGCLK divided by 4 */
674 #define MPTPR_PTP_DIV8 0x0800 /* BRGCLK divided by 8 */
675 #define MPTPR_PTP_DIV16 0x0400 /* BRGCLK divided by 16 */
676 #define MPTPR_PTP_DIV32 0x0200 /* BRGCLK divided by 32 */
677 #define MPTPR_PTP_DIV64 0x0100 /* BRGCLK divided by 64 */
678
679
680 /*-----------------------------------------------------------------------
681 * TGCR1/TGCR2 - Timer Global Configuration Registers 17-4
682 */
683 #define TGCR1_CAS2 0x80 /* Cascade Timer 1 and 2 */
684 #define TGCR1_STP2 0x20 /* Stop timer 2 */
685 #define TGCR1_RST2 0x10 /* Reset timer 2 */
686 #define TGCR1_GM1 0x08 /* Gate Mode for Pin 1 */
687 #define TGCR1_STP1 0x02 /* Stop timer 1 */
688 #define TGCR1_RST1 0x01 /* Reset timer 1 */
689 #define TGCR2_CAS4 0x80 /* Cascade Timer 3 and 4 */
690 #define TGCR2_STP4 0x20 /* Stop timer 4 */
691 #define TGCR2_RST4 0x10 /* Reset timer 4 */
692 #define TGCR2_GM2 0x08 /* Gate Mode for Pin 2 */
693 #define TGCR2_STP3 0x02 /* Stop timer 3 */
694 #define TGCR2_RST3 0x01 /* Reset timer 3 */
695
696
697 /*-----------------------------------------------------------------------
698 * TMR1-TMR4 - Timer Mode Registers 17-6
699 */
700 #define TMRx_PS_MSK 0xff00 /* Prescaler Value */
701 #define TMRx_CE_MSK 0x00c0 /* Capture Edge and Enable Interrupt*/
702 #define TMRx_OM 0x0020 /* Output Mode */
703 #define TMRx_ORI 0x0010 /* Output Reference Interrupt Enable*/
704 #define TMRx_FRR 0x0008 /* Free Run/Restart */
705 #define TMRx_ICLK_MSK 0x0006 /* Timer Input Clock Source mask */
706 #define TMRx_GE 0x0001 /* Gate Enable */
707
708 #define TMRx_CE_INTR_DIS 0x0000 /* Disable Interrupt on capture event*/
709 #define TMRx_CE_RISING 0x0040 /* Capture on Rising TINx edge only */
710 #define TMRx_CE_FALLING 0x0080 /* Capture on Falling TINx edge only */
711 #define TMRx_CE_ANY 0x00c0 /* Capture on any TINx edge */
712
713 #define TMRx_ICLK_IN_CAS 0x0000 /* Internally cascaded input */
714 #define TMRx_ICLK_IN_GEN 0x0002 /* Internal General system clock*/
715 #define TMRx_ICLK_IN_GEN_DIV16 0x0004 /* Internal General system clk div 16*/
716 #define TMRx_ICLK_TIN_PIN 0x0006 /* TINx pin */
717
718
719 /*-----------------------------------------------------------------------
720 * CMXFCR - CMX FCC Clock Route Register 15-12
721 */
722 #define CMXFCR_FC1 0x40000000 /* FCC1 connection */
723 #define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */
724 #define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */
725 #define CMXFCR_FC2 0x00400000 /* FCC2 connection */
726 #define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */
727 #define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */
728 #define CMXFCR_FC3 0x00004000 /* FCC3 connection */
729 #define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */
730 #define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */
731
732 #define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */
733 #define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */
734 #define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */
735 #define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */
736 #define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */
737 #define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */
738 #define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */
739 #define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */
740
741 #define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */
742 #define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */
743 #define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */
744 #define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */
745 #define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */
746 #define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */
747 #define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */
748 #define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */
749
750 #define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */
751 #define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */
752 #define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */
753 #define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */
754 #define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */
755 #define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */
756 #define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */
757 #define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */
758
759 #define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */
760 #define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */
761 #define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */
762 #define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */
763 #define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */
764 #define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */
765 #define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */
766 #define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */
767
768 #define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */
769 #define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */
770 #define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */
771 #define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */
772 #define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */
773 #define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */
774 #define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */
775 #define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */
776
777 #define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */
778 #define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */
779 #define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */
780 #define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */
781 #define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */
782 #define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */
783 #define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */
784 #define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */
785
786 /*-----------------------------------------------------------------------
787 * CMXSCR - CMX SCC Clock Route Register 15-14
788 */
789 #define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */
790 #define CMXSCR_SC1 0x40000000 /* SCC1 connection */
791 #define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */
792 #define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */
793 #define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */
794 #define CMXSCR_SC2 0x00400000 /* SCC2 connection */
795 #define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */
796 #define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */
797 #define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */
798 #define CMXSCR_SC3 0x00004000 /* SCC3 connection */
799 #define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */
800 #define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */
801 #define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */
802 #define CMXSCR_SC4 0x00000040 /* SCC4 connection */
803 #define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */
804 #define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */
805
806 #define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */
807 #define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */
808 #define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */
809 #define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */
810 #define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */
811 #define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */
812 #define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */
813 #define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */
814
815 #define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */
816 #define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */
817 #define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */
818 #define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */
819 #define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */
820 #define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */
821 #define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */
822 #define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */
823
824 #define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */
825 #define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */
826 #define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */
827 #define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */
828 #define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */
829 #define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */
830 #define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */
831 #define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */
832
833 #define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */
834 #define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */
835 #define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */
836 #define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */
837 #define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */
838 #define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */
839 #define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */
840 #define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */
841
842 #define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */
843 #define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */
844 #define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */
845 #define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */
846 #define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */
847 #define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */
848 #define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */
849 #define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */
850
851 #define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */
852 #define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */
853 #define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */
854 #define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */
855 #define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */
856 #define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */
857 #define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */
858 #define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */
859
860 #define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */
861 #define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */
862 #define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */
863 #define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */
864 #define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */
865 #define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */
866 #define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */
867 #define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */
868
869 #define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */
870 #define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */
871 #define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */
872 #define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */
873 #define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */
874 #define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */
875 #define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */
876 #define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */
877
878 /*-----------------------------------------------------------------------
879 * CMXSMR - CMX SMC Clock Route Register 15-17
880 */
881 #define CMXSMR_SMC1 0x80 /* SMC1 Connection */
882 #define CMXSMR_SMC1CS_MSK 0x30 /* SMC1 Clock Source */
883 #define CMXSMR_SMC2 0x08 /* SMC2 Connection */
884 #define CMXSMR_SMC2CS_MSK 0x03 /* SMC2 Clock Source */
885
886 #define CMXSMR_SMC1CS_BRG1 0x00 /* SMC1 Tx and Rx Clocks are BRG1 */
887 #define CMXSMR_SMC1CS_BRG7 0x10 /* SMC1 Tx and Rx Clocks are BRG7 */
888 #define CMXSMR_SMC1CS_CLK7 0x20 /* SMC1 Tx and Rx Clocks are CLK7 */
889 #define CMXSMR_SMC1CS_CLK9 0x30 /* SMC1 Tx and Rx Clocks are CLK9 */
890
891 #define CMXSMR_SMC2CS_BRG2 0x00 /* SMC2 Tx and Rx Clocks are BRG2 */
892 #define CMXSMR_SMC2CS_BRG8 0x01 /* SMC2 Tx and Rx Clocks are BRG8 */
893 #define CMXSMR_SMC2CS_CLK19 0x02 /* SMC2 Tx and Rx Clocks are CLK19 */
894 #define CMXSMR_SMC2CS_CLK20 0x03 /* SMC2 Tx and Rx Clocks are CLK20 */
895
896 /*-----------------------------------------------------------------------
897 * miscellaneous
898 */
899
900 #define UPMA 1
901 #define UPMB 2
902 #define UPMC 3
903
904 #if !defined(__ASSEMBLY__) && defined(CONFIG_WATCHDOG)
905 extern __inline__ void
906 reset_8260_watchdog(volatile immap_t *immr)
907 {
908 immr->im_siu_conf.sc_swsr = 0x556c;
909 immr->im_siu_conf.sc_swsr = 0xaa39;
910 }
911 #endif /* !__ASSEMBLY && CONFIG_WATCHDOG */
912
913 #endif /* __MPC8260_H__ */