include/mvebu_mmc.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Marvell MMC/SD/SDIO driver
   4  *
   5  * (C) Copyright 2012
   6  * Marvell Semiconductor <www.marvell.com>
   7  * Written-by: Maen Suleiman, Gerald Kerma
   8  */
   9
  10 #ifndef __MVEBU_MMC_H__
  11 #define __MVEBU_MMC_H__
  12
  13 /* needed for the mmc_cfg definition */
  14 #include <mmc.h>
  15
  16 #define MMC_BLOCK_SIZE                          512
  17
  18 /*
  19  * Clock rates
  20  */
  21
  22 #define MVEBU_MMC_CLOCKRATE_MAX                 50000000
  23 #define MVEBU_MMC_BASE_DIV_MAX                  0x7ff
  24 #define MVEBU_MMC_BASE_FAST_CLOCK               CONFIG_SYS_TCLK
  25 #define MVEBU_MMC_BASE_FAST_CLK_100             100000000
  26 #define MVEBU_MMC_BASE_FAST_CLK_200             200000000
  27
  28 /* SDIO register */
  29 #define SDIO_SYS_ADDR_LOW                       0x000
  30 #define SDIO_SYS_ADDR_HI                        0x004
  31 #define SDIO_BLK_SIZE                           0x008
  32 #define SDIO_BLK_COUNT                          0x00c
  33 #define SDIO_ARG_LOW                            0x010
  34 #define SDIO_ARG_HI                             0x014
  35 #define SDIO_XFER_MODE                          0x018
  36 #define SDIO_CMD                                0x01c
  37 #define SDIO_RSP(i)                             (0x020 + ((i)<<2))
  38 #define SDIO_RSP0                               0x020
  39 #define SDIO_RSP1                               0x024
  40 #define SDIO_RSP2                               0x028
  41 #define SDIO_RSP3                               0x02c
  42 #define SDIO_RSP4                               0x030
  43 #define SDIO_RSP5                               0x034
  44 #define SDIO_RSP6                               0x038
  45 #define SDIO_RSP7                               0x03c
  46 #define SDIO_BUF_DATA_PORT                      0x040
  47 #define SDIO_RSVED                              0x044
  48 #define SDIO_HW_STATE                           0x048
  49 #define SDIO_PRESENT_STATE0                     0x048
  50 #define SDIO_PRESENT_STATE1                     0x04c
  51 #define SDIO_HOST_CTRL                          0x050
  52 #define SDIO_BLK_GAP_CTRL                       0x054
  53 #define SDIO_CLK_CTRL                           0x058
  54 #define SDIO_SW_RESET                           0x05c
  55 #define SDIO_NOR_INTR_STATUS                    0x060
  56 #define SDIO_ERR_INTR_STATUS                    0x064
  57 #define SDIO_NOR_STATUS_EN                      0x068
  58 #define SDIO_ERR_STATUS_EN                      0x06c
  59 #define SDIO_NOR_INTR_EN                        0x070
  60 #define SDIO_ERR_INTR_EN                        0x074
  61 #define SDIO_AUTOCMD12_ERR_STATUS               0x078
  62 #define SDIO_CURR_BYTE_LEFT                     0x07c
  63 #define SDIO_CURR_BLK_LEFT                      0x080
  64 #define SDIO_AUTOCMD12_ARG_LOW                  0x084
  65 #define SDIO_AUTOCMD12_ARG_HI                   0x088
  66 #define SDIO_AUTOCMD12_INDEX                    0x08c
  67 #define SDIO_AUTO_RSP(i)                        (0x090 + ((i)<<2))
  68 #define SDIO_AUTO_RSP0                          0x090
  69 #define SDIO_AUTO_RSP1                          0x094
  70 #define SDIO_AUTO_RSP2                          0x098
  71 #define SDIO_CLK_DIV                            0x128
  72
  73 #define WINDOW_CTRL(i)                          (0x108 + ((i) << 3))
  74 #define WINDOW_BASE(i)                          (0x10c + ((i) << 3))
  75
  76 /* SDIO_PRESENT_STATE */
  77 #define CARD_BUSY                               (1 << 1)
  78 #define CMD_INHIBIT                             (1 << 0)
  79 #define CMD_TXACTIVE                            (1 << 8)
  80 #define CMD_RXACTIVE                            (1 << 9)
  81 #define CMD_FIFO_EMPTY                          (1 << 13)
  82 #define CMD_AUTOCMD12ACTIVE                     (1 << 14)
  83 #define CMD_BUS_BUSY                            (CMD_AUTOCMD12ACTIVE |  \
  84                                                 CMD_RXACTIVE |  \
  85                                                 CMD_TXACTIVE |  \
  86                                                 CMD_INHIBIT |   \
  87                                                 CARD_BUSY)
  88
  89 /*
  90  * SDIO_CMD
  91  */
  92
  93 #define SDIO_CMD_RSP_NONE                       (0 << 0)
  94 #define SDIO_CMD_RSP_136                        (1 << 0)
  95 #define SDIO_CMD_RSP_48                         (2 << 0)
  96 #define SDIO_CMD_RSP_48BUSY                     (3 << 0)
  97
  98 #define SDIO_CMD_CHECK_DATACRC16                (1 << 2)
  99 #define SDIO_CMD_CHECK_CMDCRC                   (1 << 3)
 100 #define SDIO_CMD_INDX_CHECK                     (1 << 4)
 101 #define SDIO_CMD_DATA_PRESENT                   (1 << 5)
 102 #define SDIO_UNEXPECTED_RESP                    (1 << 7)
 103
 104 #define SDIO_CMD_INDEX(x)                       ((x) << 8)
 105
 106 /*
 107  * SDIO_XFER_MODE
 108  */
 109
 110 #define SDIO_XFER_MODE_STOP_CLK                 (1 << 5)
 111 #define SDIO_XFER_MODE_HW_WR_DATA_EN            (1 << 1)
 112 #define SDIO_XFER_MODE_AUTO_CMD12               (1 << 2)
 113 #define SDIO_XFER_MODE_INT_CHK_EN               (1 << 3)
 114 #define SDIO_XFER_MODE_TO_HOST                  (1 << 4)
 115 #define SDIO_XFER_MODE_DMA                      (0 << 6)
 116
 117 /*
 118  * SDIO_HOST_CTRL
 119  */
 120
 121 #define SDIO_HOST_CTRL_PUSH_PULL_EN             (1 << 0)
 122
 123 #define SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY       (0 << 1)
 124 #define SDIO_HOST_CTRL_CARD_TYPE_IO_ONLY        (1 << 1)
 125 #define SDIO_HOST_CTRL_CARD_TYPE_IO_MEM_COMBO   (2 << 1)
 126 #define SDIO_HOST_CTRL_CARD_TYPE_IO_MMC         (3 << 1)
 127 #define SDIO_HOST_CTRL_CARD_TYPE_MASK           (3 << 1)
 128
 129 #define SDIO_HOST_CTRL_BIG_ENDIAN               (1 << 3)
 130 #define SDIO_HOST_CTRL_LSB_FIRST                (1 << 4)
 131 #define SDIO_HOST_CTRL_DATA_WIDTH_1_BIT         (0 << 9)
 132 #define SDIO_HOST_CTRL_DATA_WIDTH_4_BITS        (1 << 9)
 133 #define SDIO_HOST_CTRL_HI_SPEED_EN              (1 << 10)
 134
 135 #define SDIO_HOST_CTRL_TMOUT_MAX                0xf
 136 #define SDIO_HOST_CTRL_TMOUT_MASK               (0xf << 11)
 137 #define SDIO_HOST_CTRL_TMOUT(x)                 ((x) << 11)
 138 #define SDIO_HOST_CTRL_TMOUT_EN                 (1 << 15)
 139
 140 /*
 141  * SDIO_SW_RESET
 142  */
 143
 144 #define SDIO_SW_RESET_NOW                       (1 << 8)
 145
 146 /*
 147  * Normal interrupt status bits
 148  */
 149
 150 #define SDIO_NOR_ERROR                          (1 << 15)
 151 #define SDIO_NOR_UNEXP_RSP                      (1 << 14)
 152 #define SDIO_NOR_AUTOCMD12_DONE                 (1 << 13)
 153 #define SDIO_NOR_SUSPEND_ON                     (1 << 12)
 154 #define SDIO_NOR_LMB_FF_8W_AVAIL                (1 << 11)
 155 #define SDIO_NOR_LMB_FF_8W_FILLED               (1 << 10)
 156 #define SDIO_NOR_READ_WAIT_ON                   (1 << 9)
 157 #define SDIO_NOR_CARD_INT                       (1 << 8)
 158 #define SDIO_NOR_READ_READY                     (1 << 5)
 159 #define SDIO_NOR_WRITE_READY                    (1 << 4)
 160 #define SDIO_NOR_DMA_INI                        (1 << 3)
 161 #define SDIO_NOR_BLK_GAP_EVT                    (1 << 2)
 162 #define SDIO_NOR_XFER_DONE                      (1 << 1)
 163 #define SDIO_NOR_CMD_DONE                       (1 << 0)
 164
 165 /*
 166  * Error status bits
 167  */
 168
 169 #define SDIO_ERR_CRC_STATUS                     (1 << 14)
 170 #define SDIO_ERR_CRC_STARTBIT                   (1 << 13)
 171 #define SDIO_ERR_CRC_ENDBIT                     (1 << 12)
 172 #define SDIO_ERR_RESP_TBIT                      (1 << 11)
 173 #define SDIO_ERR_XFER_SIZE                      (1 << 10)
 174 #define SDIO_ERR_CMD_STARTBIT                   (1 << 9)
 175 #define SDIO_ERR_AUTOCMD12                      (1 << 8)
 176 #define SDIO_ERR_DATA_ENDBIT                    (1 << 6)
 177 #define SDIO_ERR_DATA_CRC                       (1 << 5)
 178 #define SDIO_ERR_DATA_TIMEOUT                   (1 << 4)
 179 #define SDIO_ERR_CMD_INDEX                      (1 << 3)
 180 #define SDIO_ERR_CMD_ENDBIT                     (1 << 2)
 181 #define SDIO_ERR_CMD_CRC                        (1 << 1)
 182 #define SDIO_ERR_CMD_TIMEOUT                    (1 << 0)
 183 /* enable all for polling */
 184 #define SDIO_POLL_MASK                          0xffff
 185
 186 /*
 187  * CMD12 error status bits
 188  */
 189
 190 #define SDIO_AUTOCMD12_ERR_NOTEXE               (1 << 0)
 191 #define SDIO_AUTOCMD12_ERR_TIMEOUT              (1 << 1)
 192 #define SDIO_AUTOCMD12_ERR_CRC                  (1 << 2)
 193 #define SDIO_AUTOCMD12_ERR_ENDBIT               (1 << 3)
 194 #define SDIO_AUTOCMD12_ERR_INDEX                (1 << 4)
 195 #define SDIO_AUTOCMD12_ERR_RESP_T_BIT           (1 << 5)
 196 #define SDIO_AUTOCMD12_ERR_RESP_STARTBIT        (1 << 6)
 197
 198 #define MMC_RSP_PRESENT                         (1 << 0)
 199 /* 136 bit response */
 200 #define MMC_RSP_136                             (1 << 1)
 201 /* expect valid crc */
 202 #define MMC_RSP_CRC                             (1 << 2)
 203 /* card may send busy */
 204 #define MMC_RSP_BUSY                            (1 << 3)
 205 /* response contains opcode */
 206 #define MMC_RSP_OPCODE                          (1 << 4)
 207
 208 #define MMC_BUSMODE_OPENDRAIN                   1
 209 #define MMC_BUSMODE_PUSHPULL                    2
 210
 211 #define MMC_BUS_WIDTH_1                         0
 212 #define MMC_BUS_WIDTH_4                         2
 213 #define MMC_BUS_WIDTH_8                         3
 214
 215 /* Can the host do 4 bit transfers */
 216 #define MMC_CAP_4_BIT_DATA                      (1 << 0)
 217 /* Can do MMC high-speed timing */
 218 #define MMC_CAP_MMC_HIGHSPEED                   (1 << 1)
 219 /* Can do SD high-speed timing */
 220 #define MMC_CAP_SD_HIGHSPEED                    (1 << 2)
 221 /* Can signal pending SDIO IRQs */
 222 #define MMC_CAP_SDIO_IRQ                        (1 << 3)
 223 /* Talks only SPI protocols */
 224 #define MMC_CAP_SPI                             (1 << 4)
 225 /* Can the host do 8 bit transfers */
 226 #define MMC_CAP_8_BIT_DATA                      (1 << 6)
 227
 228 /* Waits while card is busy */
 229 #define MMC_CAP_WAIT_WHILE_BUSY                 (1 << 9)
 230 /* Allow erase/trim commands */
 231 #define MMC_CAP_ERASE                           (1 << 10)
 232 /* can support DDR mode at 1.8V */
 233 #define MMC_CAP_1_8V_DDR                        (1 << 11)
 234 /* can support DDR mode at 1.2V */
 235 #define MMC_CAP_1_2V_DDR                        (1 << 12)
 236 /* Can power off after boot */
 237 #define MMC_CAP_POWER_OFF_CARD                  (1 << 13)
 238 /* CMD14/CMD19 bus width ok */
 239 #define MMC_CAP_BUS_WIDTH_TEST                  (1 << 14)
 240 /* Host supports UHS SDR12 mode */
 241 #define MMC_CAP_UHS_SDR12                       (1 << 15)
 242 /* Host supports UHS SDR25 mode */
 243 #define MMC_CAP_UHS_SDR25                       (1 << 16)
 244 /* Host supports UHS SDR50 mode */
 245 #define MMC_CAP_UHS_SDR50                       (1 << 17)
 246 /* Host supports UHS SDR104 mode */
 247 #define MMC_CAP_UHS_SDR104                      (1 << 18)
 248 /* Host supports UHS DDR50 mode */
 249 #define MMC_CAP_UHS_DDR50                       (1 << 19)
 250 /* Host supports Driver Type A */
 251 #define MMC_CAP_DRIVER_TYPE_A                   (1 << 23)
 252 /* Host supports Driver Type C */
 253 #define MMC_CAP_DRIVER_TYPE_C                   (1 << 24)
 254 /* Host supports Driver Type D */
 255 #define MMC_CAP_DRIVER_TYPE_D                   (1 << 25)
 256 /* CMD23 supported. */
 257 #define MMC_CAP_CMD23                           (1 << 30)
 258 /* Hardware reset */
 259 #define MMC_CAP_HW_RESET                        (1 << 31)
 260
 261 struct mvebu_mmc_cfg {
 262         u32     mvebu_mmc_base;
 263         u32     mvebu_mmc_clk;
 264         u8      max_bus_width;
 265         struct mmc_config cfg;
 266 };
 267
 268 /*
 269  * Functions prototypes
 270  */
 271
 272 int mvebu_mmc_init(bd_t *bis);
 273
 274 #endif /* __MVEBU_MMC_H__ */